JPH02101672U - - Google Patents
Info
- Publication number
- JPH02101672U JPH02101672U JP995789U JP995789U JPH02101672U JP H02101672 U JPH02101672 U JP H02101672U JP 995789 U JP995789 U JP 995789U JP 995789 U JP995789 U JP 995789U JP H02101672 U JPH02101672 U JP H02101672U
- Authority
- JP
- Japan
- Prior art keywords
- horizontal deflection
- fet
- turn
- during
- gate signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Details Of Television Scanning (AREA)
Description
第１図はこの考案の実施例である水平偏向回路
の回路図、第２図はその各部の波形図である。第
３図はこの考案に係る水平偏向回路と従来の水平
偏向回路の損失を比較した図である。第４図およ
び第５図は従来の水平偏向回路およびその各部の
波形図である。第６図は従来技術による水平偏向
回路の回路図である。
Ｑ１……ＦＥＴ、Ｃ１……共振コンデンサ、Ｌ
ｙ……水平偏向コイル、Ｃ２……Ｓ字補正コンデ
ンサ、Ｌ１……フライバツクトランス、水平出力
トランス、Ｄ１……ダンパーダイオード。
FIG. 1 is a circuit diagram of a horizontal deflection circuit which is an embodiment of this invention, and FIG. 2 is a waveform diagram of each part thereof. FIG. 3 is a diagram comparing the losses of the horizontal deflection circuit according to this invention and the conventional horizontal deflection circuit. 4 and 5 are waveform diagrams of a conventional horizontal deflection circuit and its various parts. FIG. 6 is a circuit diagram of a horizontal deflection circuit according to the prior art. Q1...FET, C1...Resonance capacitor, L
y...Horizontal deflection coil, C2...S-shaped correction capacitor, L1...flyback transformer, horizontal output transformer, D1...damper diode.
Claims (1)
るとともに、前記水平偏向コイルに対してＦＥＴ
を直接接続してなる水平偏向コイル駆動回路と、 前記ＦＥＴを水平帰線期間のみオフさせ、他の
期間にオンさせるゲート信号を発生するゲート信
号発生回路とからなる水平偏向回路。[Claims for Utility Model Registration] A resonant capacitor is provided in parallel to the horizontal deflection coil, and an FET is connected to the horizontal deflection coil.
and a gate signal generation circuit that generates a gate signal to turn off the FET only during the horizontal retrace period and turn it on during other periods.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP995789U JPH02101672U (en) | 1989-01-30 | 1989-01-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP995789U JPH02101672U (en) | 1989-01-30 | 1989-01-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02101672U true JPH02101672U (en) | 1990-08-13 |
Family
ID=31217163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP995789U Pending JPH02101672U (en) | 1989-01-30 | 1989-01-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02101672U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5685979A (en) * | 1979-11-14 | 1981-07-13 | Tektronix Inc | Deflecting circuit |
-
1989
- 1989-01-30 JP JP995789U patent/JPH02101672U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5685979A (en) * | 1979-11-14 | 1981-07-13 | Tektronix Inc | Deflecting circuit |