JPH0198186A - Synchronous type storage device - Google Patents

Abstract

PURPOSE:To reduce consumption power by precharging only a part of bit lines including a bit line selected at least by means of an address signal base on a precharge signal and the address signal. CONSTITUTION:When precharge is started, the precharge signal 41 is inputted to an X decoder 42 at the time of '1' are word lines 9 and 10 go to a non-active state. Since a precharge control circuit 44 outputs an AND signal between the signal 41 and bit line selection signals 27 and 28, transistor TR control signals 45 and 46 show '1' and '0'. Consequently, only the precharge TRs 33 and 34 of bit lines 1 and 2 which require precharge are conducted, and precharge starts only with respect to the bit lines 1 and 2. When precharge terminates, the signal 41 shows '0', and the signals 45 and 46 being the outputs of the circuit 44 show '0'. Consequently, TRs 33, 34-36 become non-conductive and precharge terminates.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to reducing power consumption in a memory device (synchronous memory device) in which bit lines are precharged.

[Conventional technology]

FIG. 6 is a block diagram showing a conventional synchronous storage device. In the figure, 1, 2, 3, and 4 are bit lines, 9 and 10 are word lines, 11, 12, 13, and 14 are memory cells, 60 is a power supply, and 61, 62, 63, and 64 are made conductive by a precharge signal 66. 65 is a control circuit that outputs a precharge signal 66 in response to a chip enable signal 71; 67 and 68 output control signals 69 and 70 when the potentials of bit lines 1, 2, 3 and 4 reach a predetermined level; This is a level detector that outputs. Although not shown in the same figure, bit lines 1, 2, 3 and 4
is connected to the sense amplifier via a transistor turned on by a bit line selection signal and a common data line.

Next, the operation of the synchronous storage device configured as described above will be explained. The control circuit 65 receives the chip enable signal 7
When 1 is input, a precharge signal 66 is output, and this signal 66 causes the precharge transistors 61 and 62 to be activated.
．． 63 and 64 are rendered conductive, and precharging of bit lines 1, 2, 3, and 4 is started. And level detector 67
and 68 detect the levels of bit lines 1, 2, 3 and 4, and when the levels reach a predetermined level, control signal 6 is output.
Outputs 9 and 70. The control circuit 65 receives this control signal 6
9 and 70, the output of the precharge signal 66 is stopped. Therefore, the precharge transistor 61.62
．． 63 and 64 become non-conductive, and the precharging of bit lines 1, 2, 3 and 4 ends.

[Problem to be solved by the invention]

Since the conventional synchronous memory device is configured as described above, all the bit lines 1, 2, 3, and 4 are connected to the precharging transistors 61, 6, and 6, which are turned on by the same control signal 66.
It is precharged by 62, 63 and 64. Therefore, even if only bit lines 1 and 2 are selected and this set of bit line data is transferred to the output circuit, the unselected bit lines 3 and 4 are also precharged. Therefore, there is a problem in that unnecessary precharging is performed on the bit lines 3 and 4, which hinders reduction in power consumption.

This invention was made to solve the above-mentioned problems, and precharges only some bit lines, including at least the bit line selected according to the address signal, and precharges all the bit lines, unlike the conventional method. The purpose is to reduce power consumption by not uniformly precharging the battery.

[Means to solve the problem]

This invention selects a bit line according to an address signal,
In a synchronous memory device that performs precharging while controlling the precharge timing of the bit line in accordance with a precharge signal, based on the precharge signal and the address signal, at least a portion including the selected bit line A precharging means is provided for precharging only the bit lines.

[Effect]

The precharging means in this invention precharges only some of the bit lines, including at least the bit line selected according to the address signal, based on the precharge signal and the address signal. Precharging is not performed unnecessarily.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a synchronous storage device according to the present invention.

In the same figure, 1.2.3 and 4 are bit lines, 9 and 1
0 is a word line, 11.12.13 and 14 are memory cells, 19. ．． 20.21 and 22 are bit line selection signals 27
Bit line selection transistors 33, 34, 35 and 36 are turned on by precharging transistor control signals 45 and 46, and precharging bit lines 1, 2, 3 and 4 are turned on. transistors 41 for bit lines 1, 2, 3 and 4
A precharge signal 42 that controls the precharge timing of the precharge signal 42 does not decode the X address signal 55 when the precharge signal 41 is "1", and decodes the X address signal 55 when the precharge signal 41 is "0". , an X decoder that controls the word lines 9 and 10, 43 a Y decoder that controls the bit line selection signals 27 and 28 based on the Y address signal 53, and 44 a Y decoder that controls the bit line selection signals 27 and 28.
and a precharge signal 41 as precharge transistor control signals 45 and 46, respectively, and a precharge control circuit that controls the precharge transistors 33, 34, 35 and 36, 47 is a sense amplifier, 48 and 49 is connected between bit lines 1 and 2 and 3 and 4, respectively, to make the levels of bit lines 1 and 2 and 3 and 4 the same, and when reading data after precharging, the memory cell is Equalizing transistor for preventing data rewriting, 56
and 57, when the bit lines 1, 2, 3 and 4 cannot be completely precharged during the precharge period and the common data lines 31 and 32 are connected to the bit lines with incomplete precharging, the common data line 31 and a level compensation transistor 58 which compensates the potential of 32 to prevent malfunction of the sense amplifier 47, and 58 is a common data I! When the selected bit lines 1 and 2 or 3 and 4 are connected between the common data lines 31 and 32 and are connected to the common data line 31 and 32, the equalizing transistors 48 and 49 are turned on at the same timing. The common data lines 31° and 32 are equalized and the common data Ii! This is an equalizing transistor that more quickly equalizes the bit line 1.2 or the bit line 3.4 connected to the bit line 31.32. 60 is a power supply, 61 is a precharge means, a precharge control circuit 44 and precharge transistors 33, 34, 35.
and 36 and a power supply 60.

Next, the operation of the synchronous storage device configured as described above will be explained.

Table 1 shows the output of the Y decoder in response to the Y address signal 53, that is, the states of the bit line selection signals 27 and 28.

Table 1 Below, when Y7 address signal 53 is O'', bit line selection signal 2
The case where 7 and 28 are "1" and "0" respectively will be explained. Since the bit line selection signal 27 is "1", the bit line selection transistors 19 and 20 are conductive, and the bit lines 1 and 2 are connected to the common data lines 31 and 32. on the other hand,
Since the bit line selection signal 28 is OTl, the bit line selection transistors 21 and 22 are non-conductive, and the bit lines 3 and 4 are not connected to the common data lines 31 and 32.

Therefore, bit lines 1 and 2 require precharging because they are connected to memory cells 11 or 12 to be accessed, but bit lines 3 and 4 are not connected to memory cells 11 or 12 to be accessed. Therefore, precharging is unnecessary.

A case where precharging is started in the above state will be described. In this case, the precharge signal 41 is 1
” and is input to the X decoder 42. At this time, the X decoder 42 does not decode the X address signal 55, so
Word lines 9 and 1O become inactive.

Since the precharge control circuit 44 outputs an AND signal of the precharge signal 41 and the bit line selection signals 27 and 28, in the current state, the precharge transistor control signals 45 and 46 are "1" and "0", respectively. Therefore, only the precharging transistors 33 and 34 of the bit lines 1 and 2 that require precharging are made conductive, and precharging is started only on the bit lines 1 and 2.At this point, as shown in FIG. It is T1.

Next, a case where precharging is completed will be explained. In this case, the precharge signal 41 becomes "0". Since the precharge control circuit 44 outputs an AND signal of the precharge signal 41 and the bit line selection signals 27 and 28, when the precharge signal 41 is "0", the precharge control circuit 44 outputs the precharge signal. The charging transistor control signals 45 and 46 both become "0". Therefore, precharging transistors 33, 34, 35 and 3
6 becomes non-conductive, and precharging ends.

This time point is T2 in FIG. 2, and is the time point when the bit lines 9 and 10 are completely precharged. In FIG. 2, the complete precharge voltage is 5V.

On the other hand, the precharge signal 41 of “0” is sent to the X decoder 42
In response to this, the X decoder 42 is activated, decodes the X address signal 55, and outputs it. Table 2 shows the output states of the X decoder 42 to the word lines 9 and 10 in response to the X address signal 55.

Table 2 Below, when the X address signal 55 is "0", the output of the X decoder 42 to word lines 9 and 10 is $111Z&IQ respectively.
'' case will be explained. In this state, only the word line 9 is in the active state. Information on the memory cells 11 connected to the word line 9 in the active state and the bit lines 1 and 2 for which pre-charging has been completed is , bit line selection transistors 19 and 2 are conductive as described above.
0 to the common data lines 31 and 32. The data read start point is T2 in FIG. 2, which is the same timing as the end of precharge described above.

Next, the equalizing transistors 48 and 49 will be explained. The equalizing signal 52 output during the precharge period is input to the gates of the equalizing transistors 48 and 49, and in response to this, the equalizing transistors 48 and 49 conduct during the precharging, and the bit lines 1 and 2 are connected to each other. The levels between bit lines 1 and 2 and between bit lines 3 and 4 are made the same to prevent memory cell data from being rewritten due to level differences between bit lines 1 and 2 and between bit lines 3 and 4 when reading data after precharging.

Next, the equalizing transistor 58 will be explained. As described above, equalizing transistors 48 and 49 are provided to equalize the level of the selected bit line 1.2 or 3.4 during the precharge period. When equalizing the bit lines 1.2 and 3.4, it takes time to equalize because these bit lines are long. Therefore, an equalizing transistor 58 is provided, and by inputting the equalizing signal 52 output during the precharge period to its gate, the equalizing transistor 58 is made conductive at the same timing as the equalizing transistors 48 and 49 are made conductive. Bit lines 1.2 or 3. which equalize the data lines 31 and 32 and are connected to the common data lines 31 and 32.
4 equalization was made faster.

Next, the level compensation transistors 56 and 57 will be explained using FIGS. 2, 3, and 4. In the figure, T1 is the precharge start time, T2 is the complete precharge end time and data readout start time, T3 is the incomplete precharge end time and data readout start time, T4 is the level compensation start time, and vth is the time of the sense amplifier 47. Threshold value 2th56 is the threshold value of level compensation transistor 56.

Now, the case where the common data lines 31 and 32 are at high level and low level, respectively, will be described. For example, assume that the precharge period is short and the precharge ends at time T3. In FIG. 3, the level of the common data line 31 has not reached 5V, and the precharge is not complete. Therefore, the data read margin, which is determined by the difference between the level of the common data line 31 and the threshold value vth of the sense amplifier 47, is determined by the difference between the level of the common data line 31 and the threshold value vth of the sense amplifier 47, when it is completely precharged (Fig. 2).
smaller than that of In this case, there is a high possibility that the sense amplifier 47 may malfunction and read incorrect data, which lowers the reliability of the read data.

Therefore, as shown in FIG. 4, the level of the common data line 32 is set to the threshold value
56 or less, that is, after time T4, the level compensation transistor 56 becomes conductive, connects the common data line 31 to the power supply 60, and compensates the level of the common data line 31 up to 5■. As a result, common data line 31
The data read margin determined by the difference between the level of Vth and the threshold value vth of the sense amplifier 47 is the same as that in the case of complete precharging (Fig. 2), and the sense amplifier 47 malfunctions and generates incorrect data. No more reading.

Note that when the common data lines 31 and 32 are at low level and high level, respectively, and the precharging of the bit line is incomplete, the level compensation transistor 57 becomes conductive.
The level of the common data line 32 is compensated.

FIG. 5 is a diagram showing another embodiment of the synchronous storage device according to the present invention. In the figure, only the parts that are different from or added to the configuration in Figure 1 will be explained.
．． 7 and 8 are bit lines, 15, 16, 17 and 18 are memory cells, 23, 24, 25 and 26 are bit line selection transistors, 37, 38, 39 and 40 are precharge transistors, 44t) are precharge signals 41 is 0
”, the precharge transistor control signals 45 and 46 of “0” are output, and the precharge signal 41 is “1”.
At this time, the address signal 53 is output to the precharge transistor control signal 46, the inverted signal of the address signal 53 is output to the precharge transistor control signal 45, and the precharge transistors 33, 34, 35, 36
．． 37, 38, a precharge control circuit that controls 39 and 40, 50 and 51 equalizing transistors, 5
4 is a Y address signal. The other configurations and respective functions are the same as in the previous embodiment.

Next, the operation of the synchronous storage device configured as above will be explained. Y for Y address signals 53 and 54
Decoder outputs, that is, bit line selection signals 27, 28 .
Table 3 shows the conditions of Nos. 29 and 30.

(Left below) Table 3 Below, Y address signals 53 and 54 are "1" and ", respectively.
The case where the bit line selection signals 27, 28, 29 and 30 are respectively "0", "1", "0" and "0" will be explained. Since only the bit line selection signal 28 is "1", only the bit line selection transistors 21 and 22 are conductive, and only the bit lines 3 and 4 are connected to the common data lines 31 and 32.

Therefore, only bit lines 3 and 4 are connected to the memory cell 13 or 14 to be accessed and require precharging, but the other bit lines 1, 2, 5, 6
．． 7 and 8 do not require precharging.

A case where precharging is started in the above state will be described. In this case, the precharge signal 41 is 1
'', so when this signal 41 is input to the X decoder 42, the word lines 9 and 10 become inactive as in the previous embodiment.

The precharge control circuit 44b outputs the inverted signal of the address signal 53, that is, "0", as the precharge transistor control signal 45, and outputs the address signal 53, that is, "1" as the precharge transistor control signal 46. Therefore, precharging transistors 35, 36.
39 and 40 are conductive and only bit lines 3.4.7 and 8 are precharged.

Next, when the precharge signal 41 becomes "0", the precharge control circuit 44b outputs the precharge transistor control signals 45 and 46 of 0", and in response, the precharge transistors 33 to 40 are turned off. On the other hand, in response to the precharge signal 41 of "0", the 9) is in the active state. In this state, the memory cell to be accessed is 13, and its information is output to the common data lines 31 and 32 and read out by the sense amplifier 47 in the same manner as described above. Also in this embodiment, since precharging is performed only on some bit lines including the selected bit line, power consumption is reduced.

〔Effect of the invention〕

As explained above, according to the present invention, based on the precharge signal and the address signal, only some bit lines including at least the bit line selected by the address signal are precharged. Unlike the conventional method, all bit lines are not unnecessarily precharged, and this has the effect of reducing power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a synchronous storage device according to an embodiment of the present invention, FIGS. 2, 3, and 4 are waveform diagrams for explaining precharge and read operations, and FIG. FIG. 6 is a block diagram showing a synchronous storage device according to another embodiment of the invention. FIG. 6 is a block diagram showing a conventional synchronous storage device. In the figure, 41 is a precharge signal, 53 is a Y address signal, and 61 is a precharge means. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masu Oiwa Leaving work Figure 1 Figure 5

Claims (1)

[Claims] (1) In a synchronous memory device that selects a bit line according to an address signal and performs precharging while controlling the timing of precharging the bit line according to a precharge signal, 1. A synchronous memory device comprising a precharging means for precharging only some bit lines including at least a selected bit line.