JPH0193846A - Dual port memory controller - Google Patents

Abstract

PURPOSE:To execute a block transferring at a high speed by allocating the address of a dual port memory in a ring shape and prohibiting the block transferring when difference between an input ending address and and output ending address is smaller than a prescribed value. CONSTITUTION:The addresses of dual port memories 4A And 4B are succeeded in the ring shape and allocated. By a CPU 8a to control a block transferring input and a CPU 8b to control a block transferring output, the using condition of a virtual ring memory and when the difference between the input ending address and the output ending address is smaller than the prescribed value, the block transferring is prohibited.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dual port memory control device;
In particular, dual-port memory enables high-speed block transfer by allocating consecutive addresses in a ring shape and controlling block transfer by detecting the input end address and output end address based on these addresses. - Concerning port memory control devices.

[Conventional technology]

An example of a conventional dual port memory control device is shown in FIG. This has two parallel buses 32 and 35, one of which is used for human power and the other as an output bus, and a dual port memory 33 that can be accessed from both is arranged. Image data is input to input ports 31 . The block is transferred to the dual port memory 33 via the input bus 32, and then, under the control of the output controller 34, the output device,
For example, it is transferred to a printer (not shown).

[Problem that the invention seeks to solve]

However, according to the conventional dual port memory control device, for example, if the maximum access speed of the dual port memory 33 is Vmax + the input speed is V in and the output speed is V out, the The maximum transfer speed Vilo when input and output overlap as shown in the example below is as follows: Since the output must wait until the input is finished, Vilo = (Vin + Vout) ≦ Vmax, and if Vin = Vout, then Since Vin=Vout≦'AVmay, the input/output speed becomes extremely slow, resulting in the inconvenience that block transfer takes time.

[Means for solving problems]

The present invention has been made in view of the above, and in order to speed up block transfer, addresses of dual port memory are consecutively allocated in a ring shape, and input end addresses and output end addresses are determined based on these addresses. A dual port memory control device detects and inhibits block transfer when the address difference is less than a predetermined value.

That is, the dual port memory control device of the present invention includes the following means.

(1) Address detection means When block transfer input performed from the manual port to the dual port memory and block transfer output performed from the dual port memory via the output port are performed in parallel, the block transfer input ends. Detect address and end address of block transfer output. Normally, block transfer is performed by specifying a transfer start address and a length representing the block length, and by counting down the length each time 1 byte is transferred, but there is a speed difference between block transfer input and block transfer output. Because there is
The address difference is detected based on the input/output end address. In the embodiment, although not shown, it is assumed that an address counter is provided inside the CPU.

(2) A circulating address is defined by making the end address of the control means dual port memory consecutive to its first address. Block transfer input and block transfer output are performed based on this address. At this time, signals of an input end address and an output end address are inputted from the address detection means, and block transfer input or block transfer output is prohibited when the address difference is less than a predetermined value. In the embodiment, although not shown, it is assumed that the CPU has a calculation section and a control section.

[For production]

When the input end address and the output end address are output from the address detection means, the control means calculates the input/output address difference based on the address signals. For example, assuming that dual port memory is divided into n equal parts and there are n memory units, when the aforementioned address difference becomes N8 when all addresses are N, block transfer input or block transfer output is prohibit. In this prohibition command, block transfer input is prohibited when the input speed is higher than the output speed, and block transfer output is prohibited when the reverse is the case. On the other hand, when allowing block transfer input or block transfer output, block transfer input is allowed only when there is space in the area to N, and block transfer output is allowed only when data is loaded in the area N/n. By controlling 0 or more, block transfer input and block transfer output do not overlap in the same memory unit, and input and output can be performed in parallel in different memory units. Therefore, the maximum transfer rate V i
When the maximum access speed is Vmax, lo is Vilo=2·V+sax.

Hereinafter, the dual port memory control device of the present invention will be explained in detail.

〔Example〕

FIG. 1 shows an embodiment of the present invention, which includes an ESS (subsystem: controller) 1, a printer 2 for printing M image data, and an Il! SS 1 and printer 2
The printer buffer 3 consists of dual port memories 4A and 4B (virtual ring memory described later) that store image data input from the ESS 1. ) and dual port memory 4A, 4
Image buses 5a and 5b arranged in parallel across B and a FIFO (fast in fast out) that sequentially inputs image data output from ESS 1.
6a and D? to transfer image data in FIFO 6a to dual port memory 4A or 4B? IAC (direct memory access, controller) 7a,
CP08a controls block transfer input of image data based on the input end address and output end address of the dual port memories 4A and 4B;
A CPυ8b that controls block transfer output of image data based on the input end address and output end address of the port memories 4A and 4B, a FIFO 6b that manually transfers image data to the printer 2, and a dual port memory 4A or It consists of a DMAC 7b that transfers image data from 4B to PIFO 6b. 9a.

9b indicates the interface of ESS 1 and printer 2, respectively, and 10a and 10b indicate local buses.

Here, in FIGS. 2 and 3 (a) to (e),
The concept of block transfer and virtual ring memory in the present invention will be explained. Input controller A and output controller B control input/output port 1.0 by notifying each other of the transfer end addresses (input end address and output end address) of dual port memories X and Y, and connect the input path and For example, a dual port memory X Hegelok transfer input is performed through input port I, and at the same time,
Control is performed to perform block transfer output from dual port memory Y via output port O. dual·
Port memory X.

The address of Y is as shown in Fig. 3(a) to (e).
They are arranged in a ring and are controlled as one dual port memory with ring addresses. In the present invention, this is referred to as virtual ring memory. Figure 3! Figure a) shows the block transfer in Figure 2 on the virtual ring memory, and shows the block transfer in Figure 2 on the virtual ring memory.
The arrow IN on the memory X side indicates the input end address, and the arrow OUT on the dual port memory Y side indicates the output end address. In this way, as a virtual ring memory, block transfer input and block transfer output are performed simultaneously, and individual dual port memories X, Y
In each case, only one of block transfer input and block transfer output is performed, and input and output accesses do not overlap.

However, if the input speed of image data is Vin and the output speed is Vout, the input speed Vin and output speed Vou
t is not always Vtn or Vout, for example, Vin
>Vout, as the block transfer progresses, the third
As shown in Figure fbl, the arrow IN approaches the arrow OUT, and the dual port memory
Output access occurs. In this way one dual
In port memory, in order to prevent input and output accesses from overlapping, input end address (arrow IN>
Half Full (
Input is prohibited in the state shown in FIG. 3(C)), and control is performed so that input and output accesses do not overlap. Similarly, Vin<V
In the case of out, arrow 0 [IT
approaches the arrow IN and simultaneous input and output access occurs in the dual port memory Y, so )I
By prohibiting output in the state of alf Empty (FIG. 3(e)), control is performed so that input and output accesses do not overlap. In this embodiment, dual port memory consisting of two memory units is used, so )! alf Full status, and Half
Input/output is prohibited in the Empty state, but
For example, when using four dual port memories, input is prohibited while image data is input to 374 of the entire virtual ring memory, and similarly, 374 of the entire virtual ring memory
74 is controlled to prohibit output when the area is empty. That is, the address is always between the input end address (arrow IN) and the output end address (arrow 0LIT), or between the output end address (arrow 0UT) and the input end address (arrow IN).
) is controlled to maintain an address distance equivalent to one memory unit of dual port memory.

In the above configuration, the operation will be explained based on FIG. 4, taking 1 block transfer input and 2 block transfer output as examples.

■A human power request (command: details omitted) is sent from block transfer input ESS 1 to the CPU 8a. When the CPU 8a receives an input request, it calculates an address difference based on the input end address and the output end address, and determines the usage state of the virtual ring memory (dual port memories 4A, 4B). Here, the virtual ring memory is already Half Fu
If it is in the ll state, input is prohibited (wait state),
If the state is not Half Full, input permission is output to the ESS1 and the DMAC 7a is activated. Based on the input permission, the ESS 1 sends the image data to the FIFO 6a, and the DMAC 7a inputs the image data input to the FIPO 6a by block transfer to the virtual ring memory. During block transfer, the CPU 8a sets the input end address to CPL1.
Notify 8b.

■Block transfer output An output request (command: details omitted) is sent from the printer 2 to the CPU 8b. When the CPU 8b receives the output request, it calculates the address difference based on the input end address and the output end address, and determines the usage state of the virtual ring memory (dual port memories 4A, 4B).

Here, the virtual ring memory is already IlalfEmp
ty, output is prohibited (wait state tI
E,) If the state is not Half EmptV, output permission is output to the printer 2 and the DMAC 7b is activated. The DMAC 7b transfers image data from the virtual ring memory to the FIFO 6b, and the image data transferred to the FIFO 6b is sequentially output to the printer 2 and printed. When the block transfer is completed, the CPU 8b notifies the CPU 8a of the output end address, and ends one cycle of block transfer output.

As described above, in block transfer, the CPU 8a controls block transfer input.

The CPU 8b, which controls the block transfer output and the block transfer output, manages the usage status of the virtual ring memory, thereby controlling input access and output access in one dual port memory unit, for example, the dual port memory 4^. The maximum transfer speed is Vi10 because it is #controlled so that simultaneous accesses do not occur.
can obtain a transfer rate of Vilo = 2 9 Vmax.

〔Effect of the invention〕

As explained above, according to the dual port memory control device of the present invention, the addresses of the dual port memory are continuously allocated in a ring shape, and the input end address and output end address are detected based on these addresses. Since the block transfer is prohibited when the address difference is less than a predetermined value, the block transfer speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of the present invention. FIG. 2 is an explanatory diagram showing block transfer according to the present invention. Figure 3 (al~
(e) is an explanatory diagram explaining the concept of virtual ring memory. FIG. 4 is an explanatory diagram for explaining the present invention in detail. Explanation of symbols 1・・・・・・・ESS 2・・・・・・・・Printer 3・・・・・・・・Printer buffer 4A, 4B
-Dual port memory 5a, 5b...-Image bus 6a, 6b -FIFO 7a, 7b -DMAC 8a, 8b -CPU 9a...---ESS interface 9
b.--1----- Printer interface 10a, 10b... Local, bus Patent applicant Fuji Xerox Co., Ltd. agent Patent attorney
1) Tadao Figure 2 (b no 1N Figure 3 (C) (e) Figure 5 procedural amendment (method) % formula % Relationship to the case Patent applicant address 3-3 Akasaka, Minato-ku, Tokyo No. 5 name (54
9) Fuji Xerox Co., Ltd. Representative: Yotabe Kobayashi 4, Agent address: Sogo 1st Building, 3-2 Kojimachi, Chiyoda-ku, Tokyo December 22, 1988 (Shipping port) 6. "Brief explanation of the drawings" column 7 Add the following sentence after "Explanatory diagram explaining the operation of the" in the "Brief explanation of the drawings" column of the statement of contents of the amendment, page 16, line 17. . ``Figure 5 is an explanatory diagram showing a conventional dual port memory control device.

Claims (1)

[Scope of Claims] (1) A dual port memory control device that performs block transfer input from an input port to a dual port memory and performs block transfer output from the dual port memory via an output port, comprising: address detection means for respectively detecting an input end address of the block transfer input and an output end address of the block transfer output; and a rotating address defined by following the start address of the dual port memory to its end address. when performing the block transfer input and the block transfer output based on the block transfer input and the block transfer output, the control means prohibits input or output when the address difference between the input end address and the output end address is less than or equal to a predetermined value. A dual port memory controller featuring: (2) The control means equally divides the dual port memory by a predetermined value n, and when the data free area of the dual port memory is 1/n or less of the total area, the address difference is 2. The dual port memory control device according to claim 1, wherein said input is prohibited as being less than a predetermined value. (3) When the control means equally divides the dual port memory by a predetermined value n, and the data storage area of the dual port memory is 1/n or less of the total area, the address difference is 2. The dual port memory control device according to claim 1, wherein said output is inhibited because said output is less than a predetermined value. (4) When the block transfer input and the block transfer output continue, the control means prohibits the input when the block transfer input speed is greater than the block transfer output speed, and the control means prohibits the input when the block transfer input speed and the block transfer output speed are 2. The dual port memory controller of claim 1, wherein said output is inhibited when the block transfer input rate is greater than the block transfer input rate.