JPH0136294B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmission system between two digital communication devices that perform burst communication, and particularly to a transmission system that does not provide burst synchronization bits.

The digitalization of communication systems is expanding, and for example, there are methods for connecting exchanges and subscriber terminals using digital lines. There is a method of communication. In such communication systems, burst communication is generally performed by adding a burst synchronization bit F to information bits such as PCM codes and signal bits, as shown in FIG. However, when a burst synchronization bit is added, the burst length becomes longer, which increases the transmission clock frequency, which requires a wider bandwidth transmission path, or shortens the possible transmission distance when bidirectional time-division communication is performed at a constant cycle. There is a problem. This is the same even when a multilevel code is used as a transmission code; the longer the transmitted digital signal becomes, the more multilevel codes are required, or the number of symbols in a burst signal needs to be increased. On the other hand, as shown in Patent Publication No. 1984-44523 as a burst communication system that does not add burst synchronization bits, 1 of the digital signal is converted into a transmission code of positive pulse and 0 is converted to a negative pulse transmission code, and the received signal is transmitted by converting it into a transmission code of the burst signal. There is a method of maintaining burst synchronization using the first positive or negative pulse. However, in this method, if there is a significant difference in the number of positive pulses and negative pulses in the burst signal, the average level of the burst signal will be far from zero level, and waveform distortion will increase in a transmission line with reduced cutoff characteristics, causing There is a problem that signal reproduction becomes difficult.

An object of the present invention is to minimize the amount of unbalance in the burst signal without adding a burst synchronization bit to the burst signal.

The burst signal transmission method of the present invention is a transmission method for transmitting digital signals in bursts, in which the digital signal is converted into absolute values of a plurality of multilevel symbols, and first and second polarities of opposite polarities are converted. Using a multi-level code transmitted by symbols and zero-level symbols, on the transmitting side, if the first bit of the digital signal is 1, the digital signal is directly converted to the absolute value of the multi-level symbol, and the first bit of the burst signal is converted to the absolute value of the multi-level symbol. Giving the symbol the first polarity, and when the first bit is 0, inverting the 0 and 1 of the digital signal to convert it into the absolute value of a multilevel symbol, and giving the first polarity the second polarity. and for each symbol after the second symbol of the burst signal, the polarity is opposite to the average level before each symbol, or if the average level is zero, the previous symbol excluding the zero level symbol. At the receiving side, a burst synchronization signal is extracted from the first symbol of the burst signal, and the absolute value of each symbol is converted into a digital signal. The symbol is the first
If the polarity is the same, the digital signal is decoded as is, and if the first symbol is the second polarity, the digital signal is decoded by inverting the 0s and 1s of the digital signal.

The present invention will be described in detail below with reference to the drawings. FIG. 2 is a diagram showing an embodiment of a digital communication system using the transmission method of the present invention, in which a transmitting device 1 and a receiving device 2 are connected by a transmission path 3. In FIG. First, the case where a multilevel code is used will be explained using an example in which a 2-bit binary signal corresponds to a 7-level symbol having absolute values of 4 levels including a zero level. FIG. 3 is a table showing the relationship between binary signals and seven-value symbols. As is clear from this table, the binary signal corresponds only to the absolute value of the 7-value symbol. Encoding and
The decoding method will be explained using the example shown in FIG. On the transmitting side, when the digital signal to be transmitted is 1000011101 as shown in _a1 of FIG. 4, the first bit is 1, so this digital signal is multi-valued as is, 2 bits at a time, according to the table of FIG. 3.
The absolute value of the multivalued signal is 2, 0, 1, 3, 1
becomes. Since the first bit of the digital signal shown at _a1 in FIG. 4 is 1, positive polarity is given to the first symbol. Therefore, the first symbol becomes +2. Since the next symbol is 0, it is given a zero level. In the third symbol, since the sum of the first symbol and the second symbol, that is, the average level up to the second symbol is positive, negative polarity is given. Therefore, the third symbol becomes -1. Similarly, the average level up to the third symbol is positive, so the fourth symbol is -3, and the average level up to the fourth symbol is negative, so the fifth symbol is -3.
The symbol becomes +1. This 7-level, 5-symbol burst signal is shown in FIG. _4c1 . On the other hand, the digital signal to be transmitted is as shown in a ₂ of Figure 4.
In the case of 0010011110, the first bit is 0, so the 0 and 1 of this digital signal are inverted as shown in b ₂ of Fig. 4, and the inverted digital signal is multi-valued 2 bits at a time according to the table of Fig. 3. do. The absolute values of the multivalued signal are 3, 1, 2, 0, and 1.
Since the first bit of the digital signal shown at _a2 in FIG. 4 is 0, negative polarity is given to the first symbol. Therefore, the first symbol is -3. Since the first symbol has negative polarity, the second symbol has positive polarity and becomes +1. Since the average level up to the second symbol is negative, the third symbol is +2. Since the fourth symbol is 0, it is at the zero level. Since the average level up to the fourth symbol is zero, the fifth symbol has a polarity opposite to that of the previous symbol excluding the zero level, that is, the third symbol, and becomes -1. This 7-level, 5-symbol burst signal is shown at _c2 in FIG. On the receiving side, the burst signals shown at c ₁ and c ₂ in FIG. 4 are received and rectified. Therefore, since the first symbol of the rectified burst signal always has positive polarity, it is possible to extract the burst synchronization signal. When this rectified burst signal is converted into a binary signal, b ₁ and
b The signal shown in ₂ will be obtained. Also, the extracted burst synchronization signal is used to determine the polarity of the first symbol of the burst signal shown in c _{1 and} c ₂ of FIG. In the case of , leave the converted binary signal as is and use the method shown in Figure 4.
As shown in _c2 , when the first symbol has negative polarity, 0 and 1 of the converted binary signal are inverted. Therefore, the burst signals c ₁ and c ₂ in FIG. 4 are a ₁ and c 2 in FIG.
a It is decoded into the digital signal shown in ₂ . In this way, if the encoding/decoding method of the present invention is used, the polarity of each symbol is given so as to reduce the degree of DC unbalance of the burst signal, so the bit pattern of the transmitted digital signal and the symbol of the multilevel code The burst synchronization signal can be suppressed to within the maximum absolute value of one symbol regardless of the number, and the first bit of the burst signal does not become zero level, so the burst synchronization signal can be extracted without adding a burst synchronization bit. can. FIG. 5 shows an example of the transmitting device 1 for realizing this encoding/decoding method, and FIG. 6 shows an example of the receiving device 2. Fifth
In the transmitter 1 shown in the figure, a digital signal to be transmitted is input to an exclusive OR gate (hereinafter abbreviated as EOR gate) 10 and is also supplied to a data input D of a flip-flop 12. Flip-flop 12 latches the first bit of this digital signal with control signal 8. The inverted output of flip-flop 12 is sent to another input of EOR gate 10, and the non-inverted output Q is input to selection circuit 14. Therefore, when the first bit is 1, the digital signal remains unchanged and when the first bit is 0, it is inverted.
It is output from the EOR gate 10. EOR gate 1
The output of 0 is input via the register 11 to the absolute value bit position of the input register 15 of the analog-to-digital converter 13 for each unit block (every 2 bits in the example of FIG. 4). In addition, the selection circuit 1 is placed in the sign bit position of the input register 15 by the control signal 9.
The non-inverted output Q of the flip-flop 12 selected by the flip-flop 4 is input. Analog-digital converter 1
3 converts the data in the input register 15 into an analog signal and sends it to the transmission line 3 via the driver 16 and transformer 12. The arithmetic unit 17 inputs the output data of the input register 15, integrates the input data, outputs the opposite sign of the sign bit of the integration result, and when the integration result is zero, outputs the opposite sign of the sign bit of the immediately previous input data that is not at zero level. Output. Note that this integration result is cleared after the burst signal is sent. The selection circuit 14 selects the output of the arithmetic unit 17 based on the control signal 9 after sending out the first symbol. Therefore, the transmitted digital signals shown at a ₁ and a ₂ in Fig. 4 are
When input to the EOR gate 10, c ₁ and c ₂ in Fig. 4
A multi-level signal shown in is output from the digital-to-analog converter 13. This multilevel signal is driver 1
After the burst length is limited by the control signal 7 at 6, the signal is supplied to the transmission line 3 via the transformer 12. In the receiving device 2 shown in FIG. 6, a multilevel signal input via the transmission line 3 and the transformer 27 whose secondary side is terminated by a load 28 is supplied to the rectifier circuit 23 and the comparator 26 via the receiver 24. The multilevel signal rectified by the rectifier circuit 23 is sent to the digital-to-analog converter 21 and the synchronization circuit 22.
is supplied to The synchronization circuit 22 extracts a burst synchronization signal from the first symbol of the rectified multilevel signal and supplies it to the flip-flop 25. The comparator 26 determines the polarity of the output of the receiver 24, and when the polarity is positive, it becomes 0.
Outputs 1 when the polarity is negative. flipflop 2
5 latches and holds the output of the comparator 26 using the burst synchronization signal. Digital to analog converter 2
1 digitally converts the multilevel signal symbol by symbol. Therefore, when the multilevel signals shown at c ₁ and c ₂ in FIG. 4 are input to the receiver 24, the binary signals shown at b ₁ and b ₂ in FIG.
Output from 1. The output of the flip-flop 25 is 0 when the first symbol of the burst signal is positive.
is 1 in the case of negative polarity, so the binary signals shown at b ₁ and b ₂ in FIG. 4 are decoded by the EOR gate 20 into the signals shown at a ₁ and a ₂ in FIG.

Next, a case will be described in which three values of positive and negative pulses and zero level are used as the multi-value signal. First, we will describe the encoding/decoding method. The above rules can be applied as is, but the absolute values of multivalues are 0 and 1.
Since there are only two ways, this rule can be easily expressed. On the transmitting side, when it is the first bit of the digital signal to be transmitted, the first bit is made into a positive pulse and converted into an AMI code (Alternate Mark).
This is the abbreviation for Tnverse code, and the details are described as a bipolar system in Chapter 3 of ``Basics and New Technology of PCM Communication'' edited by Hiroshi Inose, published by Sanpo. ), and if the first bit is 0, 0 and 1 of the digital signal are inverted, a negative pulse is given to the first bit, and the inverted digital signal is AMI encoded. Therefore, Figure 7
The digital signals shown in a ₁ and a ₂ are temporarily transferred to b 1 and b ₁ in FIG.
After being converted into a digital signal shown in _b2 , it is encoded into a ternary signal shown in _c1 and _c2 in FIG. As can be seen from the examples shown in c ₁ and c ₂ of FIG. 7, the DC unbalance of each burst signal is suppressed to ±1 at most. Also, since the first bit is always a positive pulse or a negative pulse, each burst can have a burst synchronization signal without adding a burst synchronization bit. On the receiving side, a burst synchronization signal is extracted using the positive pulse or negative pulse of the first bit of the burst signal, the polarity of the first bit is determined, and the burst signal is further rectified. If the polarity of the first bit is positive, it remains as is, and if it is negative, the rectified digital signal is inverted between 0 and 1 and decoded. Therefore, when the burst signals shown at c ₁ and c ₂ in FIG. 7 are received, they are decoded into digital signals shown at a ₁ and a ₂ in FIG.

Examples of a transmitter 1 and a receiver 2 using this ternary signal are shown in FIGS. 8 and 9, respectively. 8th
In the transmitter 1 shown in the figure, the transmitted digital signal is
It is input to the D input of EOR gate 10 and flip-flop 30. Flip-flop 30 latches the first bit of the digital signal according to control signal 8 and provides an inverted output to another input of EOR gate 10. Therefore, if the first bit of the digital signal is 1, it remains as is, and if it is 0, it is inverted.
It is output from the EOR gate 10. Further, the 1-bit counter 34 loads the first bit as an initial value by the control signal 8. The output of EOR gate 10 is supplied to AND gates 35 and 36 with its burst length limited by control signal 7 in AND gate 32 . The AND gate 33 supplies the output of the AND gate 32 to the clock input Cp of the counter 34 which is RZ encoded by the control signal 31.
The counter 34 uses the first bit of the digital signal as an initial value and counts the number 31 outputted from the AND gate 32 from the second bit onward. If the first bit of the digital signal is 1, the non-inverted output Q and the inverted output of the counter 34 will be 1 and 0, respectively.
The outputs of AND gates 35 and 36 are connected to driver 3
7 and 38 to the primary side of the transformer 39. The midpoint of the primary side of the transformer 39 is the power supply V
A positive pulse is supplied to the transmission line 3 in response to this first bit. When the first bit of the digital signal is 0, the non-inverted output Q of the counter 32 is 0, and the inverted output is 1, and the AND gate 3
Since the output of the gate 6 is 0 and the output of the AND gate 35 is 1, a negative pulse is supplied to the transmission line 3. AND
When the output of gate 32 is 0, counter 34 does not advance the count and the outputs of AND gates 36 and 35 are 0. Therefore, the transmission line 3 is supplied with a zero level. When 1 appears at the output of the AND gate 32, the counter 34 counts this and alternates
1 is supplied to AND gates 35 and 36. Therefore, positive pulses and negative pulses are alternately supplied to the transmission line 3 in accordance with the output 1 of the AND gate 32. The digital signals shown at a ₁ and a ₂ in Figure 7 are
When input to EOR gate 10, EOR gate 10
The signals shown in b ₁ and b ₂ in Fig. 7 appear at the output of
Signals shown at c ₁ and c ₂ in FIG. 7 are supplied to the transmission line 3. In the receiving device 2 of FIG. 9, the burst signal received from the transmission line 3 is input to comparators 42 and 43 via the transformer 27 and receiver 24. Comparator 42 compares the normal standard voltage connected to its negative input with the output of receiver 24 connected to its positive input, and outputs 1 when the received burst signal is a positive pulse. The comparator 43 compares the negative reference voltage connected to its positive input with the output of the receiver 24 connected to its negative input, and outputs 1 when the received burst signal is a negative pulse. OR gate 41 is comparator 4
Input the outputs of 2 and 43 and EOR the outputs.
The signal is sent to the gate 20 and the synchronization circuit 45. This OR
The output of gate 41 is a rectified signal of the received burst signal. Synchronization circuit 41 detects the first bit of 1 in the digital signal output from OR gate 41 and supplies a burst synchronization signal to AND gates 46 and 47. As the synchronous circuit 41, for example, one shown in patent application No. 136158/1984 may be used. AND gates 46 and 47 input the burst synchronization signal and input the comparator 42, respectively.
and input the output of 43. Therefore, when the first bit of the received burst signal is a positive pulse, the flip-flop 48 is set by the AND gate 46 and the output Q becomes 0, and when it is a negative pulse, it is set by the AND gate 47 and the output Q becomes 1. Therefore, when the first bit of the received burst signal is a positive pulse, the EOR gate uses the output of the OR gate 41 as it is, and when it is a negative pulse, the output of the OR gate 41 is 0.
and 1 are inverted and output. When the burst signals shown in c ₁ and c ₂ in FIG. 7 are received from the transmission line 3, the signals shown in b ₁ and b ₂ in FIG. of
It is decoded into the signals shown in a ₁ and a ₂ .

Although the explanation has been made using the NRZ code as the transmission code according to the present invention on the transmission path 3, the present invention can be similarly applied to the RZ code. In this case, in the transmitter 1 of FIG. 5, the pulse width of the output signal of the digital-to-analog converter 13 is narrowed,
In the transmitter 1 of FIG. 8, the AND gate 32
It is sufficient to RZ encode the output signal of . A part of the configuration of the transmitter 1 in the latter case is shown in FIG. In FIG. 10, the AND gate 132 controls the burst length of the output signal of the EOR gate 10 and outputs the RZ encoded signal using the control signal 31.
The code supplied to the transmission line 3 via the AND gates 35 and 36 is an RZ code.

Although the above description has been made using unidirectional burst communication as an example, the present invention can also be applied to bidirectional burst communication based on time division. In this case, the communication device has both a transmitter and a receiver, is connected to the transmission path 3, and has a transmission path interface circuit that separates the transmission path and the reception path. FIG. 11 shows an example of a transmission line interface circuit when a ternary signal is used. In the transmission line interface circuit shown in FIG. 11, the receiver 24 stops the receiving operation during transmission by means of the control signal 29 so as not to receive its own transmission signal.

Incidentally, in order to further suppress the DC component of the burst signal, a balancing bit may be added as shown in Patent Publication No. 163612/1982. Even when the balancing bit is added in this way, the burst synchronization bit is unnecessary and the effectiveness of the present invention in shortening the burst length is not impaired. As described above, according to the present invention, it is possible to suppress the DC component of a burst signal and shorten the burst length, and it is possible to use a transmission path having low-frequency cutoff characteristics and a narrow band, thereby improving digital communication. contribute to the economicization of

[Brief explanation of drawings]

FIG. 1 is a diagram showing the structure of a conventional burst signal.
FIG. 2 is an example of the configuration of a communication system using the present invention, FIG. 3 is an example of the relationship between a binary signal and a 7-level symbol, and FIG. 4 is an example of encoding and decoding in a multilevel code according to the present invention. , FIG. 5 and FIG. 6 are examples of a transmitting device and a receiving device used in the present invention,
FIG. 7 is an example of encoding and decoding in the ternary code according to the present invention, FIGS. 8 and 9 are other embodiments of the transmitter and receiver used in the present invention, and FIG. 10 is another example of the transmitter. FIG. 11 shows an example of a transmission line interface circuit. In the figure, 1 is a transmitting device, 2 is a receiving device, 3
is the transmission line, 10, 20, 32, 33, 35, 3
6, 41, 46, 47 and 132 are gates, 1
1 and 15 are registers, 12, 27 and 39 are transformers, 13 is a digital to analog converter, and 21
1 is an analog-to-digital converter, 17 is an arithmetic unit, 14 is a selection circuit, 12, 25, 30, and 4.
8 is a flip-flop, 23 is a rectifier circuit, 22 and 45 are synchronous circuits, 34 is a counter, 16, 3
7 and 38 are drivers, 24 is a receiver, 2
6, 42 and 43 are comparators, and 28 is a load.

Claims (1)

[Claims] 1. A burst signal is transmitted from a transmitting side to a receiving side via a transmission path, and on the transmitting side, a binary digital signal string to be transmitted is set to zero level for each one or more bits thereof. It is converted according to a conversion rule for converting into the absolute value of the multi-valued symbol, and among the absolute values of the multi-valued symbol, the zero level symbol is the zero level, and the symbols other than the zero level are the first or A signal train is created by giving the second polarity respectively, and this signal train is transmitted to the transmission path as the burst signal, and the conversion rule is such that when the first bit of the one or more bits is "0", In a burst signal transmission system in which the absolute value of a multilevel symbol can be zero level, on the transmitting side, if the first bit of the digital signal to be transmitted is "1", the digital signal to be transmitted is The digital signal is converted into the absolute value of a multi-level symbol according to the conversion rule, and the first burst signal is
The first polarity is given to the symbol, and when the first bit is "0", a signal obtained by inverting all bits of the digital signal string to be transmitted is converted into a multi-level symbol according to the conversion rule. and give the second polarity to the first symbol of the burst signal, and for each symbol after the second symbol of each burst signal, set the opposite polarity of the average level polarity before each symbol. and when the average level is zero level, the symbol is transmitted with a polarity opposite to the polarity of the immediately preceding symbol excluding the zero level symbol, and on the receiving side, the first burst signal received from the transmission path is transmitted. A burst synchronization signal is extracted from the symbols, the absolute value of each symbol is detected, and an inverse transformation corresponding to the conversion rule is performed to obtain a reproduced binary digital signal, and the polarity of the first symbol is determined by When the polarity of the first symbol is the first polarity, the reproduced binary digital signal is the decoded signal, and when the polarity of the first symbol is the second polarity, the reproduced binary digital signal is A burst signal transmission method characterized in that the decoded signal is a signal with all bits inverted. 2. The conversion rule is a conversion rule for converting the digital signal string to be transmitted into the absolute value of a multi-value symbol containing a zero level every two bits, and the multi-value symbol has an absolute value of 0, 1,
2. The burst signal transmission system according to claim 1, wherein the burst signal is a multilevel symbol that takes either 2 or 3. 3. The conversion rule is a conversion rule for converting the digital signal string to be transmitted into a binary signal string for each bit, and the multi-value symbol is a multi-value symbol that takes either 0, +1, or -1. 2. The burst signal transmission method according to claim 1, wherein the burst signal is a value symbol.