JPH01320555A - Buffer storage device - Google Patents

Abstract

PURPOSE:To improve throughput by providing plural buffers for write to hold an address for write and data, and comprising a device of a register of dual port. CONSTITUTION:A directory memory 1 and a data memory compare an address inputted from a CPU with a tag address stored in the memory 1. Simultaneously, since they perform the comparison of the addresses in a store buffer, it is possible to read/write the data by the CPU with the minimum machine cycles without making access to a main memory even when noncoincidence is obtained in a comparison result with the memory 1 if coincidence is obtained in the comparison result of the addresses. In addition to that, since registers (6a-6d) of dual port format are provided in the buffer 6, it is possible to execute the write on the data memory 2 or the main memory even when the write cycle of the memory by the CPU continues, thereby, the throughput can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a storage management technique and a technique that is particularly effective when applied to a control method for a buffer storage device, for example, in an information processing system employing a buffer storage method. This article relates to techniques that are effective for use in configuring cache memory.

[Prior Art] Conventionally, in a microcomputer that employs a buffer storage method, frequently used information in a main storage device such as a dynamic RAM is stored in a cache memory, and this information is stored in a cache controller. There are some devices that are controlled by a storage management device called ``Storage Management System'' to improve throughput.

Incidentally, a cache memory with a built-in cache controller, such as μPD43608 manufactured by NEC Corporation, is also provided.

FIG. 9 shows an example of the configuration of a buffer storage type microcomputer system.

In the case of reading, the cache memory C-MEM is accessed by the address output from the central processing unit (hereinafter referred to as CPU), and when the desired data is in the cache memory C-MEM, that is, when the cache is hit, The CPU can access data at the speed of cache memory, improving system throughput. Also, CPU
The read address and cache memory C- supplied from
When it is determined that the desired data is not in the memory by comparing it with the address tag of the directory memory inside the MEM,
That is, when a cache miss occurs, the read address is sent to the main memory M-MEM, the desired data is read out, and the data is passed to the CPU. Similarly, in the case of writing, when the data at the corresponding address exists in the cache memory C-MEM, the cache memory is accessed, but when there is no data, the main memory is accessed. However, the main memory in a buffer storage type system is often composed of an inexpensive dynamic RAM. In that case, the writing time to the main memory is considerably longer than the reading time from the cache memory, so the CP
If U was directly accessing main memory, then CP
U's waiting time increases and throughput decreases.

Therefore, the aforementioned cache memory is provided with a buffer (write buffer) that holds the write address and write data output from the CPU (see "Nikkei Microdevice J, April 1987 issue, p.86-p.90").
.

[Problems to be Solved by the Invention] However, the cache memory described above is provided with only one set of write buffers, and has a single port configuration in which only writing and discharging can be performed at the same time. Therefore, for example, when executing an instruction in which a write cycle to memory continues two or more times in one instruction cycle, the next address and data cannot be stored in the buffer until the address and data in the write buffer are flushed out. Can not. As a result, the CPU's write cycle execution time is constrained by the main memory's cycle time, which increases the CPU's waiting time and reduces system throughput.

The purpose of this invention is to store multiple addresses and write data from the CPU in succession even when write cycles are continuous, so that the main memory can be indirectly accessed when the bus is idle. An object of the present invention is to provide a cache memory that can improve throughput.

Another object of the present invention is to provide a cache memory capable of improving throughput by obtaining desired data faster than determining cache hits in a directory memory section in which address tags are stored. .

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a plurality of sets of write buffers for holding write addresses and data are provided, and the write buffers are configured with dual-port registers.

Further, an address comparator is provided to compare the address supplied from the outside with the address in the buffer, and when the two match, the data in the corresponding register is output to the bus.

[Operation] According to the above-mentioned means, multiple sets of write buffers are prepared, so when write cycles are consecutive, the address and data can be read in the next write cycle as soon as - write cycles are completed. In addition to being able to write to the write buffer and transfer data from the write buffer to the internal data memory section (hereinafter referred to as output), it is possible to It is now possible to write data into the data memory or main memory by discharging data one after another when the memory bus is free, improving throughput.

In addition, in parallel with the comparison of address tags by the tag comparator, addresses are compared by a comparator provided corresponding to the write buffer, and when the addresses match, the CPU reads the data in the write buffer. /write, so if the write buffer is hit, the hit rate can be improved.

[Embodiment] FIG. 1 shows the configuration of essential parts of an embodiment in which the present invention is applied to a cache memory with a built-in cache controller.

The cache memory 10 in the figure is composed of one chip,
directory memory], data memory 2, and LRU (Least Recently
(Used) type block replacement control circuit 3, a memory array consisting of a tag comparator 4, and a CPU interface 11.
, a system bus interface 12, etc. are formed, and are connected between the system bus to which the main memory is connected and the CPU bus.

In the directory memory 1, the upper ten or more bits of the address on the main memory of data stored in the same column position of the data memory 2 are stored as a tag.

When the column address part CLM of the address AD given by the CPU via the CPU interface 11 is supplied to the common decoder of the directory memory 1, data memory 2, and LRU 3, the address tag and the address tag from the same column of each memory are supplied. Data is read simultaneously.

Among these, the address tag read from the directory memory 1 is supplied to the tag comparator 4. This tag comparator 4
is the address A given to the memory array by the CPU.
The data of the tag portion TAG of D is also supplied, and compared with the tag read from the directory memory 1, a signal CH indicating a match (cat hit) or a mismatch (miss hit) is output. When the cache hits, data read from the corresponding column position of the data memory 2 is supplied to the CPU from the data bus 5 via the CPU interface 11. On the other hand, if a mishit occurs, the main memory can be accessed by connecting to the system bus via the system bus interface 2 and desired data can be obtained.

In this embodiment, a store buffer 6 is provided as a write buffer having a plurality of registers (four in this embodiment) for latching and holding addresses and data supplied from the CPU during a memory write cycle.

Each of the registers 68 to 6d constituting this store buffer has a number of bits capable of holding all of address AD given by the CPU, byte control data BC (hereinafter referred to as byte code), and write data, and registers 6a to 6d. Each 6d has a valid bit V indicating whether the internal data is valid, that is, whether writing has been performed, and an access bit A indicating whether the register is being accessed.

Moreover, the store buffer 6 uses a dual-port flip-flop as shown in FIG. 2, for example, as a flip-flop constituting a register, and connects a read data line and a write data line via transfer MO8Qz, Qz. Connect and light side transfer MO8
Q and the read-side transfer MO8Q can be selectively turned on using separate word lines W2 and W2. Thereby, the registers constituting the store buffer 6 can be read and written asynchronously.

In order to be able to select any one of the four registers 68 to 6d, a write counter 7a and a decoder 8a and a read counter 7b and a decoder 8b are provided as shown in FIG. The write counter 7a is a bus activation signal BS output from the CPU.
The read counter 7b counts up when a predetermined condition is satisfied in synchronization with the system clock supplied to the cache memory.

In addition, depending on the operating state of the cache memory, the valid bits and access bits A in each of the registers 68 to 6d are set or reset, and the valid bits V and V are set or reset.
and the counter 7 according to the state of access bit A.
A sip control circuit 9 is provided which controls the components a and 7b.

Furthermore, in this embodiment, although not particularly limited, a comparison circuit 20 is provided which compares the address and bytecode of the data stored in the store buffer 6 with the address and bytecode supplied from the CPU to the cache memory. It is provided. This comparison circuit 20 is, for example, as shown in FIG. 3, an OR gate G that takes the logical sum of four comparators CMP-CMP4 corresponding to each register 6a-6d and their outputs. It simultaneously compares the data in all registers 6a to 6d with the address AD and byte code BC from the CPU, and outputs hit signals H1 to H4 when they match. These hit signals H8-H are supplied to the store buffer control circuit 9 or decoders 8a, 8b to form a signal for selecting the matching register.

Further, the output signal of the OR gate G0 is sent to the CPU interface circuit 11 as a store buffer hit signal SBH.
is supplied to the CPU via.

In the memory array consisting of the directory memory 1 and the data memory 2, the address input from the CPU is compared with the tag address stored in the directory memory 1. At the same time, in the above embodiment, the address in the store buffer 6 is compared. Since addresses are compared, if the comparison result of this address matches (hit), even if the comparison result with directory memory 1 does not match (mishit), the main memory is not accessed and the minimum machine cycle is The CPU can read/write data. As a result, the hit rate of the cache memory can be improved.

Furthermore, in this embodiment, four dual-port registers 6a to 6d are provided in the store buffer 6, so even when the CPU performs consecutive memory write cycles, write addresses and data are stored one after another. The address and data can be stored in the buffer 6, and when the internal bus or main memory bus becomes free, the address and data can be discharged from the store buffer and written into the data memory or main memory.

Note that if the CPU write cycle continues many times and there are no free registers in the store buffer 6, the control circuit 9 sends a wait signal to the CPU via the interface circuit 11 to make it wait. Just do it. However, in a normal CPU, there are almost no cases where a write cycle continues more than five times, so the probability that the weight will increase is much lower than when there is only one store buffer.

Figure 4 shows the store buffer 6 by the control circuit @9.
An example of a control procedure for the circuit and its peripheral circuits is shown.

The control circuit 9 receives a bus activation signal BS from the CPU.
When the start of a bus cycle is known, the CPU interface side first starts searching the store buffer 6 using the address and byte code from the CPU (
Step 5ll).

At this time, comparison of address tags by the tag comparator 4 is also started at the same time. In parallel, as a process on the system bus interface side, every time the system clock rises, the startup of store buffer discharge is monitored, and the states of valid bits V and access bits A of store buffers 6a to 6d are checked. Then, the flow of discharging the data in the store buffer 6 is activated (step 521). In other words, write 1- and read in the store buffer are processed asynchronously. Below, read/write 1- on the CPU side
operation (processing on the CPU interface side) and dispensing operation (
Processing on the system bus interface side) will be explained separately.

In the CPU interface side processing, after searching the store buffer using the address from the CPU, it checks the read/write signal R/W from the CPU to determine whether it is a CPU read cycle or a write cycle (step 512), and if it is a read cycle, step 51). -3, it is determined whether the store buffer has been hit or not, that is, whether there is a register with a matching address. If the store buffer is hit in this step S13, the data is read from the hit register and output to the data bus 5''2 (step 515).
) After stopping the comparison by the tag comparator 4.

The store buffer hit signal SBH is returned to the CPU to end the bus cycle. If the store buffer misses in step S13, the address tag determination on the directory memory (address tag array) side is waited, and if the address tags also do not match, the CP
U goes to the main memory to retrieve data.

On the other hand, if the started bus cycle is a CI'U write cycle, steps 312 to S
Step 15 determines whether the store buffer has been hit, and if so, stores the write address, byte code, and write data in the hit register (step 818), and then stores the V bit of the stored register. 1
11 It is set to end the bus cycle (step 319).

On the other hand, if the store buffer is not hit in the write cycle, check the V bit and determine whether there is an empty register (step 816). When the write address, byte code, and write data are generated, the write address, byte code, and write data are stored in the register (step 517), and then the V bit of the stored register is set to end the bus cycle (
step 519).

In the process on the system bus interface side, when discharge of the store buffer is activated by the rise of the system clock, it is first determined whether or not the read baud 1- of the store buffer and the directory memory 1 are in use (step S21-). Here, if the directory memory 1 is in use, it waits while the store buffer discharge is activated.

This is to prevent read data from the data memory and discharge data from the store buffer from colliding on the internal data bus 5. If it is not in use, the process advances to step 322, where the V bit in the store buffer is checked to determine whether there is a register containing valid data in the store buffer, and if there is valid data, it is selected by the read counter 7b. l to the A bit of the register
/I 11 is set, the write address stored in the register is output, and the search in directory memory 1 is started using that address (step 523). If the address tag array is hit, the process moves from step S24 to 825, and the write data in the corresponding register of the store buffer is discharged to the data memory 2. On the other hand, if it is determined in step S24 that there is a miss as a result of the search in the address tag array, the process advances to step S26 and the write data in the store buffer is discharged to the main memory via the stem bus interface.

After that, the A bit and V bit of the register where the discharge was performed are reset to "Otz", and then the read counter 7 is reset.
b is updated (counted up) and the process waits for the next store buffer to be discharged (steps S27, 528).

Note that in the determination in step S22, the V bit is
'', the process jumps to step S28 without doing anything, updates the read counter 7b, and waits for the start of the next store buffer discharge.

Figure 5 shows that the CP
The timings of various signals when the address accessed by U and the address stored in the store buffer 6 are compared and a match is found are shown. In the figure, CLK is a system clock, AD is an address, BC is a byte control signal, R/W is a signal indicating a read or write state, BS is a bus start signal indicating the start of a bus cycle, As.

DS is an address strobe signal and a data strobe signal respectively indicating that a valid address and data are present on the bus, and these signals are given from the CPU to the cache memory. Further, SBH is a signal indicating that the store buffer has been hit. Furthermore, DC is a data complete signal indicating that the data requested by the CPU is ready, and is given to the CPU from the cache memory.

Further, FIG. 6 shows the timing of various signals in a write cycle by the CPU.

In this cycle, the address and data supplied from the CPU are always stored in the storage buffer 76. First, the store buffer 6 is searched, and when an empty register is found, the address and data are stored. .

Furthermore, FIG. 7 shows the timing for discharging write addresses and data from the store buffer. This cycle is performed asynchronously with the CPU cycle. That is, a search of the address tag array is started in synchronization with the rising edge of the system clock CLK, and if a search is found, the data in the anti-door buffer is transferred to the data array.

In the case of a miss, the write data is transferred to the main memory.

Furthermore, in the above embodiment, the data storage section (32 bits) of the registers 68 to 6d constituting the store buffer 6
For example, as shown in FIG. 8, gates 01 to G4 are provided for every 8 bits to the input port of , and registers 6a to G4 which constitute the store buffer 6 are controlled by the byte code BC supplied from the CPU. It has a so-called partial read/write function that reads or writes 1 byte at a time to the 4-byte data section of 6d.

As explained above, in the above embodiment, a plurality of registers are provided to hold write addresses and data, and the registers are configured with dual port registers, so even when write cycles are continuous,
In addition to being able to store write addresses and data continuously, it is also possible to write to and output from the write buffer consisting of the four registers mentioned above asynchronously, so they can be written one after another when the bus is free. Since write data can be written to the data memory or main memory by discharging the write data, the throughput of the system can be improved.

In addition, an address comparator is provided to compare the address supplied from the outside with the address in the buffer.1 When the two match, the data in the corresponding register is output onto the bus. In parallel with the comparison of address tags, a comparator provided corresponding to the store buffer as a write buffer compares the addresses, and when a match occurs, the data in the write buffer can be given to the CPU. This has the effect of improving system throughput.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, C in the above embodiment
Processing on the PU interface side (steps Sll to 519)
) in.

The A bit can be used for processing such as monitoring the A bit and forming a wait signal to make read access by the CPU wait.

Furthermore, a number of functional circuits such as a parity checker or a buffer for holding data read/written to the data memory in units of blocks may be added.

In the following explanation, the invention made by the present inventor was mainly applied to a cache memory with a built-in cache controller, which is the field of application in which the invention was made, but the invention is not limited thereto. , it can also be applied to a system in which the cache controller and cache memory are configured on separate chips.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, when the write cycles are consecutive.

- The next write address and data can be entered before the previous write cycle is completely completed, and
Since writing and discharging to the write buffer can be performed asynchronously, it is possible to write data to the data memory or main memory by discharging write data one after another during the bus's free time. In addition, the hit ratio can be improved by performing the store buffer hit determination at the same time as the cache hit determination in the directory memory section.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the invention applied to a cache memory with a built-in cache controller, and FIG. FIG. 3 is a block diagram showing the configuration of the main part of a comparison circuit that compares addresses of store buffers, and FIGS. 4(A) and (B)
) is a flowchart showing an example of a control procedure for reading and writing to the store buffer by the controller, and FIG. 5 is a time chart of the store buffer during a CPU read cycle. Figure 6 is a time chart of the store buffer during a CPU write cycle. Figure 7 is a time chart of the store buffer discharge operation that is executed asynchronously with the CPU cycle. Figure 8 is the configuration of the input port section of the store buffer. Block Diagram Showing an Example FIG. 9 is a system configuration diagram showing an example of the configuration of a microcomputer system employing the buffer storage method. 1... Directory memory, 2... Data memory, 4... Tag comparator, 5... Internal data bus, 6... Write buffer (store buffer), 1
0...Cache memory. Figure 2 crI BH Figure 4 (A) (B) Figure 5 Figure 6 '□ (X5-1←=]- Figure 7 Figure 8

Claims (1)

[Claims] 1. A data memory section into which data transferred from the central processing unit and the main memory is stored, and a directory into which an address tag indicating the storage location on the main memory of the data stored in the data memory section is stored. In a buffer storage device comprising a memory section and a tag comparator that compares an address input from the outside with an address tag read from the directory memory section, a write address supplied from a central processing unit and a tag comparator are provided. 1. A buffer storage device comprising a buffer consisting of a plurality of dual port registers that temporarily holds data. 2. The buffer storage device according to claim 1, wherein each register constituting the buffer is provided with a bit indicating the state of the register. 3. Claim 1, characterized in that writing from the outside and data transfer from a buffer storing write addresses and data supplied from the central processing unit to an internal data memory section are performed asynchronously. Buffer storage as described. 4. It is characterized by being equipped with an address comparator that compares the address supplied from the outside with the address in the buffer, and when the two match, the data in the corresponding register can be output onto the bus. The buffer storage control device according to claim 1 or claim 2.