JPH0131831B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vertical synchronization device for a television receiver.

Conventional configuration and its problems Conventionally, multiple window circuits have been installed to generate an output with a constant pulse width at the required timing using a frequency divider circuit from a frequency twice the horizontal synchronization frequency.
Select one of the window circuits using the vertical synchronization signal obtained by integrating the composite synchronization signal and shaping the waveform.
There is a vertical synchronization device using a window control method in which the vertical synchronization signal is gated using the window and vertical synchronization is performed using the output thereof.

This type of vertical synchronizer can obtain stable synchronization even when the vertical synchronization frequency changes, such as during VTR special playback (still, slow, fast forward, rewind), and also has excellent noise resistance. , a drawback is that correct synchronization cannot be obtained in a weak electric field where the vertical synchronization signal obtained by integrating the composite synchronization signal often disappears. This drawback is due to the following reasons.

Assuming that a normal television signal sent from a broadcasting station is currently being received and a narrow window is selected, if the vertical synchronization signal does not exist within the window due to a weak electric field, the window The circuit resets itself after the widest window that is different from the current window closes. Since this reset signal is used for vertical output, synchronization will be performed at a timing much later than the actual one.
Synchronization is disrupted.

Purpose of the invention The present invention solves the above-mentioned conventional problems.
An object of the present invention is to provide a window control type vertical synchronization device with good vertical synchronization characteristics in a weak electric field.

Composition of the Invention The vertical synchronization device according to the present invention generates a reset signal immediately after the window closes if there is no vertical synchronization signal within the window in any window state, and also generates a reset signal in conjunction with the reset signal. Distinguish it from a regular television signal, and if the number of consecutive drops in the vertical synchronization signal is less than the count value set in the counting circuit, the window does not change and synchronization continues at a timing close to the regular one. This makes it possible to improve vertical synchronization characteristics in a weak electric field.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a clock signal with twice the frequency of the horizontal synchronizing signal is input to terminal 1, and is connected to the input of frequency divider circuit 2 and the input of delay circuit 15. Ru. The frequency divider circuit 2 is constructed by connecting ten T-type flip-flops in series, and by combining the outputs of each flip-flop, it is possible to obtain an output with a constant pulse width at a required timing. Frequency divider circuit 2
The output thereof is connected to the inputs of the gate circuit 4, reset signal generation circuit 5, reset signal generation circuit 6, window circuit 8, window circuit 9, and window circuit 18, each forming a required timing pulse. The output of the reset signal generation circuit 6 and the output of the counting circuit 21 are connected to the input of the NAND gate 7, and the output of the counting circuit 21 controls generation of the reset signal. Further, the output of the window circuit 9 and the output of the counting circuit 21 are connected to the input of the NAND gate 10, and the output of the counting circuit 21 controls the generation of a window by the window circuit 9. The output of the window circuit 8 and the output of the NAND gate 10 are connected to the input of the AND gate 11.
A gate circuit 13 is set with the output of the gate 11.

A vertical synchronization signal obtained by integrating and waveform shaping the composite synchronization signal is input to the terminal 12, and the gate circuit 13
Connected to the reset terminal of the The output of gate circuit 13, the output of NAND gate 7, and the output of reset signal generation circuit 5 are connected to the input of NAND gate 14, and the output of this NAND gate 14 is connected to the input of delay circuit 15. Delay circuit 1
5 outputs this input signal in synchronization with the clock to prevent malfunction. The output of the delay circuit 15 is connected to the vertical output terminal 3, the reset terminal of the frequency divider circuit 2, the reset terminal of the gate circuit 4, and the NAND gate 1.
6 and the input of inverter 17.

The output of the gate circuit 4 is sent to the reset signal generation circuit 5.
and the reset signal generating circuit 6, and the generation of the reset signal is controlled. The output of the counting circuit 21 is connected to the other input of the NAND gate 16,
The output of this NAND gate 16 is connected to the clock terminal of the counting circuit 21. When the output of the counting circuit 21 reaches the set count value, it becomes L level.
Reset signal generation circuit 6 and window circuit 9 are canceled, and reset signal generation circuit 5 and window circuit 8 are selected. This state is maintained until reset by the output of the counting circuit 20.

The output of the window circuit 18 and the output of the inverter 17 are connected to the input of the AND gate 19, and
The output of gate 19 is connected to a counting circuit 20.
If the vertical output, which is the output of the inverter 17, exists within the window created by the window circuit 18,
By producing an output from the AND gate 19,
To detect whether it is a legitimate television signal.

In addition to the output of the AND gate 19, the counting circuit 20 also receives the output of the AND gate 19.
The output of the inverter 17 is also input, and the number of times the output of the AND gate 19 occurs continuously in a vertical period is counted. When the set count value is reached, an output is generated, and when the counting circuit 21 is reset by this output, At the same time, the output of the counting circuit 21 becomes H level, and the reset signal generating circuit 6 and window circuit 9 are selected.

FIG. 2 shows a specific example of the main part. In FIG. 2, parts corresponding to those in FIG. 1 explained earlier are given the same reference numerals, and detailed explanation thereof will be omitted.

Next, in FIG. 3, a, b, c, and d are the waveforms of the main parts when a normal television signal or a standard reproduction signal of a VTR is received and the window circuit 9 is selected. a is the waveform of the vertical synchronization signal obtained by integrating and shaping the composite synchronization signal, and is input to the input terminal 12. b is a window waveform formed by the window circuit 9 and output from the AND gate 11. c is gate circuit 1
This is the output waveform of No. 3. d is the waveform of the vertical output appearing at terminal 3, and c is the waveform of the delay circuit 15.
This makes it synchronized with the clock. e
is the signal output from the reset signal generating circuit 6 when the pulse of a does not exist within the window of b, and f is the waveform of the vertical output appearing at the terminal 3 at that time.

g, h, i, and j are the waveforms of the main parts when the vertical synchronization signal, such as the signal during special playback of a VTR, fluctuates and the window circuit 8 is selected;
Corresponds to b, c, d. k is a signal output from the reset signal generating circuit 5 when the pulse g does not exist within the window h, and l is the waveform of the vertical output appearing at the terminal 3 at that time.

If the count value currently set in the counting circuit 21 is M, then within the window b (for example, from the 512th clock to the 524th clock in the case of NTSC system)
If the pulse a does not exist continuously for M vertical periods, the output of the counting circuit 21 switches the window from b to h (for example, from the 384th clock to the 544th clock in the case of the NTSC system). Also, if the count value set in the counting circuit 20 is N, then
Inside the window (NTSC) by the window circuit 18
For example, if the vertical output of j exists continuously for N vertical periods (from the 523rd clock to the 525th clock), the counting circuit 21 is reset by the output of the counting circuit 20, and the window is switched from h to b. Change.

The features of this circuit are the reset signal generating circuit 6 and the window circuit 18, which will be explained below. 3 is a window waveform formed by the window circuit 18. In FIG. This window output is input to the AND gate 19 together with a signal obtained by inverting the vertical output by the inverter 17, and the configuration is such that an output is generated from the AND gate 19 if the vertical output is at the timing of a regular television signal. Therefore, the condition is that this window includes the normal vertical output d and does not include the vertical output f generated by the reset signal generating circuit 6 and appearing at the terminal 3. As an example of the NTSC system, as shown in FIG. 3, if window b closes at the 524th clock, the vertical output d will be a pulse from the 524th clock to the 525th clock even in the last case. Also, assuming that the reset signal e is generated at the 526th clock, the vertical output f is
Occurs at the 527th clock. Therefore, window m should be closed at the 525th or 526th clock. As an example, window m is
From the 523rd clock to the 525th clock.

In the vertical synchronization device configured in this way, even if the vertical synchronization signal input to the terminal 12 is lost, the timing close to the normal vertical output (in the example of FIG. Since the vertical output is generated based on the clock difference), there is little synchronization disturbance, and since the vertical output is determined and counted as to whether it is normal or irregular, the window can be switched accurately.

Effects of the Invention As detailed above, according to the present invention, in addition to the conventional advantages of the window control method such as after-sound resistance and synchronization stability during VTR special playback, the synchronization characteristics during weak electric fields can be improved. This is something that can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a vertical synchronizer according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing the wiring of the main parts of the device, and FIG. 3 is a, b, c, d, e, f,
g, h, i, j, k, l, and m are waveform diagrams of each part for explaining the operation of each part of the device, respectively. 1...Clock input terminal, 3...Vertical output terminal, 1
2...Terminals for inputting the vertical synchronization signal obtained by integrating and waveform shaping the composite synchronization signal, 7, 10, 14, 16
...NAND gate, 11, 19...AND gate, 1
7...Inverter.

Claims (1)

[Claims] 1. A frequency divider circuit that receives and divides the frequency of a clock signal with a repetition period twice that of the horizontal synchronization signal, and multiple window circuits that generate an output of a constant pulse width from the output of this frequency divider circuit at the required timing. and any one of the plurality of window circuit outputs according to the vertical synchronization signal obtained from the composite synchronization signal.
The vertical synchronization device is a window control type vertical synchronization device, which gates the vertical synchronization signal using a window of a window circuit output, and performs vertical synchronization using the gate output. A clock signal input terminal that inputs a clock signal having a clock signal, a frequency divider circuit that divides the frequency of this clock signal and is reset by a reset signal, and generates an output of a constant pulse width at a required timing from the output of this frequency divider circuit. a first window circuit that generates an output from the output of the frequency divider circuit that has a narrower pulse width and a different timing than the output of the first window circuit; A reset signal is generated only when the vertical synchronization signal obtained from the composite synchronization signal and the output of either one of the output of the circuit and the output of the second window circuit are input, and the vertical synchronization signal is present within the window. a first gate circuit that outputs a reset signal after this window closes when the first gate circuit receives the output of the first window circuit and there is no vertical synchronization signal within the window; When the output of the second window circuit is input to the first reset signal generating circuit that generates the reset signal and the first gate circuit and there is no vertical synchronization signal within the window, the window closes. a second reset signal generation circuit that generates a reset signal after the frequency divider circuit has passed, and a third window circuit that generates an output from the output of the frequency divider circuit that has a narrower pulse width and a different timing than the output of the second window circuit. and,
A second gate circuit generates an output only when the reset signal exists within the window of this third window circuit, and the output of this second gate circuit is counted and this output is N vertical synchronization (N is 0
a first counting circuit that generates an output when the reset signal is successively generated (a larger integer); and a first counting circuit that generates an output every time the reset signal is counted M times (M is an integer larger than N); a second counting circuit which is reset by the output; and one of the first window circuit and the second window circuit is selected by the output of the second counting circuit, and the first reset signal generating circuit means for selecting one of the second reset signal generation circuits; and a means for selecting one of the second reset signal generation circuits; and inputting the output of the first gate circuit and the output of the first and second reset signal generation circuits; means for generating a reset signal to the frequency dividing circuit even when
A vertical synchronizing device characterized in that the output of the means for generating the reset signal is a vertical output for applying vertical synchronization.