JPH0131830B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field The present invention relates to an apparatus for decoding and reproducing encoded signals such as facsimile, and in particular, the present invention relates to an apparatus for decoding and reproducing encoded signals such as facsimile, and in particular, for decoding and reproducing encoded signals such as facsimile, etc. The present invention relates to an image signal encoding device that reproduces encoded signals.

(b) Technical background In the field of reproduction transmission technology or image processing (optical character reading processing) technology, encoding technology for encoding (code compression, band compression) images read from manuscripts, etc., and this code Decoding techniques for decoding converted image signals are generally known. In such encoding/decoding techniques, when compressing signals for each unit scanning line, the image signal obtained from the immediately previous scan (referred to as the previous line image signal)
It encodes the change at that time by comparing it to
Dimensional compression techniques are being used to further improve compression efficiency.

(c) Prior Art FIG. 1 is a diagram for explaining a decoding device for an image signal encoded using a conventional two-dimensional compression method. In the figure, 1 to 3 are memories, 4 and 5 are selector circuits (hereinafter referred to as selectors), 6 is a decoding circuit,
7 and 8 are counters, and 9 is a control section.

Each of the memories 1, 2, and 3 has a capacity equivalent to the number of pixels obtained when scanning a document on which an image is recorded once, and each memory is divided into its own functions. use In other words, the first
2 is a decoding memory that stores the image signal of the scanning line of the unit in which the coded signal is decoded, and the second is a reference memory that stores the decoded previous line image signal that is used for reference in order to decode the image signal. can be,
The third is used as a recording memory for supplying the decoded image signal to the recording section. Also, each memory 1, 2,
3 has selector 4, in order to increase its usage efficiency.
5, the functions are controlled to be switched and used cyclically.

The operation will be explained below.

First, selectors 4 and 5 set memory 1 as recording memory and memory 2 as reference memory.
Furthermore, the memories 3 are each allocated as decoding memories.

That is, the image signal read from the memory 1 is supplied via the selector 5 to a recording unit such as a printer (not shown), and the image signal read from the memory 2 is supplied via the selector 5 to the decoding circuit 6 as a reference image signal. be done. The memory 3 is also supplied with sequentially decoded image signals as pixels from the decoding circuit 6 via the selector 4. The decoding circuit 6 is supplied with the received encoded image signal and the reference image signal read out from the memory 2, and decodes the received encoded signal by referring to the reference image signal and decodes the image signal as the number of pixels. Output.

The counter 7 counts the number of image signals (the number of pixels) decoded by the decoding circuit 6 and supplied to the memory 3, and outputs an output to the control unit 9 when the number of pixels for one line is counted.

On the other hand, in parallel with this, the output timing from the memory 1 used as a recording memory differs from the output timing of the above-mentioned decoding process (image signal from the decoding circuit 6), and the recording timing of the recording device (not shown) is used. The decoded image signal is output via the selector 5. The number of pixels of this output image signal is counted by a counter 8, and when the image signal corresponding to the number of pixels for one line is read out, an output is issued.

The control unit 9 receives outputs from the two counters 7 and 8 that count the number of pixels for one line and outputs a switching command to the selectors 4 and 5, thereby using the memory 1 as the restoration memory and the memory 2 as the recording memory. Furthermore, the memory 3 is switched so that it can be used as a reference memory.

Thereafter, this circuit operates to sequentially read out the recorded image signal and the reference image signal from each of the memories 2 and 3 in the same manner as described above, and to supply the decoded image signal to the memory 1. Furthermore, when recording output and decoding input are completed in this state, selectors 4 and 5 switch to memory 1.
is used as a reference memory, memory 2 is used as a decoding memory, and memory 3 is switched so that it can be used as a recording memory, and the same process is repeated until the encoded image signal input to the decoding circuit 6 can be finally recorded. It is output from the selector 5 as an image signal.

(g) Disadvantages of conventional methods In the conventional decoding device described above, three types of memory are used when outputting decoded image signals, but the functions of each memory are cyclically switched to obtain usage efficiency. is carried out, for which each
Since it is necessary to have a capacity corresponding to the number of pixels for a line, there is an inconvenience that the size is increased. Furthermore, even after decoding the received encoded signal and storing one line in memory, the stored data can only be output to supply the recording unit until the next one line of image is decoded. It has the disadvantage of requiring a waiting period.

(d) Objective of the present invention The objective of the present invention is to eliminate the above-mentioned conventional drawbacks,
It is an object of the present invention to provide an image signal decoding device that is small in size and capable of recording at high speed.

(e) Structure of the invention In order to achieve the above object, the present invention includes the following:
Focusing on the fact that the readout amount of the reference image signal and the input amount of the decoded image signal are usually the same and at the same timing, the above-mentioned decoding memory and reference memory are used together, and once the decoding It is possible to immediately supply the captured image signal to the recording unit as a recording image signal, and the configuration of the present application to achieve this purpose has a capacity to store the image signal as many as the number of pixels of a unit scanning line. , a shift register means for storing an image signal obtained by decoding the received encoded signal as a pixel, and the received encoded signal and the decoded image signal of the previous running line read from the shift register means are sequentially inputted. , a decoding means for supplying an image signal obtained by decoding the encoded signal with reference to the decoded image signal as a pixel to the shift register means, and counting the number of pixels output from the decoding means for the unit scanning. A counting means that outputs an output when counting the number of pixels of a line, and means that supplies an image signal of the number of pixels of a unit scanning line of the shift register to a recording section when the output from the counting means is input. It is characterized by being prepared.

A detailed explanation will be given below based on examples.

(f) Embodiment FIG. 2 is a block diagram of an embodiment of the present invention. In the figure, 6 is a decoding circuit, 10 is a shift register that stores a decoded image signal corresponding to one line of pixels, 11 is a latch circuit (hereinafter referred to as latch), 12 is a counter, 13 is a recording section, C is a decoded image signal, P is a decoded image signal, and R is a reference image signal.

The counter 12 counts +1 at timing t, which is output every time one pixel is decoded from the decoding circuit 6, and when the count value becomes equal to the number of pixels for one line, the latch 11 selects the shift register 10. It outputs a signal Q that latches the decoded image signal P stored in the memory, and also resets itself.

The shift register 10 also has a decoded image signal P.
is input at timing t, the stored image signal of the previous line is shifted at the same timing t, and a reference image signal R is output.

The operation will be explained below.

When the encoded image signal C is input to the decoding circuit 6, the decoding circuit 6 publicly recognizes the input decoded image signal C while referring to the reference image signal R output from the shift register 10 at timing t. This decoded image signal P is supplied to the shift register 10 at the same timing t.

At the same time, the counter 12 also counts the pixels supplied to the shift register 10 at timing t. The decoded image signals P sequentially decoded in the above-mentioned procedure are then stored in the shift register 10, and when the counter 12 counts the number of pixels for one latch, the output Q causes the latch 11 to store the image signals in the shift register 10. The decoded image signal P stored in is latched. The decoded image signal P latched by the latch 11 is recorded by the recording section 13 on recording paper (not shown). In parallel with this recording process, the encoded image signal C of the next line is supplied to the shift register 10 in the same manner as described above.

In the above embodiment, the shift register means is explained as a shift register in which every time one pixel is input from the previous stage, another pixel is output from the latter stage, but the present invention is not limited to this, and for example, one line Of course, a memory having a capacity for the number of pixels may also be used.

When using a memory, a so-called write pointer (counter) indicating the write address for this memory and a read pointer (counter) indicating the read address are provided, and it is possible to prevent the address indicated by the read pointer from exceeding the address indicated by the write pointer. No known control is required.

Further, in the above embodiment, the reference image signal used when decoding the image signal of one pixel is 1
Although the explanation has been made using signals corresponding to pixels, the present invention is not limited to this, but when using the write pointer and read pointer as described above, it is necessary to prevent the number of signals read from the memory from becoming less than the number of written signals. In addition, it is also possible to use a plurality of already stored decoded reference image signals as long as the number already read out for one line of signals does not become less than the number of signals.

(h) Effects of the Invention As described above, according to the present invention, one line of shift register means is used both as a reference memory and a decoding memory, so the memory and its control circuit are saved, and the encoded signal is It is also possible to shorten the waiting time from when the data is decoded until it is supplied to the recording means.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional decoding device, Figure 2 is a block diagram of a conventional decoding device.
The figure is a block diagram of one embodiment of the present invention. In the figure, 6 is a decoding circuit, 10 is a shift register, 11 is a latch circuit, 12 is a counter, and 13 is a recording section.

Claims (1)

[Scope of Claims] 1. Shift register means having a capacity to store an image signal as many as the number of pixels of a unit scanning line, and storing an image signal obtained by decoding a received encoded signal as a pixel; The decoded image signal of the previous scanning line read out from the shift register means is sequentially input, and the encoded signal is referred to and the decoded image signal is supplied as a pixel to the shift register means. a decoding means that counts the number of pixels output from the decoding means and outputs an output when the number of pixels of the unit scanning line is counted; 1. A decoding device for an image signal, comprising means for supplying an image signal corresponding to the number of pixels of a unit scanning line of a shift register to a recording section.