JPH01313959A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the short between layers by a method wherein, in the case of opening a contact hole on a wiring layer, a lower wiring layer is arranged in this region. CONSTITUTION:When a contact hole is opened on a first aluminum wiring 5, and said layer is connected with a second aluminum wiring 7, an electrode composed of polycrystalline silicon 3 is formed under a region where the contact hole is opened on the first aluminum wiring 5. Thereby, even if the contact hole and the first aluminum electrode 5 of a substratum are misaligned by positioning shift with each other, the progress of the etching of the contact hole is stopped at the part of the polysilicon, since the polysilicon electrode 3 exists under the contact hole. Thereby the short between the semiconductor substrate 1 and the second aluminum wiring 7 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a contact portion that connects wiring layers.

[Conventional technology]

In recent years, a semiconductor device having a two-layer aluminum structure as shown in FIG. 3 has been developed as an integrated circuit device that uses multilayer wiring technology to improve the degree of integration. A contact between the first aluminum electrode 5 and the second aluminum electrode 7 was formed on the first aluminum electrode 5 formed on the field region.

[Problem to be solved by the invention]

In the conventional semiconductor device described above, the interlayer insulating film 4 in which the holes are formed, the interlayer insulating film 4 underlying the first aluminum 5, and the field insulating film 2 are etched by anisotropic plasma etching for contacts, which has been frequently used in recent years. Because it is not possible to obtain a large selectivity ratio, if the contacts are misaligned during the photolithography process or the first aluminum 5 is thinned, a hole that reaches all the way to the semiconductor substrate l as shown in Figure 3 may be formed. This has the disadvantage that the second aluminum electrode 7 short-circuits with the semiconductor substrate, resulting in a defect, which significantly reduces the yield of semiconductor devices.

[Means to solve the problem]

The present invention provides a second method for a semiconductor device having a multilayer wiring structure.
Under the wiring layer in a region where a contact hole is formed on the wiring layer of the layer, a wiring layer which is a layer lower than this wiring layer and has a larger pattern than this contact hole is arranged.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.

In this embodiment, a case is described in which a contact hole is formed on the first aluminum wiring 5 and connected to the second aluminum wiring 7. Here, an electrode made of polycrystalline silicon 3 is formed below the region where the contact hole is to be formed on the first aluminum wiring 5 . In this way, even if the first aluminum electrode 5 on the base is removed due to misalignment of the contact hole, etching will stop at the polycrystalline silicon because the polycrystalline silicon electrode 3 is located below. There is no possibility that the semiconductor substrate 1 and the second aluminum wiring 7 will be short-circuited. If the underlying polycrystalline silicon 3 is made floating or set at the same potential as the first and second aluminum wiring layers, the device will not be defective.

FIG. 2 is a longitudinal sectional view showing a second embodiment of the invention.

Here, an n-type diffusion layer 8 is disposed below a region on the first aluminum 5 where a contact hole is to be formed. In this embodiment, since the n-type diffusion layer region 8 formed on the P-type semiconductor substrate 1 is used, in addition to the effect described in the first embodiment, the polycrystalline silicon wiring layer 3 can also be formed near this contact hole. It also has the effect of being able to be used freely to a certain extent and making design easier.

〔Effect of the invention〕

As described above, in the present invention, when a contact hole is formed on a wiring layer in a semiconductor device having multilayer wiring, by placing a lower wiring layer in this area, the contact can be removed from the wiring layer and punched out. Even in such a case, defects such as short circuits between layers can be prevented and the yield of semiconductor devices can be improved.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional view of an embodiment of the present invention, FIG. 2 is a longitudinal sectional view of a second embodiment of the invention, and FIG. 3 is a longitudinal sectional view of a conventional example. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... Field insulating film, 3... Polycrystalline silicon wiring layer, 4
, 6... Interlayer insulating film, 5... First aluminum wiring layer, 7... Second aluminum wiring layer, 8...
...N-type diffusion layer. Agent Patent Attorney Oto Uchihara;
For Rudo Nairo # ( 3; Yukaneyoshi Akira Kunzo j > Yukiji j Yu; "I1 Aluminum 7; 1 Te 2 γ Lumi 4, z; For waste interval tL ( 8 J 72" stratified M3 diagram

Claims (1)

[Claims] In a semiconductor device having a multilayer wiring structure, a wiring layer lower than the wiring layer is formed in a pattern larger than the contact hole below the wiring layer in a region where the contact hole is formed on the wiring layer higher than the second layer. A semiconductor device characterized in that the semiconductor device is arranged as follows.