JPH01309340A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01309340A JPH01309340A JP14104588A JP14104588A JPH01309340A JP H01309340 A JPH01309340 A JP H01309340A JP 14104588 A JP14104588 A JP 14104588A JP 14104588 A JP14104588 A JP 14104588A JP H01309340 A JPH01309340 A JP H01309340A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- layer
- insulating layer
- aluminum wiring
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000010030 laminating Methods 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 24
- 229910052782 aluminium Inorganic materials 0.000 abstract description 24
- 238000005530 etching Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 238000010586 diagram Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はシリコンゲート構造のＭＯＳ ＩＣ等の絶縁ゲ
ート形の半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate type semiconductor device such as a MOS IC having a silicon gate structure.
第８図は従来の半導体装置、特にそのボンディングパッ
ドの模式的平面図、第９図は第８図の■−■線による断
面構造図である。図において２１はシリコン基板、２２
は絶縁層、２３は多結晶シリコン層、２４は絶縁層、２
５はアルミニウム配線層、２６は絶縁層を示している。FIG. 8 is a schematic plan view of a conventional semiconductor device, particularly a bonding pad thereof, and FIG. 9 is a cross-sectional structural diagram taken along the line ■--■ in FIG. In the figure, 21 is a silicon substrate, 22
2 is an insulating layer, 23 is a polycrystalline silicon layer, 24 is an insulating layer, 2
Reference numeral 5 indicates an aluminum wiring layer, and reference numeral 26 indicates an insulating layer.
シリコン基板２１上に絶縁層１２を積層形成し、この絶
縁層２２上に多結晶シリコン層２３を選択形成し、多結
晶シリコン層２３の上面、側面を含む絶縁層１２上に絶
縁層２４を積層形成してある。そしてこの絶縁層２４上
に前記多結晶シリコン層２３と位置を合せてアルミ配線
層２５を形成し、このアルミ配線層２５の中央部を除（
周縁部及び絶縁層２４上に絶縁層２６を形成して構成し
てある。An insulating layer 12 is laminated on a silicon substrate 21, a polycrystalline silicon layer 23 is selectively formed on this insulating layer 22, and an insulating layer 24 is laminated on the insulating layer 12 including the top and side surfaces of the polycrystalline silicon layer 23. It has been formed. Then, an aluminum wiring layer 25 is formed on this insulating layer 24 in alignment with the polycrystalline silicon layer 23, and the central part of this aluminum wiring layer 25 is removed (
An insulating layer 26 is formed on the peripheral portion and the insulating layer 24.
ところでこのような従来装置にあってはボンディングパ
ッドは表面がアルミ配線ｆｆ１２５で形成されているが
、その表面は下層の絶縁層２４によって平坦化されてい
るため、ボンディングワイヤとの接触面積が小さく、良
好な接触を図るためにはパ。By the way, in such a conventional device, the surface of the bonding pad is formed of aluminum wiring ff125, but since the surface is flattened by the underlying insulating layer 24, the contact area with the bonding wire is small. Pa for good contact.
ド自体の面積を広くする必要があり、またワイヤボンデ
ィングに除してワイヤが滑り易い等の問題があった。It is necessary to increase the area of the board itself, and there are also problems such as the wire slipping easily compared to wire bonding.
本発明は係る事情に鑑みなされたものであって、その目
的とするところはパッド自体の面積が狭くてもワイヤと
の良好な接触が得られ、またポンディングに際してワイ
ヤの滑りも抑制し得る半導体装置を提供するにある。The present invention has been made in view of the above circumstances, and its purpose is to provide a semiconductor pad that can obtain good contact with the wire even if the area of the pad itself is small, and can also suppress the slippage of the wire during bonding. We are here to provide you with the equipment.
本発明に係る半導体装置は配ｖＡ層の表面に凹凸が゛形
成されている。In the semiconductor device according to the present invention, irregularities are formed on the surface of the distribution layer A.
本発明にあってはこれによってポンディングワイヤとの
接触面積が広く、また同時的にポンディングワイヤの滑
りも抑制される。According to the present invention, the contact area with the bonding wire is wide, and at the same time, slippage of the bonding wire is also suppressed.
以下本発明をその実施例を示す図面に基づき具体的に説
明する。第１図は本発明に係る半導体装置（以下本発明
装置という）の模式的平面図、第２図は第１図のｎ−ｎ
線による断面図であり、図中１はシリコン基板、２は絶
縁層、３は多結晶シリコン層、４は絶８ｉ層、５はアル
ミ配線層、６は絶縁層を示している。シリコン基板１の
表面に絶縁層２が一様に形成され、この絶縁層２上に多
結晶シリコン層３が選択形成されている。そしてこの多
結晶シリコン層３の上面を含む絶縁層２上には均一に絶
縁層４が積層形成され、この絶縁Ｎ４上に前記多結晶シ
リコン層３と対応する位置にアルミ配線層５を、更にそ
の上面には基盤目状にアルミ配線Ｎ７を積層形成してあ
る。絶縁層６，８はアルミ配線層５の周縁部に積層形成
した状態となっている。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof. FIG. 1 is a schematic plan view of a semiconductor device according to the present invention (hereinafter referred to as the present invention device), and FIG. 2 is a schematic plan view of a semiconductor device according to the present invention, and FIG.
This is a cross-sectional view taken along a line, and in the figure, 1 is a silicon substrate, 2 is an insulating layer, 3 is a polycrystalline silicon layer, 4 is an 8i layer, 5 is an aluminum wiring layer, and 6 is an insulating layer. An insulating layer 2 is uniformly formed on the surface of a silicon substrate 1, and a polycrystalline silicon layer 3 is selectively formed on this insulating layer 2. An insulating layer 4 is uniformly stacked on the insulating layer 2 including the upper surface of the polycrystalline silicon layer 3, and an aluminum wiring layer 5 is further formed on the insulating layer 4 at a position corresponding to the polycrystalline silicon layer 3. On the upper surface thereof, aluminum wiring N7 is laminated in the shape of a base plate. The insulating layers 6 and 8 are laminated on the periphery of the aluminum wiring layer 5.
アルミ配線層７はアルミ配線層５上面を含む絶縁層４上
に絶縁層６を形成した後、この絶縁層６にアルミ配線層
５が露出するよう選択エツチングを施し、この上からア
ルミ配線層７を堆積することによって形成する。The aluminum wiring layer 7 is formed by forming an insulating layer 6 on the insulating layer 4 including the upper surface of the aluminum wiring layer 5, selectively etching the insulating layer 6 so that the aluminum wiring layer 5 is exposed, and then forming the aluminum wiring layer 7 from above. formed by depositing
このような実施例にあってはアルミ配線層５上にアルミ
配線Ｎ７による凹凸が形成されてここに溶着されるポル
ディングワイヤとの接触面積が大きくなり、またポンデ
ィングワイヤの滑りも抑制される。In such an embodiment, unevenness is formed by the aluminum wiring N7 on the aluminum wiring layer 5, so that the contact area with the paulding wire welded thereon becomes large, and slippage of the paulding wire is also suppressed. .
第３図は本発明の他の実施例を示す模式的平面図、第４
図は第３図のＩＶ−ＩＶ線による断面構造図であり、こ
の実施例ではアルミ配線層５を形成した後、この表面を
含む全面に絶縁Ｎ６を被覆し、アルミ配線層５上の絶縁
Ｎ６に矩形リング状に選択エツチングした後、アルミ層
５と対応する位置にアルミ配線層７を堆積させである。FIG. 3 is a schematic plan view showing another embodiment of the present invention, and FIG.
The figure is a cross-sectional structural diagram taken along the line IV-IV in FIG. After selective etching into a rectangular ring shape, an aluminum wiring layer 7 is deposited at a position corresponding to the aluminum layer 5.
他の構成は第１．２図に示す実施例と実質的に同じであ
り、対応する部分に同じ番号を付して説明を省略する。The other configurations are substantially the same as the embodiment shown in FIG. 1.2, and corresponding parts are designated by the same numbers and their explanation will be omitted.
而してこのような実施例にあってはアルミ配線層５上に
残された絶縁層６にアルミ配線層７が重ねて形成される
結果、凹凸のが高低が大きくなり、ポンディングワイヤ
との接触面積の一層の拡大、及びワイヤの滑り止め機能
の増大が図れる。In such an embodiment, as a result of forming the aluminum wiring layer 7 over the insulating layer 6 left on the aluminum wiring layer 5, the height of the unevenness becomes large and the bonding wire becomes difficult to form. It is possible to further expand the contact area and increase the anti-slip function of the wire.
第５図は本発明の更に他の実施例を示す模式的部分平面
図、第６図は第５図のＶＴ−ＶＴ線による断面図であり
、この実施例では多結晶シリコン層３上に形成した絶縁
層４に多結晶シリコン層３上で選択エツチングを施して
部分的に多結晶シリコン層３を露出させた後、この上か
らアルミ配線層５を均一な厚さに形成してあり、アルミ
配線層５にその下層の絶縁層４の凹凸を転写した状態で
凹凸が形成されている。FIG. 5 is a schematic partial plan view showing still another embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along the VT-VT line in FIG. After selectively etching the insulating layer 4 on the polycrystalline silicon layer 3 to partially expose the polycrystalline silicon layer 3, an aluminum wiring layer 5 is formed to a uniform thickness on top of this. The unevenness is formed on the wiring layer 5 by transferring the unevenness of the insulating layer 4 therebelow.
他の構成は第１，２図に示す実施例と実質的に同じであ
り、対応する部分に同じ番号を付して説明を省略する。The other configurations are substantially the same as those of the embodiment shown in FIGS. 1 and 2, and corresponding parts are given the same numbers and their explanation will be omitted.
第７図は本発明の更に他の実施例４の断面構造図であり
、多結晶シリコン層３上の上面を含む絶縁層２上に絶ｉ
ｔ層４、導電層９、絶縁層１０をこの順序に堆積せしめ
た後、多結晶シリコン層３と対応する位置でその表面が
部分的に露出するよう選択エツチングを施し、この上か
らアルミ配線層５を堆積せしめて高低の大きい凹凸を形
成せしめである。FIG. 7 is a cross-sectional structural diagram of still another embodiment 4 of the present invention, in which there is no insulation layer on the insulating layer 2 including the upper surface on the polycrystalline silicon layer 3.
After depositing the T-layer 4, the conductive layer 9, and the insulating layer 10 in this order, selective etching is performed so that the surface thereof is partially exposed at a position corresponding to the polycrystalline silicon layer 3, and an aluminum wiring layer is deposited on top of this. 5 is deposited to form irregularities with large heights.
以上の如く本発明装置にあってはボンディングパッドの
配線層表面に凹凸が形成されているから、ポンディング
ワイヤとの接合面接が大きく、接合強度も大きくなり、
しかもワイヤのポンディング時にワイヤの滑りも生じな
い等本発明は優れた効果を奏するものである。As described above, in the device of the present invention, since the unevenness is formed on the surface of the wiring layer of the bonding pad, the bonding surface with the bonding wire is large, and the bonding strength is also increased.
Moreover, the present invention has excellent effects such as no wire slippage occurring during bonding of the wire.
第１図は本発明の実施例の模式的平面図、第２図は第１
図のｎ−ｎ線による断面構造図、第３図は本発明の他の
実施例の模式的平面図、第４図は第３図のＩＶ−■線に
よる断面構造図、第５図は本発明の更に他の実施例の模
式的平面図、第６図は第５図のＶｌ−Ｖｌ線による断面
図、第７図は本発明の更に他の実施例を示す断面構造図
、第８図は従来装置の模式的平面図、第９図は第８図の
ＩＸ−ＩＸ線による断面構造図である。
１・・・半導体基板 ２・・・絶縁層 ３・・・多結晶
シリコン層 ４・・・絶縁層 ５・・・アルミ配線層
６・・・絶縁層 ７・・・アルミ配線層
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a schematic plan view of an embodiment of the present invention, and FIG. 2 is a schematic plan view of an embodiment of the present invention.
3 is a schematic plan view of another embodiment of the present invention, FIG. 4 is a sectional structure diagram taken along line IV-■ in FIG. 3, and FIG. 5 is a schematic plan view of another embodiment of the present invention. A schematic plan view of still another embodiment of the invention, FIG. 6 is a sectional view taken along the line Vl-Vl in FIG. 5, FIG. 7 is a sectional structural diagram showing still another embodiment of the invention, and FIG. 8 9 is a schematic plan view of a conventional device, and FIG. 9 is a cross-sectional structural diagram taken along line IX-IX in FIG. 8. 1... Semiconductor substrate 2... Insulating layer 3... Polycrystalline silicon layer 4... Insulating layer 5... Aluminum wiring layer
6... Insulating layer 7... Aluminum wiring layer In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (1)
ィングパッドを備えた半導体装置において、 前記配線層はその表面に凹凸が形成されて いることを特徴とする半導体装置。 ２、配線層は、下層に位置する凹凸が形成された絶縁層
表面に形成されている請求項１記載の半導体装置。 ３、前記配線層は、その表面に他の配線層を選択的に積
層形成して表面に凹凸を形成してある請求項１記載の半
導体装置。[Claims] 1. A semiconductor device comprising a bonding pad having a wiring layer on its surface and an insulating layer underneath, characterized in that the wiring layer has irregularities formed on its surface. Device. 2. The semiconductor device according to claim 1, wherein the wiring layer is formed on a surface of an underlying insulating layer on which projections and depressions are formed. 3. The semiconductor device according to claim 1, wherein the wiring layer has an uneven surface formed by selectively laminating another wiring layer on the surface thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14104588A JPH01309340A (en) | 1988-06-07 | 1988-06-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14104588A JPH01309340A (en) | 1988-06-07 | 1988-06-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01309340A true JPH01309340A (en) | 1989-12-13 |
Family
ID=15282968
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14104588A Pending JPH01309340A (en) | 1988-06-07 | 1988-06-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01309340A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01313948A (en) * | 1988-06-13 | 1989-12-19 | Taiyo Yuden Co Ltd | Thin film circuit board and manufacture thereof |
| JPH0543544U (en) * | 1991-11-12 | 1993-06-11 | 日本無線株式会社 | Electronic element connection terminal structure |
| US5621246A (en) * | 1993-07-09 | 1997-04-15 | Fujitsu Limited | Substrate for mounting integrated circuit semiconductor chips |
| US7026721B2 (en) * | 1999-11-18 | 2006-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of improving copper pad adhesion |
| JP2010153901A (en) * | 2002-11-26 | 2010-07-08 | Freescale Semiconductor Inc | Semiconductor device having bonding pad and method of forming the same |
| US10700019B2 (en) | 2017-08-25 | 2020-06-30 | Infineon Technologies Ag | Semiconductor device with compressive interlayer |
| US10734320B2 (en) | 2018-07-30 | 2020-08-04 | Infineon Technologies Austria Ag | Power metallization structure for semiconductor devices |
| US11031321B2 (en) | 2019-03-15 | 2021-06-08 | Infineon Technologies Ag | Semiconductor device having a die pad with a dam-like configuration |
| US11127693B2 (en) | 2017-08-25 | 2021-09-21 | Infineon Technologies Ag | Barrier for power metallization in semiconductor devices |
| US11239188B2 (en) | 2016-11-21 | 2022-02-01 | Infineon Technologies Ag | Terminal structure of a power semiconductor device |
-
1988
- 1988-06-07 JP JP14104588A patent/JPH01309340A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01313948A (en) * | 1988-06-13 | 1989-12-19 | Taiyo Yuden Co Ltd | Thin film circuit board and manufacture thereof |
| JPH0543544U (en) * | 1991-11-12 | 1993-06-11 | 日本無線株式会社 | Electronic element connection terminal structure |
| US5621246A (en) * | 1993-07-09 | 1997-04-15 | Fujitsu Limited | Substrate for mounting integrated circuit semiconductor chips |
| US7026721B2 (en) * | 1999-11-18 | 2006-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of improving copper pad adhesion |
| JP2010153901A (en) * | 2002-11-26 | 2010-07-08 | Freescale Semiconductor Inc | Semiconductor device having bonding pad and method of forming the same |
| US11239188B2 (en) | 2016-11-21 | 2022-02-01 | Infineon Technologies Ag | Terminal structure of a power semiconductor device |
| US10700019B2 (en) | 2017-08-25 | 2020-06-30 | Infineon Technologies Ag | Semiconductor device with compressive interlayer |
| US11127693B2 (en) | 2017-08-25 | 2021-09-21 | Infineon Technologies Ag | Barrier for power metallization in semiconductor devices |
| US10734320B2 (en) | 2018-07-30 | 2020-08-04 | Infineon Technologies Austria Ag | Power metallization structure for semiconductor devices |
| US10978395B2 (en) | 2018-07-30 | 2021-04-13 | Infineon Technologies Austria Ag | Method of manufacturing a semiconductor device having a power metallization structure |
| US11031321B2 (en) | 2019-03-15 | 2021-06-08 | Infineon Technologies Ag | Semiconductor device having a die pad with a dam-like configuration |
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