JPH01305682A - Teletext receiver - Google Patents

Abstract

PURPOSE:To move a display position without making the recording position of a display memory variable by providing the display memory, a latch, a display signal generating circuit, a display processor, and a switching circuit. CONSTITUTION:After a character multiplex signal is sampled at a sampling circuit 6, decoding processing is executed for the sampled signal at a control circuit 33, and while non-compressed character information is recorded in a display memory 14, compressed character information is recorded in a display memory 30. When the respective pieces of character information in the respective display memories 14 and 30 are reproduced to RGB, YS and YM signals at display processing circuits 15 and 31 and displayed, the RGB, YS and YM signals are added to a switching circuit 34 together with an image RGB signal. Further, while the two types of character information are outputted to a display part 18 by switching the outputs of RGB and that of image RGB with a control signal from the control circuit 33, the reproduced YS signal, and a display position signal from the display signal generating circuit, the contents of latches 23-27 are made variable when the display position is made variable. Thus, the display position of reduced character information can be arbitrarily made variable.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a receiving apparatus for teletext broadcast multiplexed with television radio waves.

2. Description of the Related Art In recent years, code-based teletext broadcasting has been put into practical use, and various built-in teletext receivers have also been developed. Correspondingly, there is a need for diversity in the usage patterns of teletext. One possible method is to watch teletext while viewing television images, or to view multiple different teletext programs or pages at once.

Hereinafter, a conventional teletext receiver such as a "double telecast receiver" will be explained with reference to the drawings.

FIG. 9 shows a block diagram of a conventional teletext receiver. In FIG. 9, 1 is an input terminal for a composite video signal. 2 is a video RGB input terminal. 3 is a synchronization pre-separation circuit that synchronizes and separates the video signal, and the horizontal synchronization signal,
Create a vertical sync signal. A clock generation circuit 4 generates a system clock, and generates a clock synchronized with a horizontal synchronization signal. Reference numeral 5 denotes a display address generation circuit for displaying decoded character information, which operates on a display address of a display memory 14, which will be described later. Reference numeral 6 denotes a sampling circuit that extracts the character signal multiplexed during the vertical retrace period of the video signal, converts it into a digital signal, and records it in a field memory to be described later. Reference numeral 7 denotes a field memory for recording character signals for one field, and the memory is accessed in a time-sharing manner by a sampling circuit 6 and a control circuit 9, which will be described later. 8
is a timing generation circuit that creates various timing signals, and sends signals from 10H (horizontal scanning period) to 21H indicating the multiplex period of teletext to the sampling circuit 6, and sends out a system clock to the control circuit 9, and indicates the multiplex period. sending out signals,
It sends a timing signal for sending a signal indicating the boundary of a display period, sends a switching signal to a switch circuit 17 (to be described later), sends a timing signal for address generation to a display address generation circuit 5, and so on.

5 . . ”1 The control circuit 9 normally uses a CPU, and controls the field memory 7 and buffer memory 10, and also controls the memory controller 12 and switching circuit 13, which will be described later.
It sends out address signals, data signals, and read/write signals.

Buffer memory 10 is for recording character signals, and reads character information temporarily recorded in field memory 7 and sequentially records it. Reference numeral 11 denotes an operation unit for performing reception operations. 12 is a memory controller, and a control circuit 9
, the code of the display address sent from the display address generation circuit 5, and the switching control of the CPU period period 7 reading of the switching circuit 13, which will be described later. The display memory 14 is for recording decoded character information, and is composed of about 16 bytes of RAM. 15 is a display processing circuit which reproduces the data recorded in the display memory 14 during the display period and displays RGB, YS
, YM times signal is created.

16 is a character generator with a kanji font;
17 is a switch circuit for switching between a text information RGB signal and a video RGB signal, and 18 is a display tube.

The operation of the teletext receiving apparatus configured as described above will be described below.

First, the user operates the operation unit 11 to request a teletext program. The synchronization separation circuit 3 synchronously separates the video signal input to the video signal input terminal 1 to generate a horizontal synchronization signal and a vertical synchronization signal. The clock generation circuit 4 generates an 11.45 MHz clock synchronized with the horizontal synchronization signal. The timing generation circuit 8 inputs a horizontal synchronization signal and a vertical synchronization signal, and generates signals from the 10th to the 218th periods of the vertical retrace period.
And a signal indicating the multiplex period of the 273H to 284H character signals is applied to the sampling circuit 6. After the sampling circuit 6 performs waveform equalization and error correction, the sampling circuit 6 performs waveform equalization and error correction.
The character signal is recorded in the address area corresponding to. These operations are performed in steps 10H to 21H and 273H to 28 above.
This is executed during the 4H multiplex period, and at other times the field memory 7 is under the control of the control circuit 9. Control circuit 9
reads the character information recorded in the field memory 7 during a period other than the multiplexing period, and then records it in the banner memory 10 one by one if the information is the same as the character information requested by the operation unit 11. The control circuit 9 decodes the stored character information according to the protocol and stores it in the display memory 14 as shown in FIG.
Record using a period other than (e).

The areas of Fig. 7), (c), (c) and ni) are the display periods, and taking into account control delays, the control circuit 9 is actually used for display during periods other than those including the feathers. This is a period for controlling the memory 14. During the display period, an address signal from the display address generation circuit 5 is input to the memory controller 12.

The memory controller 12 decodes the address signal and creates a chip select signal for the display memory 14.

Furthermore, the memory controller 12 also creates a switching control signal for the switching circuit 13, and switches to the display side during the display period shown in FIG.

The display processing circuit 15 reads out the display memory 14 according to the display address generated during the display period, and
, YM times the signal conversion. RGB of reproduced text information
, YS, YM multiplied signals, and are displayed on the display tube 18 by switching them to video RGB signals using the switch circuit 17.

By the switching signal applied to the switch circuit 17, as shown in FIG.
A super display mode is being considered that is switched in accordance with the YS signal reproduced in 5. The above two modes are display modes defined by the protocol.

On the other hand, in the display mode shown in Fig. 6, according to the protocol, information of 248 horizontal dots and 204 vertical lines is compressed to 128 horizontal dots and 102 vertical lines and displayed in super mode. Dot, horizontal 2
04 line information can be obtained simply by sampling every other dot in the horizontal direction and every other line in the vertical direction. These processes use a microcomputer for the control circuit 9, so 9.
- Easily obtained by changing the program. Furthermore, by employing a small character font in the character generator 16, it is possible to display a reduced screen with even higher precision, and this has been put into practical use.

Problems to be Solved by the Invention However, in the method described in 1.
If you want to display the display at the position shown in the figure, it is necessary to record the position on the display memory 14 at the position shown in FIG. From position a), (b).

If you try to change to (c), to), display memory 14"
The second recording position also had to be changed correspondingly. Furthermore, in that case, in order to be able to change the display positions of the four locations at any time, such as @), ([:l), ()→, ni) in Figure 7, only one page's worth of information can be recorded. , display memory 14
The disadvantage was that it could not be used effectively.

Furthermore, instead of just superimposing text information on the TV image as in the past,
There is also a growing demand for displaying reduced text information over 204 lines of text information in the vertical direction, or for displaying multiple pieces of reduced text information at arbitrary positions.

The present invention was made in view of the above problems, and when displaying character information that has been superimposed and reduced, the display position can be arbitrarily set without changing the recording position of the display memory, and the display position can be further reduced. To provide a teletext receiver capable of displaying reduced text information on multiple pages at arbitrary positions, and further displaying reduced text information and non-reduced text information in an overlapping manner.

Means for Solving the Problems To achieve this object, the teletext receiving apparatus of the present invention includes a synchronization separation circuit, a sampling circuit for extracting character signals, a control circuit for decoding the character signals, two sets of display memories, and a display. A display signal generation circuit that generates timing and address signals for the display, a latch that sets the display start position, a display processing circuit that reads out text information from the display memory and reproduces it as an RGB signal, a display signal for text information, and a television display signal. It consists of a switch circuit for switching between 11 and \-7, a display section, etc.

According to the configuration of the present invention, after the character multiplex signal is extracted by the extraction circuit, the control circuit performs the decoding process, the uncompressed character information is recorded in the display memory 1, and the character information is stored in the display memory 2.
records compressed character information. The character information in each display memory is converted into RGB, YS, YM by a display processing circuit.
When regenerating and displaying signals, in addition to the video RG daily signal and the switching circuit, the above two types of characters are Information RGB and video RG
When the output of B is switched and outputted to the display section and the display position is varied, the display position of the reduced character information can be arbitrarily varied by varying the content of the latch.

EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a teletext receiver according to an embodiment of the present invention.

In Figure 1, 1 is a video signal input terminal, 2 is a video RG
BG power terminal, 3 is a synchronization separation circuit, 4 is a clock generation circuit, 5 is a display address generation circuit, 6 is a sampling circuit, 7 is a field memory, 10 is a sofa memory, 11 is an operation unit, 12 is a memory controller, 13 14 is a switching circuit, 14 is a display memory, 15 is a display processing circuit, 16 is a character generator, 18 is a display section, and the rest are the same as those shown in FIG. 9.

Further, in the figure, 19 is a display address generation circuit that generates a display address for displaying 128 dots in the horizontal direction and 102 lines in the vertical direction, 20 is the same display address generation circuit as above, 21 is the same display address generation circuit as above,
22 is the same display address generation circuit as above. 23 is a latch for setting the display start address of the display address generation circuit 5; 24 is a latch for setting the display start address of the display address generation circuit 19; 25 is a latch for setting the display start address of the display address generation circuit 19;
\-7 A latch that sets the display start address of the space generating circuit 20;
A latch 26 sets a display start address of the display address generation circuit 21, and a latch 27 sets a display start address of the display address generation circuit 22. 28 is a memory controller that performs processing such as synthesis and decoding of display addresses of the display address generation circuit 19, display address generation circuit 20, display address generation circuit 21, and display address generation circuit 22; 29 is a control signal and address of the control circuit 33; This is a switching circuit that switches between the signal, the control signal of the memory controller 28, and the address signal.

30 is a display memory having a memory capacity of about 16 bytes. 31 is a display processing circuit, display memo IJ 30
Display processing of character information recorded in RGB, YS, Y
Convert the signal by M times. 32 is a timing generation circuit that generates various timing signals.

33 is a control circuit that uses a CPU. 34 is a switch circuit that connects the video RGBG power signal and the display processing circuit 15.
Switching between the RGBG number of the character information from the display processing circuit 31 and the RGBG number of the character information from the display processing circuit 31 is performed using a two-hit signal from the control circuit 33, a signal from the display processing circuit 29, and a signal from the timing generation circuit 32. Perform by signal input.

The operation of the teletext receiving apparatus configured as described above will be described below with reference to FIGS. 2 to 8.

First, from the control circuit 33 to the switch circuit 34. -o,
b, supply the take of -〇. Next, a teletext program is requested using the operation unit 11. As an example, [303J
When a program is requested, the control circuit 33 sequentially stores corresponding information among the character information recorded in the field memory 7 in the buffer memo IJ 10 as shown in the conventional example.

When the information of the 303J program is accumulated for one page, the control circuit 9 accesses the character generator 16 etc. to perform the decoding process and record it in the display memory 14. During the display period rl=+J shown in (b), (c), and (b), after the recorded contents of the display memory 14 are latched, display processing is performed to display RGB.

YS, YM times signal conversion. The switch circuit 34 receives a control circuit 3315 as a switching control input signal.
.

2 hits of the control signal from the timing generation circuit 32
signals from the display processing circuit 29 and the display processing circuit 31
The signal from is being input. The input versus output characteristics are shown in FIG. The switch circuit 34 is already connected.

20. Since the signal b1=O is recorded, one character information is displayed on the entire screen of the display unit 18 according to the YS signal of the display processing circuit 15 as shown in FIG.

Next, the control circuit 33 switches to the switch circuit 34. -1゜bl
A description will be given of when a teletext program is requested after recording -0. First, the display screen at this time is a super screen with 128 dots in the horizontal direction and 102 lines in the vertical direction, and the display position is shown in FIG. 7 (a) and (b), as shown in FIG. , () → , any 1 of
It can be displayed in several locations.

- For example, by operating the operation unit 11, the teletext [305J]
When a program is requested, the control circuit 33 performs decoding processing, first records the decoded character information in the buffer memory 10, and then records it in the display memory 30 every other dot in the horizontal direction and every other line in the vertical direction. Next, control circuit 3
3 records the memory address of the display memory 30 at point (e) in FIG. 7 in the latch 27 using the vertical blanking period of the television broadcast. The timing generation circuit 32 generates display gate signals (A), (C), (C) and (C) shown in FIG. 7, and displays them on the display address generation circuit and switch circuit according to the position to be displayed. Sending a gate signal. - For example, when displaying character information as a child screen in the location shown in FIG.
A display gate signal corresponding to FIG. 7 and a strobe signal are sent out at point (e) so as not to be output to other display address generation circuits. Figure 5 shows these timings on the horizontal time axis, and Figure 5F corresponds to the horizontal display gate signal in Figure 7), and Figure 5G corresponds to the horizontal display gate signal.
corresponds to FIG. 7(e). By the way, in Figure 5 A
is an input video signal applied to the video signal input terminal 1, C is a horizontal synchronization signal synchronously separated by the synchronization separation circuit 3, and C is a 11.45 MHz clock signal generated by the clock generation circuit 4. Also, regarding the vertical direction, the horizontal 17
...-- Same as the direction display signal.

The display address generation circuit 22 reads out the contents of the latch 27 set in advance using the strobe signal at the timing shown in FIG. 7(e), and sets the display start address.
The horizontal address is created by dividing the 11.45 MHz clock. In the vertical direction, the horizontal synchronizing signal is frequency-divided and outputted to the memory controller 28 as a display address signal only during the period corresponding to (see FIG. 7). The memory controller 28 is shown in FIG. 7 (a).
, (b), (c), and (b) output the address signal of the memory controller 28 to the display memory 30, and also output a chip enable signal and a read/write signal. During other periods, the control circuit 33 controls the display memory.

During the display period, the display processing circuit 31 reads the take of the display memory 30, and then reproduces it into RGB, YS, and YM signals. The switch circuit 34 switches and displays the reproduced text information RGB signal and the video RGB signal input to the video RGB input terminal 2 so that the text information RGB signal is output only during period 18 (see FIG. 7). It is displayed superimposed in section 18 as shown in FIG. In the above explanation, character information is superimposed only in the positions shown in Figure 6, but in Figure 7, (a) and (
If the display is to be displayed in the positions b) and (c), the latch 27 is set in the same manner as described above, and the gate signal to be displayed is sent to the display address generation circuit 22 and the switch circuit 34, and Figure 7 (b), (c), (c
The value of each register is read at point l and set in each display address generation circuit. Also, when displaying character information recorded in areas other than those shown in FIG. 7 on the display memory, only the set values of the register values are changed, and the rest is the same as described above.

Next, the control circuit 33 switches to the switch circuit 34. −0,b,
The operation when a teletext program is requested after recording -1 will be explained. First, on the display screen at this time, character information for four reduced screens is displayed at once as shown in FIG. These operations are performed by recording the character information decoded in the same manner as described above once in the buffer memory 10, and then recording the character information in the horizontal direction once.
When a dot is pressed, character information in the vertical direction is recorded in the display memory 30 every other line. At this time, the switch circuit 34 outputs only the gate signals of the areas (a), (b), (/→, and) in FIG. 7 in which character information is displayed.

Furthermore, areas that are not displayed are displayed in raster colors. Repeat step 2 for 4 screens to complete the screen shown in Figure 3.

Next, the control circuit 33 switches to the switch circuit 34. -1,bl
The operation when a teletext program is requested after recording -1 will be explained. At this time, the display screen displays character information of 248 dots in the horizontal direction and 204 lines in the vertical direction, superimposed with character information of 128 dots in the horizontal direction and 102 lines in the vertical direction, as shown in FIG. As described above, these operations first request a teletext program and record the decoded character information in the display memory 15. The decoded character information is also recorded in the display memory 30 in the same manner as described above. The timing generation circuit 32 is the switch circuit 3
4, a display gate signal corresponding to FIG. At this time, when changing the display position of the reduced screen, the display address generation circuit 22
The display gate signal sent to the switch circuit 34 and the display gate signal sent to the switch circuit 34 are shown in FIG.
Send one or more of the following. Furthermore, when changing the display contents to another reduced screen, the display can be done by changing the contents of the latch paired with the display address generation circuit. Also, when displaying multiple reduced screens, after sending display gate signals to the display address generation circuit 19, display address generation circuit 20, display address generation circuit 21, and display address generation circuit 22, set the latch. Let's do it. At the same time, display gate signals for a plurality of reduced screens are sent from the timing generation circuit 32 to the switch circuit 34, and the switch circuit 34 is switched for display.

Note that the above-described switching of the display gate signal and switching of the switch circuit can be realized by a combination of a gate circuit, a selector, and the like.

Effects of the Invention 21 To-7 As stated in 2, the present invention provides a synchronization separation circuit, a sampling circuit,
By providing a control circuit, display memory, latch, display signal generation circuit, display processing circuit, and switch circuit, when character information is reduced and displayed in a superimposed manner,
The display position can be moved without changing the recording position of the display memory, and a plurality of programs can be displayed on a reduced screen. Furthermore, it becomes possible to display reduced character information at an arbitrary position superimposed on unreduced character information, which has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a teletext receiver according to an embodiment of the present invention, FIG. 2 is a front view showing an example of displaying text information, and FIG. 3 is a front view showing an example of displaying reduced text information. FIG. 4 is a characteristic diagram of the switch circuit of the present invention, FIG. 5 is a horizontal timing diagram of the present invention, FIG. 6 is a front view showing an example of superimposed display, and FIG. 7 is character information of the present invention. FIG. 8 is a front view showing still another display example of the present invention, and FIG. 9 is a block diagram of a conventional example. 22 To-1 3-...Synchronization separation circuit, 6 ・Sampling circuit, 7 field memory, 23, 24, 25, 26° 27 ・Latch, 5, 19, 20, 21, 22 ・Display address generation circuit, 32 --- Timing generation circuit, 33 ・Control circuit, 14.30 ・Display memory, 15.31 ・
Display processing circuit, 34 - Switch circuit.

Claims (3)

[Claims] (1) A synchronous separation circuit that synchronously separates television video signals;
a sampling circuit that extracts a character signal multiplexed on a television video signal, a memory that records the extracted character signal, a control circuit that decodes the character signal, and a display memory that records the decoded character information; A display signal generation circuit that creates timing and address signals for display, a latch that sets a display start position, and a display processing circuit that reproduces character information recorded in the display memory into a display signal such as an RGB signal. Equipped with a switch circuit that switches between a character information display signal and a video signal display signal, when recording decoded character information in the display memory, the character information is compressed in the horizontal and vertical directions and recorded in the display memory. When information for one page or multiple pages is sequentially recorded and the display position is varied by the display signal generation circuit during display, the latch contents are varied accordingly, resulting in a single page recorded in the display memory. A teletext receiving device characterized in that information on a page or a specific page or a plurality of pages among a plurality of pages can be variably displayed at a display position set by the display signal generating circuit. (2) The teletext receiving apparatus according to claim 1, wherein the display gate output position of the display timing generating circuit is changed to change the switch circuit so that superimposed display can be performed. (3) Multiple display address generation circuits, display memories, etc. are provided, and the first display memory records decoded character information as is, while the second display memory 2 compresses horizontal and vertical character information. The character information for one or more pages is recorded, and when displayed, the character information for one or more pages is superimposed or the first 2. The teletext receiving apparatus according to claim 1, wherein the text information is displayed in a multiplexed manner with the text information stored in the display memory.