JPH01305634A - Method and device for synchronous catching and tracing - Google Patents

Abstract

PURPOSE:To obtain correct synchronization and further, to shorten a synchronous catching time by closing a normal DLL loop (delay lock loop) when the correlative output of a leading phase arrives at a reference level near a peak value. CONSTITUTION:At the beginning of a synchronous search, an output 12a of an RS latch 12 goes to be '1' and the switch of a switch circuit 10 is caused to be in a VS side. Then, the DLL loop is opened and VCO (voltage control oscillator) 106 is driven by a constant direct current voltage VS. A phase difference detecting signal 203 is closed to a synchronous condition and when the correlative output level of the leading phase rises up and goes over a reference voltage Vrf, the output of a comparator 11 goes to be '1'. Then, the output 12a of the RS latch 12 goes to be '0' and the switch CIRCUIT 10 changes over the switch to a phase difference detecting signal 203 side. After that, the loop is closed and synchronous catching and tracing is executed by operation same as a conventional DLL circuit. Thus, phase transition can be speedily executed and synchronization can be executed to a correct stable point. Then, danger to be a pseudo-stable point is erased.

Description

[Detailed description of the invention] [Industrial application field] Kihachi relates to receivers for spread spectrum communication systems.

[Conventional technology]

Recently, spread spectrum (SS) communication systems have come to be used in a variety of fields such as satellite communication, mobile communication as terrestrial communication, power line carrier communication, and random signal radar. The SS communication method that is mainly used is a direct spreading method that uses an M-sequence code as a spreading code. The present invention is directed to a direct sequence acquisition tracking system using M-sequence codes.

As a synchronization acquisition tracking method, a DLL (delay locked loop) synchronization method is well known. In this DLL synchronization system, a synchronization acquisition tracking circuit that performs phase detection, searches for synchronization, and performs trunking after the search is configured as shown in FIG.

This circuit uses two multipliers 300 and 301 to multiply the received signal 350 by the M-sequence code 351 and 352 having a 2-bit phase difference output from the built-in M-sequence code generator 306. Here, the signal 351 has a leading phase, and the signal 3
52 is the delayed phase. Next, the outputs of the multipliers 300 and 301 are passed through the synthesizer 3 through low-pass filters 302 and 303.
Synthesize with 04. Since the output of the low-pass filter 354 is inverted and combined, a difference in correlation outputs can be obtained. Using this as the phase difference detection signal 355, the voltage controlled oscillator (VCO)
305 and changes the clock of the M-sequence code generator 306 to perform automatic phase control.

[Problem to be solved by the invention]

If the transmission path is ideal, the above-mentioned synchronization acquisition tracking circuit will generate a signal 353, as shown in FIG.
354 and a phase difference detection signal 355 are obtained, and they are synchronized at the stable point indicated by the black circle. However, if the transmission path is not ideal,
The waveform shown in Figure tal (b) (C) is obtained, and stable points indicated by black circles and pseudo-stable points indicated by white circles may occur. 5si is that stable communication can be obtained even when the transmission path is not good.
Since this is an advantage of the n-channel system, it is necessary to avoid a false stable point.

Another drawback is that it takes a long time to acquire synchronization by changing the phase of the M-sequence code generator during the synchronization search stage until synchronization is achieved. This is particularly a problem when attempting to increase the reliability of the SS communication system by increasing the code length.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization method that allows correct synchronization and shortens synchronization acquisition time, and a circuit and a receiving device that implement this synchronization method.

[Failure to solve the problem]

The synchronization method of the present invention uses two multipliers to correlate with two signals of leading phase and lagging phase of the built-in M-sequence code, and inverts and synthesizes the leading phase correlation output and the lagging phase correlation output. VCO (voltage controlled oscillator) by detection signal
A DLL (
In synchronization (delay locked loop), at the beginning of the synchronization search, the loop is opened at the VCO input terminal, the VCO is driven with a constant DC voltage, and the advanced phase correlation output level reaches a reference level close to the peak value. Sometimes the loop is closed.

The leading phase correlation output for detecting the arrival at the reference level uses the leading phase correlation output appearing in the phase difference detection signal or the output of the leading phase multiplier. The concrete implementation circuit includes a switch circuit that switches between the phase detection signal provided on the VCO input side and a constant DC voltage to open and close the loop.
A conventional DLL circuit is modified by providing a comparator for comparing the advanced phase correlation output level with a reference level and a switching control means for a switch circuit based on the output of the comparator. Another concrete realization circuit is a switch circuit that switches the phase detection signal provided on the VCO input side and a constant DC voltage to open and close the loop, and ``At the start of synchronization search, the peak value of the advanced phase correlation output is bolded.'' a comparator whose reference level is a level lower by a certain voltage than the bold value of the peak bold circuit; and a switching control means for switching the switch circuit within M code periods after the output of the comparator is generated. A conventional DLL circuit is provided and modified.

[Effect]

Figure 9 (a) (b) In the fcl waveform, if the reference level Vrf to be compared with the leading phase correlation output level is selected close to its peak value, it can be much higher than the peak value near the pseudo-stable point, so This reference level ■ is exceeded on the leading phase side. Then, normal DLL synchronization is performed, but since phase adjustment is performed as shown by the dotted line in this figure, synchronization is achieved at a stable point rather than at a pseudo-stable point.

In addition, during the search start period when the leading phase correlation output level is low, a constant DC voltage is applied to the voltage controlled oscillator, so the drive clock frequency difference between each M-sequence generator on the transmitting side and the receiving side is large and the phase Adjustment can be performed quickly and the time required to reach the reference level Vrf can be shortened.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an acquisition tracking circuit that closes the regular DL+- loop when the leading phase correlation output reaches a reference level near its peak value. The advanced phase correlation output uses the phase difference detection signal.

In FIG. 1, a received signal 200 is branched into two branches and multiplied by output signals 204 and 205 of an M-sequence code generator 107 in multipliers 101 and 102, respectively. Signal 204. ．．
205 has a leading phase and a lagging phase of the signal 206 by 1 bit, respectively. Signal 206 is used to demodulate received data.

The outputs of the multipliers 101 and 102 are passed through the low-pass filter 103.
．． 104, the leading phase correlation output 201 and the lagging phase correlation output 202 are inverted and combined by a combiner 105.

The combined phase difference detection signal 203 is input to one end of the switch terminal of the switch circuit 10 and the positive terminal of the comparator 11. A predetermined reference voltage V is applied to the negative terminal of the comparator 11.
r f is connected. The switch circuit 10 switches between the constant DC voltage 5 side and the phase difference detection signal 203 side, and controls the VCO 106. The VCO 106 controls the clock frequency that is the output, and the M-sequence code generator 107
Perform phase adjustment.

Switching control of the switch circuit 10 is performed by the comparator 11 and the RS
This is done by latch 12. This control operation will be explained with reference to FIG. At the beginning of the synchronization search, a start signal 400 is input to the RS latch 12, the output 12a is set to "1", and the switch of the switch circuit 10 is set to the - side. This opens the DLL loop, and the VCO 106 receives a constant DC voltage.
, and changes the phase of the M-sequence pattern.

Then, the phase difference detection signal 203 approaches the synchronous state,
When the level rises and exceeds the reference voltage vrf, the comparator 11
The output of the RS latch 12 becomes "1", the output 12a of the RS latch 12 becomes "0", the switch circuit 10 switches the switch to the phase difference detection signal 203 side, the loop is closed, and the conventional D
Synchronous acquisition tracking is performed using the same operation as the LL circuit.

With this operation, the level of the reference voltage (2) is kept close to the positive peak value, so at the leading edge of the leading phase of the phase difference detection signal 203, the comparator 11 becomes "1", and from this position, D
Since it is an LL operation, it synchronizes with the stable point indicated by the black circle and does not reach the pseudo-stable point indicated by the white circle.

In the switch switching control, the signal to be compared with the reference voltage RF by the comparator 11 is a multiplier 103 that takes an advanced phase correlation.
You can use the output of FIG. 2 shows an implementation circuit in which a signal 201, which is the output of the low-pass filter 103, is input to the positive terminal of the comparator 1. This circuit operation is exactly the same as the circuit shown in FIG. 1 described above.

In the embodiment described in FIGS. 1 and 2, the reference voltage V□ of the comparator was set to a predetermined fixed value close to the peak.

The closer the value is to the peak, the less erroneous synchronization occurs, but the peak value may vary depending on the conditions of the transmission path. Therefore,
At first, the peak value is actually measured and the peak value is held, and the level is lowered by a constant value that is smaller than the peak value. And it is sufficient.

FIG. 4 shows a block diagram of this implementation circuit.

This circuit differs from the circuit shown in FIG. 1 in the switch switching control part, and the phase difference detection signal 203 is input to the positive terminal of the comparator 11 and also input to the peak hold circuit 13. The output 13a of the peak hold circuit 13 is sent to the subtracter 14,
It is input to the negative terminal of the comparator 11 as the low level 13b. The output of the comparator 11 is inputted as a signal 11a to the S terminal of the RS launch 12' with reset (R) priority, and is also inputted as a signal 11b to the timer 15. This timer 15 is reset when the start signal 400 is input manually, and its output 15a becomes "1".

Then, when the input signal 11b becomes negative, measurement starts, and when the measurement reaches a certain time t, the output 15a is set to 0''.When the input signal 11b becomes positive, the previous time count becomes zero and becomes negative again. From then on, I started taking measurements.

The output 15a of the timer 15 is input to the R terminal of the RS latch 12'.

The output 12a of the RS launch 12' controls switching of the switch/7-inch circuit 10.

The above switch switching control operation will be explained with reference to FIG.

First, when the star 1 signal 400 is input, the timer 15 is cleared, its output 15a becomes "1", the output 12a of the RS launch 12' becomes 1', and the switch circuit 10
switch is set to the Vs side, and the DLL loop is opened. Further, the peak bold circuit 13 operates, bolds the peak value of the phase difference detection signal 203, and outputs 13a. The signal 1.3b input to the negative terminal of the comparator 11 is as shown in the figure. When synchronization begins and the phase difference detection signal 203 exceeds the top of the precursor hump and becomes lower in level than the signal 13b, the output signals 11a and l of the comparator 11
lb becomes '0'.Then, the timer 15 starts measuring.After that, the signal 11 becomes synchronous with the phase difference detection signal 203.
A pulse indicated by p is temporarily generated at a and 11b. This part is shown enlarged by A in the figure. Due to the pulse p of the timer 15, the measurement up to that point is cleared, and measurement starts again from the falling edge of the pulse p. Note that the RS latch 12' has reset priority, so as long as the timer output 15a is 1'', even if the pulse p occurs, the output 12a is 1'', and the switch circuit 10B.

side and the DLL loop remains open.

Then, after the fall of the pulse p, the timer output is 15.
a becomes "0", and the RS launch 12' has no set priority, and in the next cycle, when the output 11a of the comparator 11 becomes "1" near the peak of the synchronous hump, the RS launch 12'
The output 12a becomes 0'', the switch circuit 10 switches to the phase difference detection signal 203 side, and the DLL loop is closed.The above fixed time t is shorter than the M sequence period, so the next phase difference detection When the signal 203 rises, synchronization can be achieved with the stable point.

In the above embodiment, the phase difference detection signal 203 is used as the input of the comparator 11, but the signal 203 is used as the leading phase correlation output.
01 can be used. (Circuit diagram omitted) FIG. 6 shows a circuit block diagram in which the synchronization acquisition tracking circuit described above is incorporated into a receiver. This example shows a receiving section of a power line carrier communication device, which is connected to a power line through an outlet and receives a spread-modulated received signal from a coupling circuit 80.
The signal is separated from the power signal, amplified by the amplifier 90, and then input to the synchronization acquisition tracking circuit 100 and the demodulator 300.

The demodulator 300 includes a multiplier 300A and a low-pass filter 300B.
Multiply by 6. The output of demodulator 300 is sent out as received data 402 via switch circuit 301 . The switch circuit 301 is on the ground side and the received data 402 is not sent out until the synchronization acquisition tracking circuit 100 starts synchronization search and the DLL loop is closed. The signal 12a that controls the switch when the DLL loop closes is used as a control signal to switch the switch circuit 301 to the demodulator 300 side.

〔Effect of the invention〕

As explained above, the present invention uses the DLL synchronization method to capture and track synchronization in a spread spectrum communication receiver, but at the beginning of the start, the DLL loop is opened and
A constant DC voltage is applied to the voltage controlled oscillator to shift the phase of the M-sequence code generator.

In the conventional circuit, the input to the voltage controlled oscillator was almost zero before synchronization, but the phase shift can be made much faster. In addition, since the loop is closed and the DLL operation is started after the advanced phase correlation output approaches the peak value, synchronization can be achieved with the correct stable point, and there is no risk of a pseudo stable point as in the prior art.

[Brief explanation of the drawing]

Figures 1 and 2 are block diagrams of an embodiment of the synchronization acquisition circuit of the present invention, Figure 3 is a switch control waveform diagram for opening and closing the DLL loop of the above circuit, and Figure 4 is a circuit block diagram of another embodiment. , FIG. 5 is a switch control waveform diagram for opening and closing the DLL loop of the above circuit, FIG. 6 is a block diagram showing an example of a receiver incorporating the synchronization acquisition tracking circuit of the present invention, and FIG.
The figure is a block diagram of a conventional DLL synchronization acquisition tracking circuit, and FIGS. 8 and 9 are waveform diagrams of the circuit. 10-Switch circuit, 11-Comparator, 12--RS
launch, 13-peak hold circuit, 14-subtractor,
15-Timer, 80-Combining circuit, 90-Amplifier, 100-Synchronization acquisition tracking circuit, 101.102-Multiplier, 105-Synthesizer, 106
- Voltage controlled oscillator (VCO), 107- M-series code generator, 300- Demodulator, 301- Switch circuit, 40
(L---Start signal.

Claims (6)

[Claims] (1) In the synchronization method of spread spectrum communication, two multipliers are used to correlate with the two signals of the leading phase and lagging phase of the built-in M-sequence code, and inverting the leading phase correlation output and the lagging phase correlation output. In DLL (delay locked loop) synchronization, which controls a VCO (voltage controlled oscillator) using a phase difference detection signal to be synthesized and shifts the generated phase of the built-in M sequence, at the initial stage of synchronization search, the loop is opened on the VCO input side. , a synchronous acquisition tracking method characterized in that the VCO is driven with a constant DC voltage and the loop is closed when the advanced phase correlation output level reaches a reference level close to a peak value. (2) The synchronization acquisition tracking method according to claim 1, wherein the detection of reaching the reference level is performed based on the output of the phase correlator. (3) In the statement of claim 1 or 2, a switch circuit that switches between a phase detection signal provided on the VCO input side and a constant DC voltage to open and close a loop, and a comparator that compares the advanced phase correlation output level with a reference level. and a switching control means for a switch circuit based on the comparator output. (4) In the statement of claim 1 or 2, a switch circuit that switches between a phase detection signal provided on the VCO input side and a constant DC voltage to open and close a loop, and a switch circuit that opens and closes a loop, and a peak value of an advanced phase correlation output when starting a synchronization search. a holding circuit; a comparator whose reference level is a level lower by a certain voltage than the hold value of the peak hold circuit; and a switching control means for switching the switch circuit within an M-series code period after the output of the comparator is generated. A synchronous acquisition tracking circuit having. (5) A spread spectrum communication receiving device comprising the synchronization acquisition tracking circuit according to claim 3, and provided with means for transmitting the received data after the loop is closed, without transmitting the received data immediately after the circuit is activated. . (6) A spread spectrum communication receiving device comprising the synchronization acquisition tracking circuit according to claim 4, and provided with means for transmitting the received data after the loop is closed, without transmitting the received data immediately after the circuit is activated. .