JPH01305424A - Digital signal processor - Google Patents

Abstract

PURPOSE:To perform the parallel processing of an arithmetic processing and data transfer by separating an input bus which transfers data from a memory to a multiplier from an output bus which transfers a computed result from the multiplier to the memory. CONSTITUTION:When the computation of Ai=BiXCi(i=1-10) is performed, Bi is stored in the memory 30-1 and Ci in the memory 30-2, and the computed result Ai is stored in the memory 30-1. Firstly, B1 and C1 are read out from the memories 30-1 and 30-2, and are inputted to a computing element 23 via input data buses 21-1 and 21-2, and the computed result A1 is stored in a product register 24. A1 stored in the register 24 is written on the memory 30-1 via a shifter 25, an output data bus 22, and a write line 30-1a, and in parallel with the operation, next data B2 and C2 in the memory 30-1 are inputted to the computing element 23 via the data buses 21-1 and 21-2, and the computed result A2 is stored in the register 24.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital signal processing processor used in speech synthesis, digital filters, and the like.

(Prior Art) Digital signal processing processors of various structures have been proposed for use in speech synthesis, digital filters, and the like. The performance required of such digital signal processors was determined by how fast numerical data operations could be performed.

Conventionally, this type of digital signal processing processor was published in the "Go MS320C25 User's Guide.
s Guide) J (1986) Texas Instruments, P, 3-2. The configuration will be explained below using figures.

FIG. 2 is a schematic block diagram showing one example of a conventional digital signal processing processor.

The overall operation of this digital signal processor is controlled by control signals output from a control circuit 1, and one of the two data buses 2.3 has information such as the decimal point position of the data. Shifter 4 for adjusting the data, and a temporary register (T
R register) 5 is connected, and a selector 6 for signal selection is connected to both data buses 2.3.

A multiplier 7 is connected to the output 1 of the temporary register 5 and the selector 6, and the output side of the multiplier 7 is connected to a product register 8 and a shifter 9 for storing multiplication results. An arithmetic logic unit I- (hereinafter referred to as ALU) 11 is connected to the output side of the shifters 4 and 9- via a multiplexer (MUX) 10 for signal selection, and its ALU is connected to the output side of the shifters 4 and 9-.
LUII is an accumulator (AC) for storing data.
C>12 and is connected to the data bus 2 via the shifter 13.

A memory 15 is connected to the data bus 2 via a multiplexer 14, and memories 16 and 17 are also directly connected. These memories 15, 16, and 17 are memories that can read and write data, and their addresses AD
The configuration is such that the designation and modification of is performed by an auxiliary register 8 connected to the data bus 2.

Next, the operation will be explained.

For example, A・=B・×C・・・・(1) However, i=
The calculation operations 1 to 10 will be explained in each step. It is assumed that variable B is stored in memory 5 and variable C1 is stored in memory 6. Further, it is assumed that the calculation result Ai is written into the memory 16.

(1) Step 1 Among the variables B and C1 stored in the memory 15.16,
Variable Bi enters multiplier 7 via multiplexer 14, data bus 3 and selector 6, and variable °C1 enters multiplier 7 via data bus 2 and temporary register 5. Multiplier 7 multiplies variables B, ,C, and the result is A
1 (-81×C1) is placed in the product register 8.

(2) Step 2 The content A1 of the product register 8 is written to the memory 16 via the shifter 9, multiplexer 10, ALU II, accumulator 12, shifter 13 and data bus 2.

(3) Step 3 The variable 82 in the memory 15 enters the multiplier 7 via the multiplexer]-4, the data bus 3 and the selector 6, and the variable C2 in the memory 16 passes through the data bus 2 and the temporary register 5. and enters the multiplier 7. Multiplier 7 multiplies variables B2 and C2, resulting in A2 (-8
2XC2> into product register 8.

(4) Step 4 Write the contents A2 of PRODAG 1 to register 8 to memory 16 via shifter 9, multiplexer 10, ALU II, accumulator 12, shifter 13, and data bus 2.

(5) Steps 5 to 20 Proceed to steps 5 to 18 in the same manner, and step 1
9, the variable B1o is entered into the multiplier 7 through the data bus 3, and the variable C1o is entered into the multiplier 7 through the data bus 2, and the multiplication result A ("Blo
XClo) into product register 8. In step 20, the content A1o of the product register 8 is written to the memory 16 via the data bus 2, and the arithmetic processing is completed.

(Problems to be Solved by the Invention) However, the digital signal processor having the above configuration has the following problems.

Since the input data bus to the multiplier 7 and ALUll and the output data bus from the arithmetic unit are the same, it is not possible to read and write data from the memories 15 and 16 at the same time.

Therefore, even if the arithmetic unit is free, if the bus is not free, calculations cannot be performed, and the ability of the digital signal processor cannot be fully demonstrated.

That is, in FIG. 2, 20 steps are required for 10 multiplications. This takes 1 step for multiplication and 1 memory
This is because one step is required for the transfer to the multiplier 7, and the multiplier 7 is operating only in 50% of the 20 steps. Furthermore, in the case of Fig. 2, there are two arithmetic units, multiplier 7 and ALU II, but if the number of arithmetic units increases, for example, there are two multipliers and one ALU, then A. =B・×C・+D・×E・However, Bi, C
i, Di, Ei: Variable i: 1, 2. ..., n
Considering arithmetic processing such as -1, n, etc., the frequency of use of the bus increases further, and the operating rate of the arithmetic unit decreases.

The present invention is a digital signal processing method that solves the problem that the conventional technology had, in that it is difficult to improve the calculation speed because the operating rate of the calculation unit decreases due to the processing bottleneck caused by the data bus. It provides a processor.

(Means for Solving the Problems) In order to solve the problems, a first invention includes a memory capable of reading and writing data, a multiplier, an ALU, and data read from the memory to the multiplier and the ALU. transmit,
and a data bus for transmitting output data of the multiplier and AI, U to the memory, the data bus comprising first and second input data buses for transmitting input data; an output data bus for transmitting output data; It consists of memory.

In a second invention, in the first invention, the multiplier includes a first and a second multiplier. Further, the data bus includes first, second, third and fourth input data buses for input data transmission and first and second output data buses for output data transmission, The memory includes first, second, and third data buses having read lines connected to the first, second, third, and fourth input data buses, and write lines connected to the first and second output data buses, respectively. and a fourth memory.

Further, in the first and second inventions, a part of the memory may be configured as a first-in/first-out (hereinafter referred to as FIF).
The input data bus may be constructed of a type memory (referred to as O) type memory, or a diode (nh) may be connected between the input data bus and the output data bus.

(Function) According to the present invention, since the digital signal processing processor is configured as described above, the two or four memories can read and write a plurality of variables, and furthermore, data can be read and written from these memories. Providing separate input data buses for inputting data to the multiplier and ALU, and output data buses for writing data from the multiplier and ALU to the memory is advantageous in handling arithmetic processing and data transfer to the memory. This makes it possible to perform the transfer in parallel. Furthermore, providing a FIFO memory as part of the memory simplifies arithmetic processing such as recursive expressions, and further providing a divider allows other arithmetic processing to be performed in parallel with division. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a schematic block diagram of a digital signal processing processor showing a first embodiment of the present invention.

The overall operation of this digital signal processor is controlled by control signals, address signals, etc. output from the control circuit 20, and the first and second input data buses 21-1, 21-2 and output data A bus 22 is provided, and a multiplier 23 is connected to the first and second input data buses 21-1 and 21-2. On the output side of the multiplier 23,
Product register (P
A register 24 is connected, and a shifter 25 for adjusting the decimal point position of data is further connected to its output side. The output side of the shifter 25 is connected to the input data bus 21.
-2 together with a multiplexer for signal selection (MUX>26
The output side of the shifter 25 is also connected to the output data bus 22. The output 1 of the multiplexer 26 is connected via the ALU 27 to the input side of an accumulator (ACC) 28 for data storage, and the output side of the accumulator 28 is connected to the ALU 27, and the output data bus 22 is connected via the shifter 29. It is connected to the.

The output data bus 22 includes a write line 3O-1a.

First and second memories 30-1 and 30-2, which are readable and writable, are respectively connected via 3O-2a. First,
The addresses of the second memories 30-1 and 30-2 are specified by the address signal AD output from the control circuit 20. The second memory 30-2 is connected to the first and second input data buses 21-1 and 21-2 via the readout line 3O-2b and the multiplexer 32. Input data bus 21-1.21-. Connected to 2.

Next, the operation will be explained.

For example, the operation when performing the multiplication in equation (1) above will be explained in each step. Note that the variable Bi is stored in the first memory 30-1, the variable C1 is stored in the second memory 30-2, and the calculation result A is obtained.

is written into the first memory 30-1.

(1) Step 1 Enter variable B1 in memory 30-1 into multiplier 24 via readout line 3O-1b, multiplexer 31 and input data bus 21-1, and read variable 01 in memory 30-2. It is input to the multiplier 23 via line 3O-2b, multiplexer 32 and input data bus 21-2. The multiplier 23 multiplies the variables Bt and C1, and stores the multiplication result A1 (=B1XC1) in the product register 24.

(2) Step 2 Content A1 of the product register 24 is written to the memory 30-1 via the shifter 25, output data bus 22, and write line 3O-1a. In parallel with this, memory 3
Variable B2 in memory 30-1 enters multiplier 23 via readout line 30-1b, multiplexer 31 and input data bus 21-1, while variable 02 in memory 30-2 enters readout line 30-1b, It enters the multiplier 23 via the multiplexer 32 and the input data bus 21-2, and the multiplier 23 multiplies variables B2 and C2, resulting in A2
(=32 XC2) is entered in the product register 24.

(3) Step 3 The content A2 of the product register 24 is written into the memory 30-1 via the shifter 25, the output data bus 22, and the write line 30-1a.

(4) Steps 4 to 11 Proceed to steps 4 to 9 in the same manner, and then step 10.
Then, the variable B1o in the memory 30-1 enters the multiplier 23 via the input data bus 21-1, and the
The variable C1o in 0-2 enters the multiplier 23 via the input data bus 21-2, and the multiplier 23 converts the variable C1o into the variable B1o,
A multiplication of C1o is performed, resulting in A1o(2B1oXC
1o) is entered into the product register 24. Step 11
Then, the content A1o of the product register 24 is written to the memory 30-1 via the output data bus 22, and the multiplication process ends.

In this embodiment, 10 multiplications can be performed in 11 steps. In other words, it is a pipeline operation, so
Zero multiplications can be performed in (n+1) steps. Therefore, in the case of a conventional processor, for example, the above (1)
It takes 20 steps to find Alo of the equation,
Whereas 2n steps were required for 0 multiplications, the 10 setters of this embodiment can reduce the number of steps by about 50%. Note that it is naturally possible to perform other arithmetic operations such as product-sum operations and complex operations using the digital signal processor of this embodiment.

FIG. 3 is a schematic block diagram of a digital signal processor showing a second embodiment of the present invention, and the same elements as those in FIG. 1 are given the same reference numerals.

This digital signal processing processor has four input data buses 21-1 to 21-4, two output data buses 22-1.22-2, and two multipliers 23-1.23. -2, a product register (P register>24-1.24-2, a shifter 25-1.25-2, and a multiplexer (MUX>25-1.25-2), and an input data bus 21. -3.2
1-4 is connected to the multiplier 23-1, and the multiplier 23-
1 is connected to one input side of the ALU 27 via the product register 24-1, shifter 25-1 and multiplexer 26-1. Furthermore, input data bus 21-1
．． 21-2 is connected to the multiplier 23-2, and the multiplier 2
3-2 is the product register 24-2 and shifter 25-2
and is connected to the other input side of the ALU 27 via the multiplexer 26-2. Further, the first, second, third and fourth readable/writable memories 3 whose addresses are specified by the address signal AD outputted from the control circuit n20
0-1 to 30-4, each of these memories 30-1 to 30-4.
The write lines 3O-1a to 3O-4a of 30-4 are connected to the output data bus 22-1.22-2, and the read lines 3O-1b to 3O-3
0-4b are connected to input data buses 21-1 to 21-4, respectively.

In the above configuration, for example, A.=B.×C.+D.×E. . . (2) However, the operation when performing an operation such as i=1 to 10 will be described. Note that the variables B., C., D., and Ei are stored in the memories 30-1, 30-2.
30-3 and 30-4 respectively, and the calculation result Ai
is one of the memories 30-1 to 30-4, for example 30-1
shall be written in.

Multiplication of variables B・, C・(=B・×C) is performed by one multiplier 23-2 as in FIG. 1, and multiplication of variables D・, E・(
=D,
is determined by the ALU 27, and the accumulator 28 and shifter 29
If the data can be written into the memory 30-1 via the output data bus 22-2, the calculation of equation (2) can be performed. If the multipliers 23-1, 23-2 and ALU 27 are fully used in this way, it takes only 11 steps to execute the calculation of equation (2).
It is possible to speed up arithmetic processing without creating a processing bottleneck caused by the data bus.

FIG. 4 is a schematic block diagram of a digital signal processor showing a third embodiment of the present invention, and the same elements as those in FIG. 3 are given the same reference numerals.

In this digital signal processing processor, a FIFO memory 30-1 is used instead of the memory 30-3 and 30-4 in FIG.
3.30-14 is set up, and its FIFO function is 30-14.
13.30-14 write lines 3O-13a, 3O-14
a to output data bus 22-1, 22-2, read line 3
O-13b.

3O-14b are connected to input data buses 21-3 and 21-4, respectively. FIFO memory 30-13.
30-14 requires no addressing, and the data written first is read out first. Therefore, for example, XH=f (X H-1)...(3)
However, when executing a repo expression such as Xl-1' variable Xi; calculation result i; 1 to n, variable X1-1 is
If stored in FO memory 30-12.30-14,
Without specifying the address, those variables
The signals are sequentially read out from the IFO memories 30-13 and 30-14 and subjected to arithmetic processing in the multiplier 23-1, AL[J27, etc. Therefore, multiplier 23-1, 23-2 and ALU 27
It becomes easy to create a program that executes a recursive expression without considering the influence of the depth (number) of the pipeline due to the number of stages.

FIG. 5 is a schematic block diagram of a digital signal processor showing an embodiment of the present invention, and the same elements as those in FIG. 4 are given the same reference numerals.

This digital signal processing processor is the same as the processor shown in FIG. 4, with a divider 40 connected between the input data bus 21-4 and the output data bus 22-1. Fixed-point division typically takes processing steps depending on the number of bits. For example, if you need 16 bits of precision, use 16
Requires steps. Therefore, when the divider 40 is provided, the multiplier 2
It becomes possible to process other calculations using 3-1.23-2, AL027, etc.

Note that the present invention is not limited to the illustrated embodiment; for example, the first embodiment
FI the memory 30-1 or 30-2 in the figure.
It can be configured with FO memory, or input data bus 2 in Figure 1.
Various modifications may be made, such as connecting a divider between 1-2 and output data bus 22, or connecting a divider between input data bus 21-4 and output data bus 22-1 in FIG. is possible.

(Effects of the Invention) As described above in detail, according to the present invention, two or four memories are provided, and the input data bus and output data bus to the multiplier and ALU are provided separately. , it becomes possible to perform arithmetic processing and data transfer to memory in parallel, and it is possible to improve the operation rate of the multiplier and ALtJ and improve the arithmetic capacity. In addition, in order to increase parallel processing capacity, etc., we can increase the number of multipliers,
It is possible to configure multiple arithmetic units by using FIFO memory or providing a divider.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital signal processor according to a first embodiment of the present invention, FIG. 2 is a block diagram of a conventional digital signal processor, and FIGS. 3, 4, and 5 are block diagrams of a conventional digital signal processor. FIG. 4 is a configuration block diagram of a digital signal processor showing second, third, and fourth embodiments of the present invention, respectively. 21-1 to 21-4... Input data bus, 22
゜22-1.22~2...Output data bus, 2
3゜23-1.23-2... Multiplier, 27...
...ALU, 30-1 to 30-4...Memory, 30-13゜30-14...F I FO memory, 3O-1a to 3O-4a, 3O-13a, 3O-
14a...Writing line, 3O-1b to 3O-4b
, 3O-13b. 3O-14b...readout line, 40...
Divider.

Claims (1)

[Scope of Claims] 1. A memory capable of reading and writing data, a multiplier that multiplies data, an arithmetic and logic operation unit that performs arithmetic and logical operations on data, and a multiplier that performs data read/write from the memory. and a data bus for transmitting output data of the multiplier and the arithmetic and logic unit to the memory, the data bus comprising a data bus for transmitting input data. 1st and 2nd
an input data bus for transmitting output data, and an output data bus for transmitting output data, and the memory has read lines connected to the first and second input data buses, and write lines connected to the output data bus. A digital signal processing processor comprising first and second memories. 2. The multiplier includes first and second multipliers, and the data bus includes first, second, third, and fourth input data buses for input data transmission, and output data transmission. first and second output data buses, the memory has read lines connected to the first, second, third and fourth input data buses, and write lines connected to the first and second input data buses. first, second, and
A digital signal processing processor comprising third and fourth memories. 3. The digital signal processing processor according to claim 1 or 2, wherein a part of the memory is constituted by a first-in first-out type memory. 4. The digital signal processing processor according to claim 1, 2 or 3, further comprising a divider connected between the input data bus and the output data bus.