JPH01303730A - Mounting structure of semiconductor element and manufacture thereof - Google Patents
Mounting structure of semiconductor element and manufacture thereofInfo
- Publication number
- JPH01303730A JPH01303730A JP63132676A JP13267688A JPH01303730A JP H01303730 A JPH01303730 A JP H01303730A JP 63132676 A JP63132676 A JP 63132676A JP 13267688 A JP13267688 A JP 13267688A JP H01303730 A JPH01303730 A JP H01303730A
- Authority
- JP
- Japan
- Prior art keywords
- tape
- semiconductor
- semiconductor element
- active surfaces
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000008188 pellet Substances 0.000 claims abstract 6
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- 238000000465 moulding Methods 0.000 abstract description 9
- 239000003795 chemical substances by application Substances 0.000 abstract description 7
- 239000007767 bonding agent Substances 0.000 abstract 2
- 230000003190 augmentative effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000012207 thread-locking agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子の実装構造およびその製造方法に保
り、特に、半導体素子をテープ伏フィルムに実装するい
わゆるＴＡＢ （Ｔａｐｅ ＡｕｔｏｍａｔｅｄＢｏｎ
ｄｉｎｇ）方式に好適な半導体素子の実装構造およびそ
の製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a mounting structure for a semiconductor element and a method for manufacturing the same, and particularly relates to a so-called TAB (Tape Automated Boning) in which a semiconductor element is mounted on a tape-bound film.
The present invention relates to a semiconductor element mounting structure suitable for the ding) method and a method for manufacturing the same.
半導体素子の高密度実装構造およびその製造方法につい
ては、これまでに、例えば、特開昭第６１−２２５８２
５号、特開昭第４ｌ−２５４５５Ｂ号等に提案がなされ
ており、電極上にバンプを形成した半導体素子の能動面
を互に向い合わせ、テープリムドに配置接合する方法が
とられていた。Regarding the high-density packaging structure of semiconductor elements and its manufacturing method, for example, Japanese Patent Laid-Open No. 61-22582
No. 5, Japanese Patent Application Laid-Open No. 41-25455B, etc., the active surfaces of semiconductor elements having bumps formed on electrodes are faced to each other, and a method is adopted in which the active surfaces of semiconductor elements are arranged and bonded to a tape rim.
しかしながら、上記従来技術においては、一方の半導体
素子をギヤングボンディングした後他方の半導体素子を
フェースダウン法で実装する形態か、あるいは、双方の
素子ともフェースダウン法で実装する形態がとられてお
り、前者の形態の場合にはギヤングボンディングとフェ
ースダウン法との２種類の工程が必要であり、工程数の
増加を招く問題があり、また、後者の形態の場合には、
一方の半導体素子を７エースダウン法で実装後、他方の
素子を実装する際に、初めに実装した素子がテープリー
トからの位置ずれあるいははく離を起こしやすく、歩留
りの低下を招くという問題があった。However, in the above-mentioned conventional technology, one semiconductor element is subjected to gigantic bonding and then the other semiconductor element is mounted using a face-down method, or both elements are mounted using a face-down method. In the case of the former form, two types of processes are required: gigantic bonding and face-down method, which causes the problem of an increase in the number of processes, and in the case of the latter form,
After mounting one semiconductor element using the 7 ace down method, when mounting the other element, there was a problem in that the first element mounted was likely to be misaligned or peeled off from the tape reel, resulting in a decrease in yield. .
さらに、上記の方法によって２つの素子を実装した後モ
ールド剤を充填する際に、素子の能動面間の間隙にモー
ルド剤が十分に浸入せず、耐熱性等信頼性の低下を招く
といり問題もあった。Furthermore, when filling the molding agent after mounting two elements using the above method, the molding agent does not sufficiently penetrate into the gap between the active surfaces of the elements, resulting in a decrease in reliability such as heat resistance. There was also.
本発明の目的は、従来技術の有していた上記の課題を解
決して、製造工程数の増加を招くことがなく、高歩留り
での製造が可能で、信頼性の高い半導体素子の実装構造
およびその製造方法を提供することにある。An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a semiconductor element mounting structure that does not increase the number of manufacturing steps, can be manufactured at a high yield, and has high reliability. and its manufacturing method.
上記目的は、ギヤングボンディングにより半導体素子を
接続したテープリードの裏面同士および半導体の能動面
の裏面同士を絶縁性接着剤モー用いて貼９合わせ九構造
とすることによって達成することができる。The above object can be achieved by bonding the back surfaces of tape leads to which semiconductor elements are connected by gigantic bonding and the back surfaces of the active surfaces of the semiconductors using an insulating adhesive to form a structure.
半導体素子をギヤングボンディングしたテープリードの
裏面同士および該半導体素子の能動面の裏面同士を絶縁
性接着剤で貼り合わせることにより、半導体素子のテー
プリードへの接続がギヤングボンディングのみで足り、
フェースダウン法によるボンディングを追加する必要が
なく、また、歩留りのよい実装を得ることができる。By bonding the back sides of the tape leads to which the semiconductor elements are gigang-bonded and the back sides of the active surfaces of the semiconductor elements together with an insulating adhesive, the semiconductor element can be connected to the tape leads by only gigang bonding.
There is no need to add bonding using the face-down method, and it is possible to obtain high-yield mounting.
また、半導体素子の能動面の裏面同士を接着することに
よって、モールディングの際に、モールド剤が素子の能
動面を十分充填することとなる丸め、附湿性の劣化等が
なく、従って、信頼性が向上する。In addition, by bonding the back surfaces of the active surfaces of the semiconductor elements, during molding, there is no rounding or moisture deterioration caused by the molding agent sufficiently filling the active surfaces of the elements, thus improving reliability. improves.
実施例 １
第１図は本発明の半導体素子の実装構造の一実施例の概
略構成を示す断面図で、テープリード１、テープ２、絶
縁性接着剤３、半導体素子４、バンプ５、モールド剤６
、デバイス孔７かもなることを示す。ここで、デバイス
孔７を有するテープ２の材質としてはポリイミドあるい
はガラスエポキン基材を用い、該基材上に銅箔からなる
テープリード１を形成する。また、半導体素子４は、通
常の工程により回路を形成し、電極上に金、はんだ等か
らなるバンプ５を形成したものである。また、テープリ
ード同士および半導体素子同士を貼り合わせる絶縁性接
着剤３としては、ポリエステル系接着剤あるいはエポキ
シ糸接着剤などを用いる。Embodiment 1 FIG. 1 is a cross-sectional view showing a schematic configuration of an embodiment of the semiconductor element mounting structure of the present invention, which includes a tape lead 1, tape 2, insulating adhesive 3, semiconductor element 4, bumps 5, and molding agent. 6
, indicates that the device hole 7 also becomes. Here, a polyimide or glass epoxy base material is used as the material for the tape 2 having the device holes 7, and a tape lead 1 made of copper foil is formed on the base material. Further, the semiconductor element 4 has a circuit formed by a normal process, and bumps 5 made of gold, solder, etc. are formed on the electrodes. Further, as the insulating adhesive 3 for bonding tape leads to each other and semiconductor elements to each other, a polyester adhesive, an epoxy thread adhesive, or the like is used.
実装製造の方法は下記の通りである。すなわち、まず、
半導体素子４上のバンプ５をそれぞれ対応するテープリ
ード１にギヤングボンディングした後、テープ２の裏面
および半導体素子４の能動面の裏面に絶縁性接着剤を塗
布し、同様にして形成した半導体ボンディング済みテー
プと位置合わせを行った後、裏面同士を貼り合わせる。The mounting manufacturing method is as follows. That is, first,
After the bumps 5 on the semiconductor element 4 are gang-bonded to the corresponding tape leads 1, an insulating adhesive is applied to the back surface of the tape 2 and the back surface of the active surface of the semiconductor element 4, and a semiconductor bond is formed in the same manner. After aligning with the finished tape, paste the back sides together.
次いで、デバイス孔７部を含め、半導体素子４全面をモ
ールド剤６を用いて封止する。このようにして、テープ
２のデバイス孔７内に半導体素子を収納することができ
る。Next, the entire surface of the semiconductor element 4 including the device hole 7 is sealed using a molding agent 6. In this way, the semiconductor element can be accommodated within the device hole 7 of the tape 2.
実施例 ２
第２図は本発明の半導体素子の実装構造の他の実施例の
概略構成を示す断面図で、第１図の構成に加えて、テー
プ２上に、さらに、必要とする電子部品８、例えば抵抗
体、コンデンサ等、を実装した構成を示す。Embodiment 2 FIG. 2 is a sectional view showing a schematic configuration of another embodiment of the semiconductor element mounting structure of the present invention. In addition to the configuration shown in FIG. 1, necessary electronic components are further mounted on the tape 2. 8 shows a configuration in which, for example, resistors, capacitors, etc. are mounted.
製造方法は、まず、実施例１の場合と同様にして、半導
体素子４とテープリード１とをギヤングボンディングし
、互いの裏面を貼り合わせた後、必要とする電子部品８
を、局部加熱によるはんだ付けあるいは導電性接着剤等
を用いて、それぞれのテープ２上に実装する。The manufacturing method is as follows: First, the semiconductor element 4 and the tape lead 1 are bonded together in the same manner as in Example 1, and after bonding their back surfaces together, the necessary electronic component 8 is attached.
are mounted on each tape 2 by soldering by local heating or by using a conductive adhesive or the like.
このよりにすることによって、機能の異なる電子部品を
、さらに、テープ２上に混載することができる。This twisting allows electronic components with different functions to be mounted together on the tape 2.
以上述べてきたように１本発明の半導体素子の実装の製
造方法を用い、本発明の実装構造とすることによって、
従来技術の有していた課題を解消して、以下に述べるよ
うな効果を得ることができた。As described above, by using the manufacturing method for semiconductor element packaging of the present invention and creating the mounting structure of the present invention,
The problems of the prior art were solved, and the following effects could be obtained.
すなわち、半導体素子とテープリードとをギヤングボン
ディングのみで接続することができることによって製造
工程数の増加を招くことがなく、また、フェースダウン
法に起因する位置ずれやはく離を生ずることがないので
、歩留り向上を果すことができた。また、半導体素子の
能動面の裏面同士を接着した構造とすることによって、
半導体能動面がモールド剤によって十分に被覆されるた
め、耐湿性等信頼性が保持できる高密度実装を得ること
ができた。That is, since the semiconductor element and the tape lead can be connected only by gigantic bonding, there is no increase in the number of manufacturing steps, and there is no misalignment or peeling caused by the face-down method. We were able to improve yield. In addition, by creating a structure in which the back surfaces of the active surfaces of the semiconductor elements are bonded together,
Since the active surface of the semiconductor is sufficiently covered with the molding agent, high-density packaging that maintains reliability such as moisture resistance can be achieved.
第１図は本発明の半導体素子の実装構造の一実施例の概
略構成を示す断面図、第２図は本発明の半導体素子の実
装構造の他の実施例の概略構成を示す断面図である。FIG. 1 is a sectional view showing a schematic configuration of one embodiment of a semiconductor device mounting structure of the present invention, and FIG. 2 is a sectional view showing a schematic configuration of another embodiment of a semiconductor device mounting structure of the present invention. .
Claims (1)
れぞれ対応するテープリードを接続してなるテープキャ
リヤ実装構造において、テープリードに接続した半導体
ペレットの能動面の裏面同士およびテープリードの裏面
同士を絶縁性接着剤で貼り合わせてなることを特徴とす
る半導体素子の実装構造。 ２、半導体素子ペレットの電極上にバンプを形成し、各
バンプに対応してテープリードを接続する工程を含む半
導体素子のテープキャリヤ実装方法において、半導体ペ
レットをテープリードに接続した後、ほぼ同一のデバイ
ス孔を有するテープリードの裏面同士および半導体ペレ
ットの能動面の裏面同士を絶縁性接着剤で貼合わせるこ
とを特徴とする半導体素子の実装方法。[Claims] 1. In a tape carrier mounting structure in which bumps formed on the electrodes of a semiconductor element pellet are connected to corresponding tape leads, the back sides of the active surfaces of the semiconductor pellets connected to the tape leads and the tape A semiconductor element mounting structure characterized by bonding the back sides of leads together with an insulating adhesive. 2. In a tape carrier mounting method for a semiconductor device, which includes a step of forming bumps on the electrodes of a semiconductor device pellet and connecting tape leads corresponding to each bump, after connecting the semiconductor pellet to the tape leads, approximately the same 1. A method for mounting a semiconductor device, which comprises bonding the back surfaces of tape leads having device holes and the back surfaces of active surfaces of semiconductor pellets together using an insulating adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63132676A JPH01303730A (en) | 1988-06-01 | 1988-06-01 | Mounting structure of semiconductor element and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63132676A JPH01303730A (en) | 1988-06-01 | 1988-06-01 | Mounting structure of semiconductor element and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01303730A true JPH01303730A (en) | 1989-12-07 |
Family
ID=15086900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63132676A Pending JPH01303730A (en) | 1988-06-01 | 1988-06-01 | Mounting structure of semiconductor element and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01303730A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5147815A (en) * | 1990-05-14 | 1992-09-15 | Motorola, Inc. | Method for fabricating a multichip semiconductor device having two interdigitated leadframes |
| US5299094A (en) * | 1992-01-08 | 1994-03-29 | Mitsubishi Denki Kabushiki Kaisha | IC card including multiple substrates bearing electronic components |
| US5313367A (en) * | 1990-06-26 | 1994-05-17 | Seiko Epson Corporation | Semiconductor device having a multilayer interconnection structure |
| EP0473796A4 (en) * | 1990-03-15 | 1994-05-25 | Fujitsu Ltd | Semiconductor device having a plurality of chips |
| US5471369A (en) * | 1993-07-09 | 1995-11-28 | Fujitsu Limited | Semiconductor device having a plurality of semiconductor chips |
| US5491612A (en) * | 1995-02-21 | 1996-02-13 | Fairchild Space And Defense Corporation | Three-dimensional modular assembly of integrated circuits |
| US5701031A (en) * | 1990-04-26 | 1997-12-23 | Hitachi, Ltd. | Sealed stacked arrangement of semiconductor devices |
| US5952725A (en) * | 1996-02-20 | 1999-09-14 | Micron Technology, Inc. | Stacked semiconductor devices |
| US6407456B1 (en) | 1996-02-20 | 2002-06-18 | Micron Technology, Inc. | Multi-chip device utilizing a flip chip and wire bond assembly |
| US6784023B2 (en) | 1996-05-20 | 2004-08-31 | Micron Technology, Inc. | Method of fabrication of stacked semiconductor devices |
| US7109059B2 (en) | 1996-11-20 | 2006-09-19 | Micron Technology, Inc. | Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
-
1988
- 1988-06-01 JP JP63132676A patent/JPH01303730A/en active Pending
Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0473796A4 (en) * | 1990-03-15 | 1994-05-25 | Fujitsu Ltd | Semiconductor device having a plurality of chips |
| USRE37539E1 (en) * | 1990-04-26 | 2002-02-05 | Hitachi, Ltd. | Sealed stacked arrangement of semiconductor devices |
| US5701031A (en) * | 1990-04-26 | 1997-12-23 | Hitachi, Ltd. | Sealed stacked arrangement of semiconductor devices |
| US5147815A (en) * | 1990-05-14 | 1992-09-15 | Motorola, Inc. | Method for fabricating a multichip semiconductor device having two interdigitated leadframes |
| US5313367A (en) * | 1990-06-26 | 1994-05-17 | Seiko Epson Corporation | Semiconductor device having a multilayer interconnection structure |
| US5299094A (en) * | 1992-01-08 | 1994-03-29 | Mitsubishi Denki Kabushiki Kaisha | IC card including multiple substrates bearing electronic components |
| US5579208A (en) * | 1993-07-09 | 1996-11-26 | Fujitsu Limited | Semiconductor device having a plurality of semiconductor chips |
| US5724233A (en) * | 1993-07-09 | 1998-03-03 | Fujitsu Limited | Semiconductor device having first and second semiconductor chips with a gap therebetween, a die stage in the gap and associated lead frames disposed in a package, the lead frames providing electrical connections from the chips to an exterior of the packag |
| US5471369A (en) * | 1993-07-09 | 1995-11-28 | Fujitsu Limited | Semiconductor device having a plurality of semiconductor chips |
| US5491612A (en) * | 1995-02-21 | 1996-02-13 | Fairchild Space And Defense Corporation | Three-dimensional modular assembly of integrated circuits |
| US5952725A (en) * | 1996-02-20 | 1999-09-14 | Micron Technology, Inc. | Stacked semiconductor devices |
| US6165815A (en) * | 1996-02-20 | 2000-12-26 | Micron Technology, Inc. | Method of fabrication of stacked semiconductor devices |
| US6337227B1 (en) | 1996-02-20 | 2002-01-08 | Micron Technology, Inc. | Method of fabrication of stacked semiconductor devices |
| US6407456B1 (en) | 1996-02-20 | 2002-06-18 | Micron Technology, Inc. | Multi-chip device utilizing a flip chip and wire bond assembly |
| US6989285B2 (en) | 1996-05-20 | 2006-01-24 | Micron Technology, Inc. | Method of fabrication of stacked semiconductor devices |
| US6784023B2 (en) | 1996-05-20 | 2004-08-31 | Micron Technology, Inc. | Method of fabrication of stacked semiconductor devices |
| US7371612B2 (en) | 1996-05-20 | 2008-05-13 | Micron Technology, Inc. | Method of fabrication of stacked semiconductor devices |
| US7109059B2 (en) | 1996-11-20 | 2006-09-19 | Micron Technology, Inc. | Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
| US7282792B2 (en) | 1996-11-20 | 2007-10-16 | Micron Technology, Inc. | Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
| US7402902B2 (en) | 1996-11-20 | 2008-07-22 | Micron Technology, Inc. | Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
| US7411286B2 (en) | 1996-11-20 | 2008-08-12 | Micron Technology, Inc. | Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
| US7423338B2 (en) | 1996-11-20 | 2008-09-09 | Micron Technology, Inc. | Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
| US7423339B2 (en) | 1996-11-20 | 2008-09-09 | Mircon Technology, Inc. | Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
| US7776652B2 (en) | 1996-11-20 | 2010-08-17 | Micron Technology, Inc. | Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
| US7812436B2 (en) | 1996-11-20 | 2010-10-12 | Micron Technology, Inc. | Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
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