JPH01298763A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To restrain kink phenomena, strengthen resistance to noise and enable maintenance of storage by adding a capacitive element into a storage element. CONSTITUTION:A capacitive element is constituted of a P-type MOSFET's channel 2, an insulating film 14 and a grounding wiring 9. When voltage is applied to terminals D and G with a terminal S earthed and a terminal B floated, the drain voltage current characteristics show kink phenomena in which currents increase abnormally in a saturation region. By giving potential to the terminal B, the capacitive element functions and draws hot carriers generated in the channel by impact ionization toward the terminal B and reduces the effect on the drain currents flowing on the channel surface on the side of and gate electrode G and restrains the kink phenomena.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to semiconductor memory circuit devices, particularly SOI (Sil 1conon In
MO having an element of 5ulator) structure in the memory element
The present invention relates to a 5-type static RAM (hereinafter abbreviated as SRAM).

[Prior Art] FIG. 3a is a circuit diagram of a memory element of a MOS type SRAM. In normal CMO5 (complementary MO9) type SRAM,
T1 and T2 are P-type MO9 field effect transistors (hereinafter referred to as FETs), and T3 and 'UT4 are N-type MOSFETs. Since the CMOS inverters are connected power and output to each other, storage operation with bistable properties is possible.

Here, T5 and T6 are gate elements that operate to connect the storage element and an external circuit, and are usually N-type MO3FE.
Consists of T. Further, V is connected to a power supply potential, and G is connected to a ground potential. Figure 3b shows the P-type MO5F of T1 in Figure 3a.
It shows a cross-sectional structure of a first inverter composed of an N-type MOSFET of ET and T3. Highly integrated SRAM
Then, in order to reduce the area occupied by the element, the P-type M inside the element is
O5FET Sol (Silicon on 1
nsulator). 30 in FIG. 3b is a P-type silicon substrate, 33 is a gate electrode, 31A,
31B is an N-type diffusion layer with an impurity concentration of 102"-10" cm-3, 34 is a gate insulating film, and 30, 33,
34.31A, 31B, T3ON type M in Figure 3a
Configure OSFET.

Here, 31A is connected to ground potential G in FIG. 3a. On the other hand, in FIG. 3b, 32 is a silicon thin film, 32A, 3
2B is 1019~ formed in the silicon thin film of 32
P-type diffusion layer with impurity concentration of 10” cm−3, 35
The gate insulating film is 33.35.32A.

32B constitutes the P-type MOSFET of T1 in FIG. 3a as an SoI. Here, 32A is connected to the power supply potential V in FIG. 3a. In Figure 3b, 36 is P of T2 in Figure 3a.
This is the gate electrode of the second inverter composed of a type MO5FET and a T4 N type MOSFET, and
Connected to B.

37 is an insulating film.

[Problems to be Solved by the Invention] In the storage element of the MOS type SRAM having the conventional SOI element described above, the Sol channel (33 in FIG. 3b)
) is in a floating state where the potential is not fixed. Therefore, depending on the potential state of the drain and gate, impact ionization occurs and a large amount of hot carriers are generated, causing a king phenomenon peculiar to SOI devices that causes abnormal train current to flow, and causing deterioration of the device.

In addition, if polycrystalline silicon or the like is used as the silicon thin film constituting the SOI, and the current driving ability of the P-type MO5FET is inferior to that of single-crystal silicon, the inverter outputting a high potential will be affected by the accumulation of noise such as alpha rays. This had the disadvantage that the stored charge was washed away and the output was reversed, making the memory retention operation impossible.

[Differences between the invention and the prior art] The present invention adds a capacitive element to the storage element of the MOS type SRAM having the conventional SOI structure as described above, thereby eliminating the kink phenomenon unique to the Sol structure. The difference is that it suppresses noise, strengthens resistance to noise, and enables memory retention.

[Means for Solving the Problems] The semiconductor memory device of the present invention includes first and second MOSFETs of a first conductivity type formed on the main surface of a semiconductor substrate, and a second conductivity type MOSFET formed in a silicon thin film. 3rd and 4th M of mold
The third and fourth MOSFETs are respectively arranged on top of the first and second MOSFETs, and the gate electrodes of the first and third MOSFETs are formed in common with the first conductive layer. and the second and fourth MOS
A gate electrode of the FET is formed in common with the second conductive layer,
The sources of the first and second MOSFETs are connected to a first power supply, and the sources of the third and fourth MOSFETs are connected to a second power supply.
a first region that is connected to a power supply of the first conductive layer and commonly connects the trains of the first and third MOSFETs and the second conductive layer; a second region connecting the layers in common, and having first and second capacitive elements, the first capacitive element being connected to the third capacitive element;
and the second capacitive element is provided between the channel region of the fourth MOSFET and the first power source.

Alternatively, the first and second capacitive elements are arranged such that the first capacitive element is between the third MOSFET train and the first power supply, and the second capacitive element is between the third MOSFET train and the first power supply. 4 MOS
A feature is provided between the train of FETs and the first power source.

Further, third and fourth capacitive elements are added, the first capacitive element being between the channel region of the third MOSFET and the first power source, and the second capacitive element being between the third MOSFET channel region and the first power source. MO of 4
The third capacitive element is between the channel region of the SFET and the first power supply, and the fourth capacitive element is between the drain of the third MOSFET and the first power supply. Fourth
It has the feature that it is provided between the drain of the MOSFET and the first power supply.

[Example code] Next, the present invention will be explained through examples.

1a to 1b show a first embodiment of the present invention, in which FIG. 1a is a plan view and FIG. 1b is a sectional view taken along line xx' in FIG. 1a. Here, FIG. 1a is the MO5 shown in FIG. 3a.
This figure shows the application of the present invention to the main components I-T4 of a circuit diagram of a type SRAM, and T5 and T6, which are called transfer gates, are omitted. Also the first
Figure b is a sectional view of an inverter composed of TI and T3.

In FIG. 1, IA and IB are first N-type MOS
The source and drain regions of the FET are formed on the main surface of the semiconductor substrate. 2A.

2B is the source of the first P-type MO9FET.

The drain region, 2 is the channel region of the P-type MOSFET T1, and 2.2A and 2B are formed in the same silicon thin film. 3 is a first gate electrode common to the first N-type MOSFET and the first (7) P-type MOSFET (7). 4A and 4B are each second N-type MOS
The source and train regions of the FET are formed on the main surface of the semiconductor substrate. 5A and 5B are second P-type MO5FETs
source and drain regions, 5 is the second P-type MO3FET
5.5A and 5B are the channel regions of 1st degree P
It is formed in the same silicon thin film separate from the type MOSFET. 6 is a second N-type MOSFET and a second P-type M
This is a common gate electrode for OSFETs.

7 is a connection region between the N-type region on the semiconductor substrate and the gate electrode;
8 is a connection region between the gate electrode and the silicon thin film. 9 is an N-type MOS FET (1)'/-(IA.

4A) is connected in 10 regions by wiring made of a conductive material that provides a ground potential, and extends above the channel region 2.5.

In FIG. 1b, 11 represents a semiconductor substrate, 12 represents a gate insulating film of an N-type MOSFET, and 13 represents a P-type MOSFET.
This is the gate insulating film. 14 is an insulating film; 2. 1
4. 9 forms a parallel plate type capacitor.

First, we will discuss the characteristics of SOI elements in Figures 2a to 2.
This will be explained with reference to figure c. Figure 2a shows a typical So 1
MO5FET (7) cross-sectional view, 20 is an insulating substrate, 2
1 is the channel area of So 1MO3FET, 21A,
21B is the source and drain region of the SOIMOSFET. 22 is a gate insulating film of the MOSFET, 23 is a gate electrode, 24 is an electrode provided on the back surface of the insulating substrate,
Reference numeral 25 denotes electrodes connected to the source and drain regions, and each electrode is connected to a terminal as shown in the figure. 2nd b
The figure shows the equivalent circuit of FIG. 2a, which includes a MOSFET T21 and a capacitive element C21.

In the circuit shown in Figure 2b, when terminal S is grounded, terminal B is left floating, and a voltage is applied to G, the drain voltage-current characteristic will be such that the current will rise in the saturation region as shown by the broken line a in Figure 2c. Shows an abnormally increasing kink phenomenon.

On the other hand, the drain voltage-current characteristics of a MOSFET formed on a semiconductor substrate are shown by the solid line C in FIG.

Next, when a potential, for example, the same ground potential as the terminal S is applied to the terminal B, the king phenomenon is reduced in the drain voltage current characteristics as shown by the dashed line in FIG.

This is because when a potential is applied to terminal B, the capacitive element works and attracts hot carriers generated by impact ionization in the channel to the terminal B side, which has an effect on the drain current flowing through the channel surface on the gate electrode G side. This is to reduce the risk.

In this way, the kink phenomenon can be suppressed by applying a potential through the capacitive element without directly applying a potential to the channel region of the SOIMO9FET.

In the embodiment shown in FIG. 1b, 2. 14. 2nd by 9
A capacitive element corresponding to C21 in figure b is formed, and 2
．． 2A, 2B, 3. The kink phenomenon of the P-type MO5FET formed by 13 can be suppressed and the deterioration of the element can be prevented. Also, 5. 5A, 5B, 6゜13
A capacitive element also exists on the P-type MOSFET formed by. An equivalent circuit of this embodiment is shown in FIG. 6a. T61 in the diagram
．． T62 is a P-type MOSFET, T63. Ta2 is N type M
OSFET, C61, and C62 are capacitive elements.

In the embodiment shown in FIG. 1a described above, the conventional insulating film and wiring are used to realize the capacitive element, and no special manufacturing process is required for realizing the capacitive element.

Fig. 4 is a plan view showing the second embodiment of the present invention;
In the figure, 41 to 49 correspond to 1 to 9 in FIG. 1a, and 40 in FIG. 4 corresponds to 10 in FIG. 1a, respectively. The feature of FIG. 4 is that the wiring 49 is the drain 42B, 45 of the P-type MO5FET.
42B and 49.45B and 4
A capacitive element is present between each of 9 and 9.

As a result, the output capacitance of each inverter in the storage element increases and the stored charge increases, so the P-type MOS
Even if polycrystalline silicon is used for the silicon thin film that forms the FET, and the current drive capacity of the P-type MO5FET is small, the output level can be maintained even when noise from alpha rays etc. enters the inverter that outputs a high potential. can do.

An equivalent circuit of this example is shown in FIG. 6b. T65, T in the figure
66 is P type MOSFET, Te3, Te3 are N type FET
, C63, and C64 are capacitive elements.

In this embodiment, like the previous embodiment, it can be realized without using any special manufacturing process.

Figure 5 is a plan view showing a third embodiment of the present invention. Fifth
In the figure, 51 to 59 correspond to 1 to 9 in Figure 1a and 5 in Figure 5.
0 corresponds to 10 in FIG. 1a, respectively. The feature of FIG. 5 is that the width of the wiring 59 is widened, 52.52B, 55.55B.
The reason is that it covers B at the same time. As a result, 52.
52B, 55. 55B will each have a total of four capacitive elements in front of 59, realizing a composite of the embodiments of FIGS. 1a and 4. An equivalent circuit of this embodiment is shown in FIG. 6c. T69 in the figure. T70 is P type M
O5FET, T71. T72 is N-type MOSFET, C6
5 to C68 are capacitive elements.

This embodiment also does not require any special manufacturing process like the two embodiments described above. Further, the first to third embodiments described above have the feature that each embodiment can be realized by simply changing the arrangement of the ground wiring.

Note that the transfer gate is omitted in FIGS. 6a to 6c. Further, in each embodiment, the capacitive elements are connected to the ground potential, but they may be connected to the power supply potential.

[Effects of the Invention] As explained above, the present invention provides a channel or drain of a P-type MOSFET formed of SOT in a memory element;
Alternatively, by providing a capacitive element between both of them and the ground wiring, it is possible to prevent deterioration by reducing the King phenomenon, strengthen memory retention against noise, and achieve both.

[Brief explanation of the drawing]

1a to 1b show a first embodiment of the present invention, in which FIG. 1a is a plan view and FIG. 1b is a sectional view taken along line XX' in FIG. 1a. 2a to 2c show a SOIMOSFET, FIG. 2a is a sectional view showing its structure, FIG. 2b is an equivalent circuit diagram, and FIG. 2c is a graph showing drain voltage/current characteristics. Figure 3a is a circuit diagram of a storage element of a MOS type SRAM;
Figure b is a sectional view showing a conventional example of the structure of an inverter using TI and T3 in Figure 3a. FIG. 4 is a plan view of a second embodiment of the invention. FIG. 5 is a plan view of a third embodiment of the present invention. Chapter 6a
6C to 6C are equivalent circuit diagrams showing the first to third embodiments, respectively. TI, T2. Ta2゜Te3. Ta2. T66°Te3. T2O---P type MO5FET, T4~T
6. Te3. Te3. Te3゜Te3. T71. T72
---N type MOSFET, C21, C61~C68...
・Capacitive element, T21---SOTMO3
FET. IA, 4A, 31A. 41A, 44A. 51A, 54A---N type MOSFET (7) source,
IB, 4B, 31B. 41B, 44B. 51B, 54B---N-type MOSFET (7) drain, 2) 5. 32. 42゜45, δ2,55...P-type MOSFET channels, 2A, 5A, 32A. 42A, 4!5A. 52A, 55A...P-type MO5FET source, 2B, 5B, 32B. 42B, 45B. 52B, 55B...Drain of P-type MO3FET, 3, 6. 23. 33°36, 43. 46°53.56...Gate electrode? ,47.5
7... Connection region between gate electrode and N-type region, 8.48.58... Connection region between gate electrode and silicon thin film, 9.49.59... Ground wiring, 10. 40.
δ0... Connection area between N-type region and ground wiring, 11.30... Semiconductor substrate, 12) 13
, 22° 34.35... Gate insulating film, 14.
37...Insulating film, 20-------So IMOSFET (7) Insulating substrate, 21------SOIMOSFET (7) Channel, 21A◆...So IMOSFET source, 2
1 B ・----So IMOSFET (DF drain 24... Electrode of insulated substrate, 25... Electrode, D, G, S, B... Terminal. Agent Patent attorney Kuwai Kiyoshi-Subue 2C Figure 3a Figure V Figure 4 42B: P-type MO3FET drain 15 figure

Claims (3)

[Claims] (1) First and second field effect transistors of the first conductivity type formed on the main surface of the semiconductor substrate, and third and fourth field effect transistors of the second conductivity type formed in the silicon thin film. The third and fourth field effect transistors are disposed above the first and second field effect transistors, respectively, and gate electrodes of the first and third field effect transistors are formed of a first conductive layer. the gate electrodes of the second and fourth field effect transistors are commonly formed in a second conductive layer, and the sources of the first and second field effect transistors are connected to a first power supply; The sources of the third and fourth field effect transistors are
a first region that is connected to a power source and commonly connects the drains of the first and third field effect transistors and the second conductive layer; and the drains of the second and fourth field effect transistors; and a second region commonly connecting the first conductive layer, the semiconductor memory device having first and second capacitive elements, the first capacitive element being connected to the third field effect. between the channel region of the transistor and the first or second power supply, the second capacitive element is connected to the channel region of the fourth field effect transistor;
A semiconductor memory device, characterized in that it is provided between the first or second power source. (2) In the semiconductor memory device according to claim 1, the first and second capacitive elements are connected to the drain of the third field effect transistor and the first capacitive element is connected to the drain of the third field effect transistor. Alternatively, a semiconductor memory device provided between the drain of the fourth field effect transistor and the first or second power source. (3) The semiconductor memory device according to claim 1 further includes third and fourth capacitive elements, and the third capacitive element connects the drain of the third field effect transistor and the third capacitive element. The fourth capacitive element is connected between the drain of the fourth field effect transistor and the first or second power source.
Or a semiconductor memory device provided between a second power source and a second power source.