JPH01296743A - Data communication system - Google Patents

Abstract

PURPOSE:To eliminate complicated changeover switch operation by using a transfer speed discrimination data transferred from the host so as to allow a terminal side to discriminate the transfer speed automatically, synchronizing the synchronization of data transfer speed between the host side and the terminal side and transiting the transfer processing of a communication data. CONSTITUTION:A discrimination means at the terminal side discriminates the transfer speed automatically by a transfer speed discrimination data transferred by the transfer means from the host side, the data transfer speed between the host side and the terminal side is synchronized and the mode is transited to the transfer processing of the transfer data. Thus, the limit of the combination due to the difference the transfer speed is eliminated and complicated switch operation is eliminated. Moreover, a data transfer speed discrimination data is transferred at the start of transaction transfer to switch the reception transfer speed clock at the terminal side and the reception of data is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data communication system between a host and a terminal, and more particularly to a data communication system that performs data transfer rate synchronization.

[Prior Art] Conventionally, as a data transfer method for data transfer from a host to a terminal, there is a start-stop synchronous method in which a data transfer speed is determined in advance between the host and the terminal, and data communication is performed at this determined transfer speed. There is a communication method called

In this method, when the host sends a start bit,
The terminal (peripheral device) side recognizes the start of data transfer, receives data sent following the start bit according to a predetermined transfer rate, and continues this process until it detects a stop bit from the host. This is a method of receiving data. In the case of this start-stop synchronization method, complicated data transfer procedures are not required and it can be easily performed, so it is currently widely used in the world of communication between personal computers.
This is a general-purpose communication procedure.

Further, even if other synchronization methods were used, the data transfer rate had to be fixed and determined in advance, resulting in a lack of versatility.

[Problems to be Solved by the Invention] However, there are various types of data transfer speeds, such as 4800 BPS and 9600 BPS.

There are various transfer speeds such as 19200 BPS.

This difference in types has the disadvantage that combinations of host and terminal sides are limited, making it impossible to select the optimal speed for each case.

It is also conceivable to have a configuration in which each device has a changeover switch so that the transfer speeds are the same, but this is troublesome and troublesome.

[Means for Solving the Problems] The present invention has been made for the purpose of solving the above-mentioned problems, and includes the following configuration as one means for solving the above-mentioned problems.

That is, as shown in the functional block diagram of FIG. 1, the terminal is equipped with a determining means for determining a data transfer rate to the host, and a transfer means for transmitting transfer rate determination data at the transfer rate determined by the determining means. a receiving means for receiving transfer rate determination data from a host; a determining means for determining a data transfer rate from the transfer rate determining data received by the receiving means; and a switching means for switching a reception clock according to the determination result of the determining means. Equipped with.

[Operation] In the above configuration, the terminal side automatically determines the transfer speed based on the transfer speed determination data transferred from the host side, synchronizes the data transfer speed between the host side and the terminal side, and then transfers the communication data. By shifting the processing, restrictions on combinations due to differences in transfer speeds are removed, and complicated switch operations are eliminated.

[Embodiment] An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment according to the present invention. In the figure, 10 is a host such as a personal computer, word processor, etc., which sends necessary data to the terminal 50 side. 50 is a terminal, and between the host IO and the terminal 50 there are two sets of signal lines, namely data signal lines (RXD
) 2i and a control signal line (DR) 22 to exchange necessary data.
The power supply that drives the is all connected to the power line 23 from the host 10 side.
Powered by.

In the host 10, numeral 11 is an MPU that controls the entire embodiment according to a control program to be described later, which is built into a ROM 12, 12 is a ROM that stores the above-mentioned program and parameters used in the host, and 13 is a ROM for transmitting/receiving data and processing. A memory stores data, etc.; 14 is an interface circuit for interfacing with a terminal; and 15 is a power supply section.

In the terminal 50, 51 is a CPU which controls the entire embodiment according to a control program which will be described later and which is built into a ROM 52, 52 is a ROM which stores the above-mentioned program and other parameters used in the terminal, and 53 is a CPU for transmitting/receiving data and processing. A memory 54 stores data and the like, and an interface circuit 54 controls the interface with the host.

FIG. 3 is a diagram showing the state of transfer of one frame of data on the line used in this embodiment having the above configuration.
RXD21 when transferring data “11010000”
It is a figure showing the above state.

As shown in FIG. 3, one frame of data consists of 10 bits including a start bit 61 and a stop bit 62, and is sent out in order from the least significant bit.

An outline of the basic data communication processing of this embodiment will be explained below.

On the terminal side, the own device is in operation and host 1
When data communication (data reception) from 0 is possible, the data ready signal (DR) 22 is turned on. Therefore, the basic data transfer procedure is such that the host side checks the DR signal 22 from the terminal 50 every time one frame is transferred, and then executes the data transfer process.

FIG. 4 is a diagram showing the structure of a data transfer frame for one transaction used in this embodiment, and shows the format of transfer data.

As shown in the figure, the data length 65 to be transferred from now on is transferred at the beginning of one transaction, and the data 66 is transferred thereafter.

When the CPU 51 in the terminal receives the data transfer frame, it reads the data length 65, receives the amount of data specified by the data length 65 that is sent subsequently, and ends the data transfer process. do.

Next, the synchronization process of this embodiment having the above configuration will be explained as follows.
This will be explained with reference to the flowchart shown in the figure.

FIG. 5 is a flowchart of the synchronization processing program stored in the ROM 52 in the terminal, and the host side also executes the synchronization processing program in the ROM 12.
The host side first determines the data transfer rate with the terminal 50. This speed can also be specified by the operator.
It may be controlled by the program to be different depending on the nature of the transmitted data. In this example, 19200BP
This covers both transfer speeds of S and 9600 BPS.

Discrimination data, which will be described later, is then sent to the terminal at the determined transfer rate.

On the terminal side, the transmission rate is detected through processing to be described later, and the following data is received at a reception timing synchronized with the determined data transfer rate.

That is, first, in step S1, the terminal 50 sets the receiving clock of the interface circuit 54 to 192008 PS. Then, in the following step S2, the DR signal 22 is turned on (active), and in step S3, data transfer from the host is waited for. If data is transferred, step S4
Then, it is checked whether the received frame data is "#EF" or not. If it is "#EF", the transfer rate from the host is determined to be 19200 BPS, and the process jumps to step S8, and the process proceeds to receive the transaction shown in FIG.

On the other hand, if it is not "#EF", the process proceeds to step S5, and it is checked whether the received frame data is "#FE". ”#
If it is not "FE", it is determined that there is a reception error and the process returns to step S2.

If it is “#FE” in step S5, step S6
Wait for the next received data, and the next received data will also be “#”.
The next received data is also “#F”.
E", the transfer speed from the host is 960
Since it is 0BPS, the process proceeds to step S7, and the reception clock of the interface circuit 54 is switched to 96008PS, and since the reception clock synchronization process is now complete, the process proceeds to step S8.

If the next received data is not "#FE" in step S6, it is determined that there is a reception error and the process returns to step S2.

In step S8, the required amount of transactions is received for each data transfer frame of one transaction shown in FIG. Then, in step S9, a lamp or the like in the terminal is turned on to notify completion of reception, and the series of processing is completed.

A timing chart of the above-mentioned transfer rate determination process is shown in FIG.

FIG. 7 is a diagram showing how the receiving side, which is set to 19200 BPS, receives and receives data when the transmitting side transfers data "#EF" at 9600 BPS.

As shown in the figure, in this case, "#FE" is received twice.

In this way, prior to actual data transmission, the optimal transmission pattern for determining each predetermined transfer rate is sent to the terminal side, and the terminal side receives this pattern and determines what kind of data to interpret. , you can know the data transfer speed.

This transfer pattern is not limited to the pattern in the embodiment, but may be any pattern that allows the transfer speed to be determined. Further, the transfer speed is not limited to the above two types, but can be any speed, and there are no restrictions on the type. As long as it can be determined based on the transfer pattern, various applications are possible.

As explained above, according to this embodiment, by transmitting the data transfer rate determination data before transferring transaction information, the receiving side determines the data transfer rate and switches the receiving clock, so that the host side and terminal side can communicate with each other. To provide a device that eliminates restrictions on transfer rate selection and eliminates complicated switch operations.

Also, since transfer rate determination data is always sent before a transaction, in the case of a terminal that is powered by the host, the host side will detect that the connection with the terminal side is interrupted. Troublesome controls are also unnecessary.

In this way, the terminal side automatically determines the transfer speed based on the transfer speed determination data transferred from the host side, synchronizes the data transfer speeds between the host side and the terminal side, and then transfers the communication data. This eliminates restrictions on combinations due to differences in transfer speeds and eliminates complicated switch operations.

Furthermore, by transferring data transfer rate determination data at the start of transaction transfer, it is possible to switch the reception transfer rate clock on the terminal side and receive data.

[Effects of the Invention] As explained above, according to the present invention, the terminal side automatically determines the transfer speed based on the transfer speed determination data transferred from the host side, and the data transfer speed between the host side and the terminal side is adjusted. By shifting communication data transfer processing after synchronization, restrictions on combinations due to differences in transfer speeds can be removed, and complicated switch operations can be eliminated.

[Brief explanation of the drawing]

Figure 1 is a functional block diagram of the present invention. Figure 2 is a block diagram of an embodiment of the present invention. Figure 3 is a timing chart for transferring one frame of data in this embodiment. Figure 4 is a diagram of this embodiment. FIG. 5 is a communication control flowchart on the terminal side of this embodiment, and FIG. 6 is a diagram for explaining the data transfer rate determination process of this embodiment. In the figure, 10...Host, 11...MPU, 12゜5
2...ROM, 13.53...Memory, 14.54
...interface circuit, 15...power supply section, 21.
...Data signal line RXD, 22...Control signal line DR1
23...Power line.

Claims (1)

[Claims] 1) In the data communication method between the host and the terminal, a determining means for determining the data transfer rate for the host;
a transfer means for transmitting the discrimination data at the transfer rate determined by the determining means; receiving means for receiving the discrimination data from the host at the terminal; and a data transfer rate determined by the discrimination data received by the reception means. The apparatus includes a discriminating means for discriminating, and a data receiving means for receiving data at a timing according to the discriminating result of the discriminating means, and synchronizes the data transfer speed between the host side and the terminal side using the discriminating data prior to data communication. A data communication method characterized by: