JPH01296496A - Control system for non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To attain erasing for the unit of a page by executing the erasing of data with impressing a high voltage to a source line and grounding a word line and executing the writing of the data with impressing the high voltage to a bit line and the word line and grounding the source line. CONSTITUTION:For the erasing of the data, a high voltage Vpp level is impressed to a source line 10a of the selected and word lines 11a and 11b are caused to be a grounding voltage 0V level. Then, electronic accumulated in a floating gate 6 is extracted and the selected page is erased. For the writing of the data, the word line 11a and a bit line 9b of a selected memory transistor 21c are impressed to the high voltage Vpp level and a source line 10b is caused to be the grounding voltage 0V level. Then, the writing is executed with executing the avalanche-injection of the electron to the gate 6. Thus, the erasing can be executed for the unit of the page and a reloading time can be shortened.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to the control of a non-volatile semiconductor memory device that can be electrically erased and written, for example, the control of a non-volatile semiconductor memory device that can be rewritten in page units. It is related to.

[Prior Art] A conventional nonvolatile semiconductor memory device will be described with reference to FIGS. 3 and 4. Figure 3 shows r1987 l5SCCDI
GEST OF TEC++NICAL PAPER3
Conventional batch erase type E having a memory cell consisting of one memory 1 to transistor disclosed in pp7 Row 77 J
E P ROM's simple circuit, memory transistor's goo 1~ line.

It is a block diagram in which voltage values applied to the drain line and the lines 1 to 2 correspond to each other. In the figure, 1a and 1b are memory transistors, and the memo sword 1 to transistor 1
As shown in FIG. 4, the semiconductor substrate 2 has a drain diffusion region 3, which is a drain, and a source diffusion region 4, which is a source, which are formed at intervals on the surface of a semiconductor substrate 2. 2 is covered with a thin oxide film 5 of about 200 layers, and a floating gate 1-6 is provided on this oxide film 5 so as to be located above the end of the drain diffusion region 3.

Further, the floating gate 6 and the oxide film 5 are covered with an oxide film 7, and a control layer 7 is formed on the oxide film 7 so as to be located between the source diffusion region 4 and the floating gate 6. -8 is provided. - The floatation cage 6 is surrounded by oxide films 5 and 7 at a temperature of 4°C.
It is in an electrically floating state.

Furthermore, the controller I-8 has a stepped structure that is lower in the portion where the floating gate 6 is not present. In this memory transistor 1, a bit line 9 is connected to the drain diffusion region 3, a source line]-◯ is connected to the source diffusion region 4, and a word line 11 is connected to the control gate 8.

” 2nd Memo January ~ The run transistors 1a to 1d are arranged in a lattice pattern in a nonvolatile semiconductor memory device, and each drain diffusion region 3 corresponding to the arrangement of the pins 1 to 9a,
9b, each source diffusion region 4 is connected to a source line 10a, 10b.
, each controller 1 to roll gate 8 is connected to the word line 11a, ll
connected to b.

Next, the operation will be explained. First, erasing data, that is, writing "1" into all memory transistors 1a to 1b, requires all bit lines 9a and 9b to be connected to a high voltage V.
All the word lines 1.1a and llb are set to the ground voltage O2 level to Pp level, and a high electric field is generated between the floating lines 1-6 and the rain diffusion region 3 on the memory transistor. Therefore, the electrons accumulated in the floating gate 6 are drawn out to the drain diffusion region 3 through the thin oxide film 5 by a tunneling phenomenon.

As a result, the floating gate 6 becomes deficient in electrons, and the threshold voltage of the memory transistor 1 as seen from the controller gate 1-8 becomes low (becomes a negative level).

Assume that this state is logically stored as 11111.

When erasing of the data is completed, writing begins.

This writing is performed in the same manner as the program operation for EPROM, and the memory jl l-transistors 1a to 1 are
The selected memory transistor 1 will be described as writing to the memory l-run raster 1c at d.
The selected bit line 9b corresponding to C is set to the VPP level. The unselected bins 1 to 9a are set to the OV level, the selected word line 11a is set to the VPP level, and the unselected word line 11b is set to the Ov level. Therefore, a high electric field is generated in the drain diffusion region 3 of the selected memory 1 to transistor 1c and the controller 1 to roll gate 8. At this time, hot electrons are generated near the drain diffusion region 3, and these hot electrons are accelerated by the high electric field applied to the controller 1 roll gate 1-8, and the floating gate 6
injected into. As a result, electrons are accumulated in the floating elements 1 and 6, so that the threshold voltage of the memory transistor 1c as seen from the control gate 8 increases (
positive level).

11011 is logically written into the memory transistor 1c selected in this manner. Note that the source lines 10a and 10b are always set at the ground voltage Ov level.

As described above, EEPROMs with one memory transistor and one memory cell configuration do not require ultraviolet erasure like EPROMs and can be electrically erased, and can be erased electrically compared to ordinary EEPRs.
Unlike OM, it is not necessary to configure one memory cell with two or more transistors, and since one memory cell can be configured with one memory 1 to transistor, the area of the semiconductor chip can be reduced.

[Problems to be Solved by the Invention] Since the conventional non-volatile semiconductor memory device is configured as described above, the entire device is erased at once, and pages that do not need to be rewritten are also erased and have to be written again. , there were problems such as it took a long time to rewrite.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a control method for a nonvolatile semiconductor memory device that can erase page by page.

[Means for Solving the Problems] A control method for a nonvolatile semiconductor memory device according to the present invention includes:
The drain of each memory transistor is connected to a bit line, the source is connected to a source line, and the control gate is connected to a word line, and data is erased by applying a high voltage to the source line and grounding the word line. Writing is performed by applying a high voltage to the -1- line and the word line, and by grounding the source line.

[Function] The control method of the nonvolatile semiconductor memory device according to the present invention applies high voltage to the source line of the page to be erased and grounds the word line, thereby erasing the word line in units of pages. The selected memory transistor is written by applying a high voltage to the bit line and word line of the memory transistor and grounding the source line.

[Embodiment] A nonvolatile semiconductor memory device which is an embodiment of the present invention will be described below with reference to FIG. In addition, Figures 3 and 4
Components that are the same as those in the figures are designated by the same reference numerals, and the description thereof will be omitted. In the figure, 21a to 21d are memory transistors, and 21a to 21d are memory transistors 2 and 21d of the drain diffusion region 3.
8 is located, and the floating gate 6 and the above-mentioned controllers 1 to 8 are located at -1- of the source diffusion region 4.

Next, the operation will be explained. To erase data, apply a high voltage VPP level to the source line 10a of the selected page, set the word lines 11a and llb to the ground voltage O level, and extract the electrons accumulated in the floating gate 6. The selected page will be deleted.

At this time, the pins 1 to 9a and 9b may be at O■ level or may be floating. For writing, the word line 11a and pin 1-line 9b of the selected memory transistor 21c are
This is carried out by avalanche injection of electrons into the floating gate 6 by applying the .rho.p level and setting the source line 10b to the O2 level.

In this embodiment, it is assumed that erasing can be performed page by page, but as shown in FIG. It may also be possible to share the information and erase every two pages.

Further, in this embodiment, the non-volatile semiconductor memory device is composed of four memory transistors 21a to 21d.
Although the case of 2 pages is shown, the above memory transistor 2
1 may be any number or pages of nonvolatile semiconductor memory devices.

[Effects of the Invention] As described above, according to the present invention, the control method for a nonvolatile semiconductor memory device is such that data is erased by applying a high voltage to the source line and grounding the word line, and data is written by applying a high voltage to the source line and grounding the word line. This is done by applying high voltage to the bit lines and word lines and grounding the source line, so it is done on a page-by-page basis (
This makes it possible to erase pages that do not require rewriting (for each word line), and it is not necessary to erase pages that do not need to be rewritten, reducing rewriting time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a non-volatile semiconductor memory device which is an embodiment of the present invention, FIG. 2 is a block diagram of a non-volatile semiconductor memory device which is another embodiment of the invention, and FIG. 3 is a block diagram of a conventional non-volatile semiconductor memory device. A block diagram of the device, FIG. 4 is a sectional view of a memo transistor. 3 - Drain diffusion region, 4 - Source diffusion region, = 8 - 6 - Floating gate, 8 - Control gate, 9a, 9b - Bin 1 ~ line, 10a, 10b - Source line, lla, 1lb - Word line, 21a-21d-Memory transistor. Agent Masuo Oiwa (2 idiots) Ward! t) l・zucO= Procedural amendment (voluntary) 20 Name of the invention Control method for non-volatile semiconductor storage device 3, Relationship to the case of the person making the amendment Patent applicant address 2 Maruno Potter-chome, Chiyoda-ku, Tokyo No. 3 Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent Address 2-3-5 Maruno Potter-chome, Chiyoda-ku, Tokyo
Detailed description and drawings of the invention to be amended. 6 Contents of amendment (1) Page 2 of the specification, lines 12 to 13 r 1
"a-1b is" is corrected to "r l a-1d is". (2) The drawings and Figures 1 to 4 shall be amended as shown in the attached sheet. Figure 1'0
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faction CI') ■ ・ ('J

Claims (1)

[Claims] A plurality of memory transistors each having a floating gate disposed above the source through an oxide film, and a control gate disposed above the floating gate and a substrate on the drain side via an oxide film, each memory transistor is a nonvolatile semiconductor memory device in which the drain is connected to a bit line, the source is connected to a source line, and the control gate is connected to a word line.Data is erased by applying a high voltage to the source line and grounding the word line. A control method for a nonvolatile semiconductor memory device, characterized in that writing is performed by applying a high voltage to the bit line and word line and grounding the source line.