JPH01282839A - Manufacture of element isolation - Google Patents
Manufacture of element isolationInfo
- Publication number
- JPH01282839A JPH01282839A JP11319088A JP11319088A JPH01282839A JP H01282839 A JPH01282839 A JP H01282839A JP 11319088 A JP11319088 A JP 11319088A JP 11319088 A JP11319088 A JP 11319088A JP H01282839 A JPH01282839 A JP H01282839A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- oxide film
- element isolation
- film
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 150000004767 nitrides Chemical class 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 4
- 210000003323 beak Anatomy 0.000 abstract 3
- 241000293849 Cordylanthus Species 0.000 description 7
- 230000000694 effects Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の素子分離製造方法に関し、特に１
μｍ以下の微細素子分離の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing semiconductor devices with element isolation, and in particular, 1.
The present invention relates to a method for forming fine element isolation of micrometers or less.
従来、この種の素子分離ではＬＯＣＯ８法が用いられて
いる。すなわち、第４図（ａ）に示すように、酸化膜２
を回してシリコン基板ｌ上に窒ｆＦ３３を設け、次に第
４図（ｂ）に示すようにこの窒化膜３をマスクにしてシ
リコン基板１を酸化して素子分離領域を形成する。Conventionally, the LOCO8 method has been used for this type of element isolation. That is, as shown in FIG. 4(a), the oxide film 2
Then, as shown in FIG. 4(b), the silicon substrate 1 is oxidized using the nitride film 3 as a mask to form an element isolation region.
上述した従来のＬＯＣＯ３法は、バーズビークと呼ばれ
る酸化膜のくい込み１６が生ずるため、実効的な素子分
離領域が広がってしまい、微細な素子分離領域が形成で
きないという欠点がある。The above-mentioned conventional LOCO3 method has the drawback that the effective element isolation region expands because the oxide film bite 16 called a bird's beak occurs, making it impossible to form a fine element isolation region.
本発明によれば、窒化膜をマスクにして選択酸化をし素
子分離領域を形成する方法において、窒化膜の側面に多
結晶シリコン側壁を設けてからシリコン基板を選択的に
酸化する工程を含む素子分離の製造方法が得られる。According to the present invention, a method for forming an element isolation region by performing selective oxidation using a nitride film as a mask includes a step of providing a polycrystalline silicon sidewall on the side surface of a nitride film and then selectively oxidizing a silicon substrate. A separation manufacturing method is obtained.
本発明では窒化膜の側面に多結晶シリコンの側壁を設け
ておくから、この多結晶シリコンが酸化されることによ
り、バーズビークの発生が抑制される。In the present invention, since a side wall of polycrystalline silicon is provided on the side surface of the nitride film, the occurrence of bird's beak is suppressed by oxidizing the polycrystalline silicon.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｇ）は、本発明の第１の実施例の一製
造方法を示す断面図である。シリコン基板１上に２０〜
５０μｍ厚の酸化膜２を介して窒化膜３を成長する（第
１図（ａ））。窒化膜の厚さは０．１μｍ〜０．３μｍ
程度が望ましい。次に素子分離領域４の窒化膜をエツチ
ングした後（第１図（ｂ））、多結晶シリコン５を成長
しく第１図（Ｃ乃、異方性シリコンエツチングによって
多結晶シリコン側壁６を窒化膜の側面に形成する（第１
図（ｄ））。次にシリコン基板１を熱酸化する。熱酸化
は、多結晶シリコン側壁６が完全に酸化される程度に行
う。FIGS. 1(a) to 1(g) are cross-sectional views showing one manufacturing method of the first embodiment of the present invention. 20~ on silicon substrate 1
A nitride film 3 is grown through an oxide film 2 with a thickness of 50 μm (FIG. 1(a)). The thickness of the nitride film is 0.1 μm to 0.3 μm
degree is desirable. Next, after etching the nitride film in the element isolation region 4 (FIG. 1(b)), the polycrystalline silicon 5 is grown. (first
Figure (d)). Next, silicon substrate 1 is thermally oxidized. The thermal oxidation is performed to such an extent that the polycrystalline silicon sidewall 6 is completely oxidized.
バーズビークは多結晶シリコン側壁が酸化されることに
より、窒化膜３と基板１の間に発生しない。Bird's beaks do not occur between the nitride film 3 and the substrate 1 because the polycrystalline silicon sidewalls are oxidized.
酸化膜７には、多結晶シリコン側壁６が酸化されること
によって生ずる突起９ができる。この突起は平坦化膜８
を形成（第１図（ｆ）） Ｌ、エツチングバックにより
除去できる。最後にマスク寸法通りの平坦化された酸化
膜１０が形成される（第１図（ｇ））。Protrusions 9 are formed in the oxide film 7 due to the oxidation of the polycrystalline silicon sidewalls 6. This protrusion is the flattening film 8
(FIG. 1(f)) L can be removed by etching back. Finally, a planarized oxide film 10 having the dimensions of the mask is formed (FIG. 1(g)).
第２図（ａ）〜（ｃ）は、本発明の第２の実施例の断面
図である。素子分離領域のシリコン基板１をわずか（例
えば０．１〜０．４μｍ）エツチングし、シリコン溝１
１を形成する。次に溝１１の側面に多結晶シリコン側壁
１３を形成した後、選択酸化を行い酸化膜１４を形成す
る。この実施例では、あらかじめ素子分離領域をエツチ
ングしておくため、シリコン基板１に深く入り込んだ素
子分離領域が形成できる利点がある。深い分離領域は、
素子間隔が狭くなったときの分離特性を著しく改善する
。酸化膜１２は多結晶シリコンエッチのストッパーとし
て設けであるが、無くても良い。酸化膜が無い方が、バ
ーズビークの発生はより抑制される。FIGS. 2(a) to 2(c) are cross-sectional views of a second embodiment of the present invention. The silicon substrate 1 in the element isolation region is slightly etched (for example, 0.1 to 0.4 μm) to form silicon grooves 1.
form 1. Next, after forming polycrystalline silicon sidewalls 13 on the side surfaces of trench 11, selective oxidation is performed to form oxide film 14. In this embodiment, since the element isolation region is etched in advance, there is an advantage that the element isolation region can be formed deeply into the silicon substrate 1. The deep separation region is
Significantly improves isolation characteristics when the element spacing becomes narrow. Although the oxide film 12 is provided as a stopper for polycrystalline silicon etching, it may be omitted. When there is no oxide film, the occurrence of bird's beak is more suppressed.
第３図は、本発明の第３の実施例の断面図である。窒化
膜３が薄いと、多結晶シリコン側壁が形成しにくくなる
。そこで、ＣＶＤ酸化膜１５を窒化膜上に形成し、段差
をつけて多結晶側壁６が容易に形成できるようにする。FIG. 3 is a sectional view of a third embodiment of the invention. If the nitride film 3 is thin, it becomes difficult to form polycrystalline silicon sidewalls. Therefore, a CVD oxide film 15 is formed on the nitride film with a step difference so that the polycrystalline sidewall 6 can be easily formed.
さらに、多結晶シリコン側壁６は、シリコン基板１に直
接接触させる。Furthermore, the polycrystalline silicon sidewall 6 is brought into direct contact with the silicon substrate 1.
これにより、バーズビークの発生をほとんどなくすこと
ができる。This can almost eliminate the occurrence of bird's beak.
以上説明したように本発明は、窒化膜の側面に多結晶シ
リコン側壁を設けることにより、バーズビークの発生を
抑えることができる効果がある。As described above, the present invention has the effect of suppressing the occurrence of bird's beak by providing polycrystalline silicon sidewalls on the side surfaces of the nitride film.
第１図（ａ）〜（ｇ）は本発明の第１の実施例を説明す
る素子断面図、第２図（ａ）〜（ｃ）は本発明の第２の
実施例を説明する素子断面図、第３図は本発明の第３の
実施例を説明する素子断面図、第４図（ａ） 、 （ｂ
）は従来の素子分離領域の形成方法を示す断面図である
。
１・・・・・・シリコン基板、２・・・・・・酸化膜、
３・・・・・・窒化膜、４・・・・・・素子分離領域、
５・・・・・・多結晶シリコン、６・・・・・・多結晶
シリコン側壁、７・・・・・・酸化膜、８・・・・・・
平坦化膜、９・・・・・・突起、１０・・・・・・平坦
化された酸化膜、１１・・・・・・シリコン溝、１２・
・・・・・酸化膜、１３・・・・・・多結晶シリコン側
壁、１４・・・・・・酸化膜、１５・・・・・・ＣＶＤ
酸化膜、１６・・・・・・バーズビーク。
代理人 弁理士 内 原 音
箔１国
号２図FIGS. 1(a) to (g) are cross-sectional views of an element explaining a first embodiment of the present invention, and FIGS. 2(a) to (c) are cross-sectional views of an element explaining a second embodiment of the present invention. Figures 3 and 3 are cross-sectional views of elements explaining a third embodiment of the present invention, and Figures 4 (a) and (b).
) is a cross-sectional view showing a conventional method of forming an element isolation region. 1... Silicon substrate, 2... Oxide film,
3...Nitride film, 4...Element isolation region,
5... Polycrystalline silicon, 6... Polycrystalline silicon side wall, 7... Oxide film, 8...
Flattening film, 9... Protrusion, 10... Flattened oxide film, 11... Silicon groove, 12...
... Oxide film, 13 ... Polycrystalline silicon side wall, 14 ... Oxide film, 15 ... CVD
Oxide film, 16...Bird's beak. Agent Patent Attorney Uchihara Otohaku 1 Country No. 2 Diagram
Claims (1)
形成する方法において、前記窒化膜の側面に多結晶シリ
コン側壁を設けてからシリコン基板を選択的に酸化する
工程を含むことを特徴とする素子分離の製造方法A method of selectively oxidizing using a nitride film as a mask to form an element isolation region, the method comprising the step of providing a polycrystalline silicon sidewall on the side surface of the nitride film and then selectively oxidizing the silicon substrate. Manufacturing method for element isolation
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11319088A JPH01282839A (en) | 1988-05-09 | 1988-05-09 | Manufacture of element isolation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11319088A JPH01282839A (en) | 1988-05-09 | 1988-05-09 | Manufacture of element isolation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01282839A true JPH01282839A (en) | 1989-11-14 |
Family
ID=14605838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11319088A Pending JPH01282839A (en) | 1988-05-09 | 1988-05-09 | Manufacture of element isolation |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01282839A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4109184A1 (en) * | 1990-11-17 | 1992-05-21 | Samsung Electronics Co Ltd | METHOD FOR FORMING A FIELD OXIDE LAYER OF A SEMICONDUCTOR COMPONENT |
| JPH08153777A (en) * | 1994-11-29 | 1996-06-11 | Nec Corp | Manufacture of semiconductor device |
| US5629230A (en) * | 1995-08-01 | 1997-05-13 | Micron Technology, Inc. | Semiconductor processing method of forming field oxide regions on a semiconductor substrate utilizing a laterally outward projecting foot portion |
| US5656537A (en) * | 1994-11-28 | 1997-08-12 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device having SOI structure |
| US5753962A (en) * | 1996-09-16 | 1998-05-19 | Micron Technology, Inc. | Texturized polycrystalline silicon to aid field oxide formation |
| US6306726B1 (en) | 1999-08-30 | 2001-10-23 | Micron Technology, Inc. | Method of forming field oxide |
| US6417093B1 (en) | 2000-10-31 | 2002-07-09 | Lsi Logic Corporation | Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing |
| US6586814B1 (en) | 2000-12-11 | 2003-07-01 | Lsi Logic Corporation | Etch resistant shallow trench isolation in a semiconductor wafer |
| US6613651B1 (en) * | 2000-09-05 | 2003-09-02 | Lsi Logic Corporation | Integrated circuit isolation system |
| US6617251B1 (en) | 2001-06-19 | 2003-09-09 | Lsi Logic Corporation | Method of shallow trench isolation formation and planarization |
-
1988
- 1988-05-09 JP JP11319088A patent/JPH01282839A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4109184A1 (en) * | 1990-11-17 | 1992-05-21 | Samsung Electronics Co Ltd | METHOD FOR FORMING A FIELD OXIDE LAYER OF A SEMICONDUCTOR COMPONENT |
| JPH04234146A (en) * | 1990-11-17 | 1992-08-21 | Samsung Electron Co Ltd | Formation method of field oxide film for semiconductor device |
| US5472905A (en) * | 1990-11-17 | 1995-12-05 | Samsung Electronics Co., Ltd. | Method for forming a field oxide layer of a semiconductor integrated circuit device |
| DE4109184C2 (en) * | 1990-11-17 | 1995-12-21 | Samsung Electronics Co Ltd | Method for forming a field oxide layer of a semiconductor device |
| US5656537A (en) * | 1994-11-28 | 1997-08-12 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device having SOI structure |
| JPH08153777A (en) * | 1994-11-29 | 1996-06-11 | Nec Corp | Manufacture of semiconductor device |
| US5629230A (en) * | 1995-08-01 | 1997-05-13 | Micron Technology, Inc. | Semiconductor processing method of forming field oxide regions on a semiconductor substrate utilizing a laterally outward projecting foot portion |
| US6114218A (en) * | 1996-09-16 | 2000-09-05 | Microm Technology, Inc. | Texturized polycrystalline silicon to aid field oxide formation |
| US5753962A (en) * | 1996-09-16 | 1998-05-19 | Micron Technology, Inc. | Texturized polycrystalline silicon to aid field oxide formation |
| US6306726B1 (en) | 1999-08-30 | 2001-10-23 | Micron Technology, Inc. | Method of forming field oxide |
| US6326672B1 (en) | 1999-08-30 | 2001-12-04 | Micron Technology, Inc. | LOCOS fabrication processes and semiconductive material structures |
| US6613651B1 (en) * | 2000-09-05 | 2003-09-02 | Lsi Logic Corporation | Integrated circuit isolation system |
| US6417093B1 (en) | 2000-10-31 | 2002-07-09 | Lsi Logic Corporation | Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing |
| US6586814B1 (en) | 2000-12-11 | 2003-07-01 | Lsi Logic Corporation | Etch resistant shallow trench isolation in a semiconductor wafer |
| US6617251B1 (en) | 2001-06-19 | 2003-09-09 | Lsi Logic Corporation | Method of shallow trench isolation formation and planarization |
| US6949446B1 (en) | 2001-06-19 | 2005-09-27 | Lsi Logic Corporation | Method of shallow trench isolation formation and planarization |
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