JPH01282642A - Data driving type computer - Google Patents

Abstract

PURPOSE:To evade the stoppage of processing due to a dead lock even when the dead lock occurs by providing a dead lock detector and a packet discharging control device. CONSTITUTION:When a dead lock occurs, a deal lock detector 9 informs a packet discharging control device that the whole of the device falls into the dead lock. It is received, and the packet discharging control device discharges a packet, which becomes the cause of the dead lock, out of the packet stored in a firing processing part 3. Thus, the dead lock is avoided and a data processing is restarted. The discharged packet, when the data processing is started, is returned to the firing processing part 3 again.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data-driven computer that aims at high-speed, parallel, and distributed processing. Specifically, the present invention relates to a data-driven computer configured to avoid stopping processing due to deadlock. [Prior Art] Regarding conventional data-driven computers, the present applicant has already made an invention in the application method [Associative Memory Device and Data-Driven Computer JA
This will be explained using PJ5863 (Patent Application No. 1982) as an example. The data-driven computer according to the application includes an input section that takes in packets from the outside into the computer, a program storage section that reads out a program according to the tag of this packet and outputs it as an instruction packet together with the packet data, and a program storage section that receives the instruction packet. a firing processing unit that performs firing processing and outputs a calculation packet; a calculation processing unit that performs calculation processing on the calculation packet and outputs a result packet; and a calculation processing unit that receives the result packet and transmits the result packet to an external device or the input unit. a branching mechanism for branching through packets between the firing processing section and the arithmetic processing section; and a merging mechanism for merging through packets between the program storage section and the firing processing section. Furthermore, a local bus through which through packets flow is provided between the branching mechanism and the merging mechanism, and a buffer is provided between the branching mechanism and the merging mechanism. It was there. The associative memory tα device includes: an address converter that latches the tag (data identifier) of the inputted first packet and outputs a packet input signal and a memory address; an address register that holds the memory address; and an address register that holds the memory address; A write register that holds the first packet and has a first presence bit (hereinafter referred to as FBI) indicating whether the packet is valid or invalid; and a write register that holds the packet and further the FB, and outputs from the address register. a waiting memory for reading the packet stored at the specified memory address or storing the contents of the write register; a read register for holding the second packet read from the waiting memory; and a read register for holding the second packet read from the waiting memory; an empty determination unit that determines whether or not two packets are valid and outputs the determination result as a determination signal; and a comparison between the tags of the second packet output from the read register and the first packet output from the write register. If there is a match, both the first and second packets are output, and if there is a mismatch, the one with the larger tag of both packets is output, and the comparison result is also output. a tag comparison section that outputs the second packet as a first comparison signal; a data pair generation section that appends the data of the second packet output from the tag comparison section to the first packet and outputs it; and the packet input signal, determination section. t or the first comparison signal, control of reading and writing of the waiting memory, control of outputting FB2 held in the read register to the empty determination section or outputting the second packet to the tag comparison section, a control unit that performs control to output the first packet held in the write register to the tag comparison unit, and control to disable the FBI of the write register when the first comparison signal indicates “1-match”; It was established. Figure 5 shows a block configuration diagram of an example of a data-driven computer.
This is a program storage unit that reads the tag (data identifier) and instruction of the packet output from the input unit 1 and outputs it as an instruction packet. Reference numeral 3 denotes a firing processing unit which receives an instruction packet output from the program storage unit 2, detects an instruction packet having the same tag as that of the instruction packet, and outputs it as an operation packet; It stores command packets output from the program storage section 2. 4 receives the calculation packet output from the firing processing unit 3 and performs the calculation specified by the instruction that is part of the tag of the calculation packet,
an arithmetic processing unit that outputs a result packet; 5 is an output unit)
, receives the result packet from the arithmetic processing unit 4, and if the external flag that is a part of the tag indicates "external output", outputs the result packet to the outside and sets the external flag to "
In the case of "internal output", the result packet is output to the input section 1. 6 is a branching mechanism for sending the packet to the buffer when the flag of the packet indicates "through", and 7 is a merging mechanism for sending the data sent from the buffer 8 to the firing processing section 3. 8 is a buffer for temporarily storing packets. FIG. 6 is a block diagram of an associative memory device used as the firing processing unit 3 of the data-driven type machine X, in which 31 removes the tag of the first instruction packet, determines the memory address, and outputs the packet input signal. and an address converting section 32 that outputs a memory address is an address register that holds the memory address from this address converting section 31. 33
34 is a write register that holds the first instruction packet and has an FBI indicating whether the packet is valid or invalid; 34 is a waiting memory that stores the packet and PB; The first command packet is read from the write register 33 to the memory address from the address register 32. A read register 35 holds the second instruction packet and PB2 read from the waiting memory 34. Further, numeral 36 examines the PB2 output from the read register 35 and outputs a determination signal as a determination signal as to whether or not the second instruction packet is valid. The tag comparison unit compares the tags of the instruction packet and the first instruction packet output from the write register 33 to detect a match or a magnitude, and outputs the comparison result as a first comparison signal, and also outputs a "match" signal. In the case of , both the first and second instruction packets are output, and in the case of ``mismatch'', the one with the larger tag is output. 38 is this tag comparison section 37
The first comparison signal output from the first comparison signal and the first comparison signal output from the first comparison signal. A data pair generation unit that receives both or one of the second instruction packets and outputs an operation packet or a through packet, and when the first comparison signal indicates “match”, the data pair generation unit outputs the data of the second instruction packet. It is attached to the first instruction packet and output as @non-packet, and when it indicates "mismatch", it is attached to the first instruction packet. Second
For the instruction packet with the larger tag, the sp-bucket puffer that is part of the tag is set to sy-, and is output as a through packet. Further, 39 is the packet input signal, the determination signal and the first
This is a control section that performs the following controls in response to a comparison signal. That is, (1) Control of reading or writing to the waiting memory 34; (2) Transferring PB2 of the read register 35 to the empty determination unit 36;
Alternatively, control for outputting the second instruction packet to the tag comparison unit 37; Control for outputting the first instruction packet of the write register 33 to the tag comparison unit 37; and ■ Control for outputting the first instruction packet of the write register 33 to the tag comparison unit 37; If 33 PEIs are invalidated and indicated as “inconsistent”,
It controls writing the command packet and FBI to the waiting memory 34 by validating the J'BI. FIG. 7 is a block diagram of the tag comparison section 37.
1,372 are the 1st. In the second comparison circuit, the first comparison unit Pr371 detects the generation number or color number that is part of the tag of the second and first instruction packets output from the read register 35 and the write register 33. It inputs and compares them, detects coincidence or magnitude, and outputs the detection result as a second comparison signal. Further, the second comparison circuit 372
The second and first output from both registers 35 and 33
Destination node numbers, which are part of the tag of the instruction packet, are input and compared, a match or a magnitude is detected, and the detection result is output as a third comparison signal. 373 is a second register that holds the second instruction packet output from the read register 35;
374 is the first output from the write register 33.
This is the first register that holds instruction packets. i, 375 is the second. Upon receiving the third comparison signal, one of them is outputted as the first comparison signal, and the first. This is a comparison/judgment circuit that controls the second registers 374 and 373), and more specifically, when the comparison signal 'j42 indicates "mismatch", the second comparison signal is set as the first comparison signal, and the second comparison signal is set as the second comparison signal. If the comparison signal indicates a "match," the third comparison signal is output as the first comparison signal, and the first comparison signal is output as the first comparison signal.
With the comparison signal of 1st. 2nd register 3f 4, 3f 3Kf
This control controls the output of the first and second instruction packets held in the first and second instruction packets. Next, the operation will be explained. FIG. 11 shows the packet format used in the data-driven computer. A packet consists of a tag (data identifier), first data, and second data, and the tag includes a through packet flag, an external flag, a generation number or a color number, a destination node number, an instruction, and an L/R graph. configured. The input section 1 inputs a packet having a tag and first data inputted from the outside, and a packet having a tag and first data outputted from the output section 5, and outputs them to the program storage section 2. The program storage unit 2 stores the data flow graph in its memory, and when a packet is input, the destination node number, command, and input packet are stored from the memory using the destination node number, which is part of the tag of the input packet, as an address. Reads the L/R flag indicating whether the data it has is the left or right input of the instruction, and the destination node number that is part of the tag of the input packet. The instruction and L/R graph are updated and output together with the first data as a first instruction packet. This first command packet is input to the firing processing section 3, and the firing geography section 3 outputs a calculation packet. The firing processing section 3 uses the associative memory shown in FIG. 6, and its operation will be explained with reference to FIG. The first instruction packet output from the program storage section 2 is input to the address conversion section 31 and the write register 33. The address conversion unit 31 outputs a packet input signal indicating that the first instruction packet has been input to the control unit 39, and also outputs the generation number or cut number and destination node number that are part of the tag of the first instruction packet. The memory address of the waiting memory 34 is determined and output. Control ff1s39c to which the packet input signal is input;
Control is performed to hold the memory address output from the address converter 31 to the address register 32, so that the address register 32 holds the memory address. Next, the control unit 39 sends a mode signal to the waiting memory 34 indicating the mode of reading or writing from the memory.
The address register 32 is controlled to output the memory address held by the address register 32 to the waiting memory 34. The waiting memory 34 to which the mode signal and memory address are input has a tag, a command packet with data, and PB as one piece of information, as shown in FIG. Of this information, FB is a bit indicating whether or not the tag and data are valid. The waiting memory 34 has a mode signal and an address vs;
Input the memory address output from ty, evening 32,
The PB and instruction packet stored in the waiting memory 34 specified by the memory address are read and outputted to the read register 35. Read register 35
FB2 held at
Ru. The vacancy determination unit 3'6 outputs PBZ output from the read register 35 to the control unit 39 as a determination signal. When the determination signal is inputted, the control unit 39 writes valid to PBl of the write register 33, outputs the mode signal as "Write" to the waiting memory 34, and sends the corresponding information to the address register 32. Controls output of the memory address held by the address register 32 to the waiting memory 34, and outputs the first command packet and FBI held by the write register 33 to the waiting memory 34. Take control. Waiting memory 3 into which a mode signal indicating the "write" mode is input
4 stores the first instruction packet and PBI outputted from the write register 33 at the memory address outputted from the address register 32. Therefore, when the determination signal indicates invalidity, since the area of the waiting memory 34 specified by the memory address held in the address register 32 is empty, the first instruction packet held in the write register 33 and the FBI are stored in the waiting memory. 34 and waits for an instruction packet with the same tag. When the determination signal indicates validity, the control unit 39 controls the write register 33 and the read register 3 to output the first and second instruction packets 2 held in the write register 33 and the read register 35 to the tag comparison unit 37.
Do this for 5. Next, the operation of the tag comparison section 37 will be explained according to the block diagram shown in FIG. The first instruction packet output from the write register 33 is held in the first register 374. Further, the second instruction packet output from the read register 35 is held in the second register 373. The generation number or cuff number, which is part of the tag of the first and second instruction packets output from the write register 33 and the read V raster 35, is sent to the first comparison circuit 371, and the destination node number is sent to the second comparison circuit. Sent to 372. 1st
The comparison circuit 371 compares the generation #rt or the number of the two instruction packets, detects a match or a magnitude, and uses the comparison result as a second comparison signal to the comparison output determination circuit 3.
Output to 75. Further, the second comparison circuit 372 compares the destination node numbers of both instruction packets, detects a match or a magnitude, and uses the comparison result as a third comparison signal to the comparison output determination circuit 375.
Output to. If the second comparison signal indicates "mismatch (packet collision)", the comparison output determination circuit 375 outputs the second comparison signal as the first comparison signal, and outputs the second comparison signal as the first comparison signal, and outputs the second comparison signal as the first comparison signal, Control is performed for the first and second registers 374 and 373 to output the larger one. Further, if the second comparison signal indicates "match", the third comparison signal is output as the first comparison signal, and if the third comparison signal indicates "match", both command packets are output as "mismatch" (packet (collision)", the control to output the one with the larger destination node number of both command packets is performed. The data pair generation section 38 generates the first comparison signal outputted from the tag comparison section 37, the first comparison signal outputted from the tag comparison section 37, and the first comparison signal outputted from the tag comparison section 37. If both or one of the second command packets are input and the first comparison signal indicates "match",
The data of the second instruction packet is attached (fired) to the data portion of the first instruction packet indicated by the L/R flag of the second instruction packet, and is output as an operation packet. Further, if the first comparison signal indicates a "mismatch", the first or second instruction packet is set to throughput, and this instruction packet is output as a S/V-packet. Further, the control unit 39 inputs the first comparison signal, and receives the first comparison signal.
If the comparison signal indicates a "match", the PBI of the write register 33 is invalidated, and if the tag of the first instruction packet is smaller than the tag of the second instruction packet, the FBI of the pledge register 33 is validated. . At the same time, a mode signal indicating "write" is output to the waiting memory 34, and the address register p32 is output to the address register 32.
controls to output the memory address held by the write register 33, and outputs the first instruction packet and PI 31 held by the write V dimeta 33 to the write register 33, thereby outputting the first instruction to the waiting memory 34. Store packets and FBI. As a result of the above operation, if the tags of the first and second instruction packets match, the first and second instruction packets fire, are output as an operation packet, and the second instruction packet is stored in the memory 34. In order to invalidate the area, the FBI of the sorting register 33 is invalidated and stored into the memory 34. Also, 1st. If the tags of the second instruction packet do not match (packets collide) and the tag of the first instruction packet is smaller than the tag of the second instruction packet, the waiting memory 34
The second instruction packet stored in the content addressable memory device and the instruction packet input to the content addressable memory device are exchanged. If the tag of the first instruction packet is larger than the tag of the second instruction packet, the second instruction packet will be stored as is as soon as it is stored in the waiting memory 34, and the 16th instruction packet will be output. Here, the operation of the associative memory device will be explained using FIGS. 8(a) and ('b). In order to simplify the explanation, it is assumed here that the generations 'af or the number of packets are all the same, and the memory used as the waiting area can store four packets. “3” as the destination node number
The first and fourth packets with "7" as the destination node number and the second and third packets with "7" as the destination node number use the same memory address 13" as a waiting area. Therefore, the first packet is input and then the fourth packet is input. When a packet is input, the first and fourth packets are fired because their destination node numbers are both '3', and are output as calculation packets. Now, consider the case where the first packet is input and then the second packet is input. When the first packet is input, since the first packet has 3" as the destination node number, it is stored at the memory address "3°. Second
Since the packet has "7" as the destination node number, it will indicate the memory address "3m".Therefore, the destination node numbers of the first and second packets are compared, and the destination node number of the second packet is Since the destination node number of is larger (the packet collided), the second packet is output as a through-packet flag, and the 17th <get is directly stored at memory address "3" ” and waits for the fourth packet. Next, consider the case where the second packet is input, followed by the first packet. The second packet has “7” as the destination node number, It is stored in the memory address "3". When the first packet is input in this state, the destination node number of the first packet is '3°, so it will inevitably indicate the memory address "3". , 1st
The destination node numbers of the packet and the second packet are compared, and since the destination node number of the first packet is smaller (the packets collided), the second packet stored at memory address "3" is The through packet flag becomes through and is output as through v −/<
The calculation packet output from the firing processing unit 3 using an associative memory device is input to the calculation geography unit 4, and the data is stored in accordance with the instructions that are part of the tag of the calculation packet. The arithmetic processing is performed and a result packet is output.The output unit 5 inputs the result packet from the arithmetic processing unit 4, determines the external flag that is part of the tag of the result packet, and determines whether the external flag indicates the external output. If the external flag indicates internal output, the result packet is output to the input unit 1.The SUL m packet output from the firing processing unit 3 is sent to the arithmetic processing unit 4 and the program storage unit 2. Then, without being processed,
It returns to the firing processing unit 3 again and undergoes the firing process again as a command packet.As a second specific example, as shown in FIG.
Consider the case of executing a structured dataflow graph. In FIG. 4, the main block 41 and the loop 49 represent the input side of the data flow graph having a loop structure, and the graph 50 represents the output side of the data flow graph having the loop structure. A synchronization block 45 detects that all data have completed one μm period, and a condition determination 44 determines whether the loop should be continued again or terminated. In response to the signal from the condition judgment 44, the node 46TG passes the data input from the right arc only when the truth value of the data input from the input arc from the left side is true, and vice versa. The node 47S performs the process of absorbing the data, continues the loop, and terminates it.
When the truth value of the data input from the input arc from the left side is true, W outputs it to the left side, and when it is false, it outputs it only to the right arc. By performing this operation, it is possible to continue the loop. In the case of termination, a data packet is sent to the output side of the graph. Now, in the data-driven computer shown earlier in the conventional example,
Consider the case where a dataflow graph having the loop structure shown in FIG. 4 is executed. The node number of the node 51 in FIG. 4 is O, and the node number of the node 48 is 80. Let the left input packet of node 48 be the first packet, and the right input packet of node 51 be the second packet. As shown in FIG. 8(b), the first packet and the second packet point to the same memory address in the operand memory (memory address 'O'). If the packet arrives, the second packet will occupy the location at address 10'. Even when the first packet arrives and causes a hash collision, conventional data-driven computers determine whether to give priority to the first packet or the second packet, depending on the node number to which the data packet is next directed. Since the node number (80) of the second packet is greater than the node number (0) of the first packet, the first packet is treated as a through packet. Furthermore, since the node 51 is waiting for the data packet after the second packet and the first packet have been processed by the node 48, this data processing will completely stop unless the first packet is processed. . However, because the second baguette interferes and the first packet is not processed, the processing of this data flow graph remains in a deadlock state and stops forever. [Problem to be solved by the invention] When processing a complex data flow graph, as in the second specific example explained in the conventional example, the data processing of a data-driven computer may be affected depending on the order in which data packets arrive. °C may be interrupted and permanently stopped (deadlock state). [Means for solving the problem J] In a data-driven computer consisting of an input section, an output section, a program storage section, a processing section, and an arithmetic processing section as shown in the conventional example, ■Deadlock detection device■ Packet release It is equipped with a control device. ■As a deadlock detection device, the data processing system consisting of the five parts mentioned above has the function of detecting a deadlock state where processing is completely interrupted before the end of data processing, and sending a deadlock signal to the packet release control device (■). It is something. ■As a packet release control device, in order to receive a deadlock signal from the deadlock detection device and release one or more packets stored in the firing processing section,
It controls the packet waiting function of the firing processing section. "Operation" In the invention of the present application, in a data-driven computer,
Depending on the order in which data packets arrive, deadlock may occur. At this time. The deadlock detection device notifies the packet emission control device that the entire device has fallen into a deadlock, and in response, the packet emission control device detects the cause of the deadlock from among the packets stored in the firing processing section. By discharging the packets that have become , deadlock is avoided and data processing is resumed. The released packet will be returned to the firing processing section once data processing begins. [Example J] Hereinafter, a first example of the present invention will be described with reference to the drawings. FIG. 1 shows a block configuration diagram of a first embodiment of a data-driven computer. In the figure, 1 is an input section for inputting an external transfer packet, 2 is an input section for storing a data flow graph, and The tag of the packet output from 1 (
This is a program storage unit that reads instructions according to data identifiers and outputs them as instruction packets. Reference numeral 3 denotes a firing processing unit which receives an instruction packet output from the program storage unit 2, detects an instruction packet having the same tag as that of the instruction packet, and outputs it as an operation packet; It stores command packets output from the storage unit 2. 5 is an output unit which receives the calculation packet output from the 4-cigarette firing processing unit 3, performs the calculation specified by the instruction that is part of the tag of the calculation packet, and outputs the result packet; After receiving a result packet from the arithmetic processing unit 4, if the external flag that is part of the tag indicates "external output", the result packet is output to the outside, and the external flag indicates "internal output". If it indicates, the result packet is output to the input section 1. Reference numeral 9 is a timer. In this embodiment, the timer 9 is used as a deadlock detection device, and the timer 9 is used as a deadlock detection device, and when a certain period of time has elapsed since no calculations are performed in the calculation processing unit, it is regarded as a deadlock state, and the deadlock is detected. A lock signal is sent to the firing processing section 3. The ignition processing section 3 has a built-in packet release control device.
When a packet collision occurs or when a deadlock signal is received from the timer 9, it is determined which packet is to be a through packet, and that packet is output. Through packets are sorted at the branching section 7 and stored in a buffer, and sent to the merging section 8 while the device is performing arithmetic processing.
is sent to the ignition processing section 3 again. FIG. 2 is a block diagram of an associative memory device used as the firing processing section 3 of the data-driven computer, in which 31 hashs the tag of the first instruction packet, determines the memory address, and stores the packet input signal and the memory. The address converter 32 that outputs the address is an address register that holds the memory address from the address converter 31. 33
34 is a write register that holds the first instruction packet and has an FBI indicating whether the packet is valid or invalid; 34 is a waiting memory that stores the packet and PB; The first instruction packet is read from the write register 33 to the memory address from the address register 32. A read register 35 holds the second instruction packet and PB2 read from the waiting memory 34. Further, numeral 36 examines the PB2 output from the read register 35 and outputs a determination signal as a determination signal as to whether or not the second instruction packet is valid. It is a tag comparison section that compares the tags of the instruction packet and the first instruction packet output from the write register 33 to detect a match or a size. In the case of "mismatch", both the first and second instruction packets are output, and in the case of "mismatch", the one with the larger tag is output. 38 is this tag comparison section 3
7 and the first comparison signal output from the first. A data pair generation unit that receives both or one of the second instruction packets and outputs an operation packet or a through packet, and when the first comparison signal indicates "match", the second instruction packet The data of the first instruction packet is attached to the first instruction packet and output as a calculation packet, and if it indicates a "mismatch", the data of the first instruction packet is added to the first instruction packet and output as a calculation packet.
For the second command packet with a larger tag, the through packet flag, which is part of the tag, is set to sp-, and the packet is output as a through packet. Further, 39 is the determination multiple of the packet input signal 9 and tg
This is a control unit that performs the following control in response to the comparison signal of l. That is, (1) Control of reading or writing to the waiting memory 34; (2) Transferring PB2 of the read register 35 to the empty determination unit 36;
Alternatively, control for outputting the second instruction packet to the tag comparison unit 37; Control for outputting the first instruction packet of the write register 33 to the tag comparison unit 37; and ■ Control for outputting the first instruction packet of the write register 33 to the tag comparison unit 37; 330 FBI is invalidated and indicates “inconsistency”,
It controls writing the command packet and FBI into the waiting memory 34 by validating the FBI. Further, 40 is a DL control unit. In this embodiment, the DL control unit 40 is used as a packet release control device, receives a deadlock signal from the timer 9, reads out the waiting memory 34, and reads out the read register 330F.
Disable BI. Then, the tag flag of the data packet is set to 1st/L/J, and control is performed to output it as a through packet. FIG. 3 shows the internal configuration of the DL control section. 401 receives the good lock signal from the timer 9, and
A random number generator 402 generates memory addresses using random numbers, and a flag generation unit 403 rewrites the flag of the address data generated by the random number generator 401 to "S)v-1". This is a signal generator that generates two signals: a judgment signal for disabling data FBI, and a mode signal for setting the memory to read mode.The operation will be explained next. The deadlock avoidance method will be explained using the second concrete example. Consider the case where a data flow graph having a more μm structure shown in Fig. 4 is processed. Let the node number of node 51 in Fig. 4 be O. , the node number of node 48 is 80. The right input packet of node 48 is the first packet,
Let the left input packet of node 51 be the second packet. Now, assuming that the second packet arrives earlier than m1t<key, the first packet and the second packet point to the same memory address in the memory 34 (memory address "o"). Now, the second packet occupies address 101. Even if the first packet arrives and a hash collision occurs, the conventional data exchange method described above compares the node numbers of the data tags, so the node number is larger than the second packet's node number (0). The second packet is output as a t-through packet. Moreover, the node 51 with the node number 0 sends the second packet, and the first packet goes to the node 4.
Since it is waiting for the data packet processed in step 8, unless the first packet is processed, this data processing will completely stop, leading to a deadlock situation. The timer 9 measures the time since the last arithmetic processing was performed in the arithmetic processing section 4, and sends a deadlock signal to the DL control section 40 of the firing processing section 3 when the measured time exceeds a certain fixed time. The timer 9 initializes a time count each time an arithmetic process is performed or outputs a deadlock signal, and determines that a deadlock state occurs when no arithmetic process is performed for a certain period of time. Upon receiving the deadlock signal from the timer 9, the random number generator 401 of the DL control unit 40 randomly generates an address t-, sends a signal to the address register 32, flag generation unit 402, and signal generator 403, and generates a signal. The device 403 puts the data at the address in the memory 34 into read mode and invalidates the PBI at the address. The flag generation unit 402 writes the flag of the data packet read from the memory 34 and outputted to 1 through, and outputs it as a through packet. −
/(The data packet output as a kerato is sent through the branching unit 7 to the buffer 8. While this series of operations is returned ab by the deadlock signal from the timer 9, the second packet is transferred from the memory 34. The first packet is output as a through packet, and while the second packet remains in the buffer 8, the first packet is stored in the memory 34. Thereafter, it is sent to the arithmetic processing section 4 together with the corresponding data packet, where arithmetic processing is performed. When the data processing is restarted, the packets remaining in the buffer 8 will be gradually returned to the firing processing unit 4 through the merging unit 6. This will prevent the data processing from breaking out of the deadlock. Next, as another example, a case in which the present invention is applied to the tweeter-driven computer of the earlier application was described, but it can also be applied to other data-driven computers that use hash memory in the firing geography section. It goes without saying that this is possible. ■In a data-driven computer that does not use hash memory for the firing processing section but uses ordinary memory for the operand memory, an overflow of the obefund memory is a deadlock condition. It is possible to avoid the Sibra lock by deeming and detecting this detection signal, and similarly discharging the data packet from the operand memory in response to this detection signal. ■ Figure 10 shows a second embodiment of the present invention. However, in the first embodiment, the detection of the stoppage of data processing in the data processing system was focused on the data processing of the arithmetic processing unit 4. Focusing on data processing such as 1 branch, the timer 9 detects that a certain period of time has elapsed since the input section 1 and the output section 5 are no longer performing data processing, and the same data as in the first embodiment is output. A drive-type computer can be constructed. ■The address generation method for the hash memory in the packet release control device is as follows, instead of the random number generator 401 in FIG.
By using the counter 404, two or more addresses are generated at the same time (see Figure 9), and two or more addresses are generated simultaneously (see Figure 9 (bJ)). Two or more packets stored in the computer may be simultaneously released. ■Methods for measuring the time elapsed by the timer include (A) a method of measuring using the system clock that the computer system itself has; (b) data It may also be realized using an analog circuit, such as discharging a capacitor or the like every time a process is performed, and performing the process in the time from when electricity begins to be stored until a certain amount of charge is accumulated [Effects of the invention J and above] According to the present invention, even if a Sibra lock occurs in data processing of a data-driven computer, by providing a deadlock detection device and a packet release control device, it is possible to promptly avoid stopping processing due to deadlock. A data-driven computer can be obtained.Furthermore, if a deadlock detection device and a packet release control device are provided in the data processing system of a data-driven computer using hash memory as the memory of the firing processing section, Even if a deadlock state due to a collision occurs, it has a relatively simple structure and uses an associative memory device with a small capacity of memory and an associative memory device with a small capacity of memory in the firing processing section, but can still stop the MW due to a deadlock. A data-driven calculator is obtained that can be avoided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data-driven computer according to a first embodiment of the present invention, FIG. 2 is a block diagram of an embodiment of a firing processing section constituting the computer, and FIG. 3 is a block diagram of a firing processing section according to a first embodiment of the present invention. FIG. 4 is a block diagram of an example of a DL control section built in the computer, FIG. 4 is a diagram showing an example of a loop data flow graph, and FIG. 5 is a diagram showing a conventional example of a data-driven computer. 6 is a block diagram showing a conventional example of the firing processing section that constitutes the computer; FIG. 7 is a block diagram showing a conventional example of the tag comparison section that constitutes the firing processing section; FIG. 8, etc. )
Figure 8(b) shows an example of a digital glove.
9 is a diagram showing an example of the correspondence between node numbers and memory addresses, FIG. 9 is a diagram showing a second embodiment of the block diagram of the DL control section constituting the firing processing section, and FIG. 10 is a diagram showing the data of the present invention. FIG. 11 is a diagram showing the internal configuration of a data packet processed by the computer, and FIG. 12 is a diagram showing the contents of the memory of the computer. 1 indicates the input section, 2 indicates the deroghum storage section, 3 indicates the firing processing section, 4 indicates the arithmetic processing section, 5 indicates the output section, 6 indicates the branching section, and 7 indicates the merging section. 8 indicates a buffer, 31 indicates an address translation unit, 32 indicates an address register, 33 indicates a write register, 34 indicates a memory, 35 indicates a read register,
36 indicates a free space determination section, 37 indicates a tag comparison section, and 3
8 indicates a data pair generation section, 39 indicates a control section, and 4.
0 indicates the DL control unit, 401 indicates the random number generator, 4
02 indicates a flag generation unit, and 403 indicates a signal generator. In addition, in the figures, the same reference numerals indicate the same parts or the priest parts. Agent Masuo Oiwa Figure 1 Figure 3 Figure 4 Figure 5 Figure 7 (b) Figure 9 (d) (b) Figure 10 Figure 12 Procedure amendment (voluntary) l. Display Patent Application No. 63-112844 2,
Name of the invention Data-driven computer 3, relationship to the amended person case Patent applicant address 2-2-3 Marunouchi, Chiyopo 1-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4. Address of the agent: Mitsubishi Electric Corporation, 2-2-3 Marunouchi, Chiyoda-ku, Tokyo 5. Detailed description of the invention in the specification to be amended. 6. Contents of amendment (1) rAPJ5863 (
``Special Application No. 1988'' was replaced with ``Special Application No. 1982-54''.
No. 406”. (2) In the 37th page, line 13 of the specification, the phrase "ignition processing section" is corrected to "the ignition processing section." After and

Claims (1)

[Claims] An input unit that takes in packets from the outside, a program storage unit that reads out a program according to the tag of this packet and outputs it as an instruction packet together with packet data, and a program storage unit that receives this instruction packet and performs firing processing. , a firing processing unit that outputs a calculation packet; a calculation processing unit that performs calculation processing on the calculation packet and outputs a result packet; and a calculation processing unit that receives the result packet and outputs the result packet to the outside or to the input unit. an output unit; a deadlock detection device for detecting a deadlock when data processing is completely interrupted before completion in the data processing system consisting of the five parts described above and the data processing system is in a deadlock state; In order to release one or more packets stored in the firing processing unit in response to a deadlock signal output from the deadlock detection device,
A data-driven computer consisting of a packet release control device that controls the packet waiting of the firing processing section.