JPH01279681A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To reduce power consumption by installing a means to open and close a current path from a power source to a ground wire, closing the current path in a horizontal blanking period, and opening the current path in a horizontal scanning period. CONSTITUTION:One MOS is provided for one preamplifier, and a gate is connected with a terminal S5. When the horizontal blanking period starts, the potential of the S5 becomes higher, and the states of a preamplifier activating switch 21 and a unity gain buffer amplifier activating switch 22 become ON states. Action to hold the d.c. output voltage of a unity gain buffer amplifier in memory capacity is executed by this. When the horizontal scanning period starts, the potential of the S5 becomes lower, and the states of the preamplifier activating switch 21 and the unity gain buffer amplifier activating switch 22 become OFF states. As the result, for both the preamplifier and the unity gain buffer amplifier, the current path from an amplifier power source 18 to an amplifier ground wire 19 is disconnected.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a solid-state imaging device, particularly a highly sensitive solid-state imaging device.

The present invention relates to an MO8 type solid-state imaging device suitable for achieving low smear.

[Conventional technology]

Conventionally, MO8 is a typical type of two-dimensional solid-state imaging device.
type solid-state imaging device is known (M.

Aokj et a]: ISSC Digest of Technical Papers, p26. Feb
.

13.1980). The above-mentioned conventional technology has a circuit configuration as shown in FIG. In FIG. 7, 1 is a photoelectric conversion element (photodiode) arranged two-dimensionally to perform photoelectric conversion, 2 is a vertical scanning circuit that selects each row, and 3 is a selection signal from the vertical scanning circuit 2 to each vertical switch. 4 is a vertical switch that opens and closes according to the selection signal from the vertical scanning circuit 2; 5 is a horizontal scanning circuit that selects each row; 6 is a horizontal switch that opens and closes according to the selection signal from the horizontal scanning circuit 5; An amplifier circuit provided outside the element, 8 is a vertical signal line, and 9 is a horizontal signal line.

The above circuit performs the following operation. First, during the horizontal blanking period, the voltage of the vertical gate line 3 of the row selected by the vertical scanning circuit 2 becomes high, the vertical switch 4 opens, and signal charges are sent from the photodiode 1 to the vertical signal line 8. Thereafter, during the horizontal scanning period, the horizontal scanning circuit 5 operates, the horizontal switches 6 sequentially open and close, and the signal charges are sequentially amplified and outputted by the amplifier circuit 7 outside the element via the horizontal signal line 9.

[Problem to be solved by the invention]

The above-mentioned MO8 type solid-state image sensor has two points: kTC noise generated by thermal noise of the horizontal switch 6 when it opens and closes, and noise of the external wideband amplifier 7 required for high-speed horizontal scanning. No consideration was given. As a result, the noise is large and the signal-to-noise ratio (S/
There was a problem that the N ratio was low. Furthermore, - there is no consideration given to the smear phenomenon caused by excess charge generated in the vertical signal line 8 due to light leakage during the horizontal scanning period, and it is difficult to capture a bright subject during high-illuminance imaging. There was a problem in that bright lines that looked like white tails sometimes appeared at the top and bottom of the reproduced image, significantly degrading the image quality.

On the other hand, each vertical signal line 8 is equipped with an amplifier circuit that detects and amplifies the potential of the vertical signal line 8, and an amplifier circuit that resets the vertical signal line 8.
means for detecting the difference between the potential of the empty vertical signal line 8 after reset and the potential of the vertical signal line 8 when there is a signal and outputting only the true signal component (hereinafter referred to as correlation 2). The inventors have proposed a solid-state imaging device that achieves low noise and low smear by providing a heavy sampling circuit (Japanese Patent Application No. 128123/1982).
issue).

FIGS. 8 and 9 are diagrams for explaining the operation of an example of this type of solid-state image sensor. This will be explained below according to the figures.

FIG. 8 shows a circuit configuration diagram of the solid-state image sensor.

In the figure, 1 to 6, 8 and 9 are the same as those in FIG. 71 is a preamplifier circuit for detecting and amplifying the potential of each superimposed signal line; 72 is a self-bias switch for setting the preamplifier circuit 71 to a high gain region; 74 is a camp link capacitor; 73 is a feedback capacitor; 75 is a clamp switch,]
2 is a unity gain buffer amplifier, 20 is a unity gain buffer amplifier output line, and 13 to 17 are unity gain buffers (Y, A) that cancel offsets.
, HAOLIE et al: IEE Journal of Solid State Circuits VoU, 5C-14, pp, 9 6 1-9 6
9. 1)ec.

1979 (IEEE J, 5solid-5tate C
j, rcuist, Vo Q, 5C-14pp,
961-969. 13 is a memory capacity, 14 is a sample hold switch for writing a signal to the memory capacity 13, 15 is a signal readout switch, 16 is a switch for offset cancellation, and 17 is an output buffer amplifier. , 18 and 19 are power supply lines and ground lines for each amplifier. Terminal 0UT
1,0UT2 is the output terminal, and the terminal Vv contains the bias voltage necessary for the operation of the unity gain bath amplifier.
The power supply voltage of the amplifier and the ground voltage are applied to o and Vs. Further, FIG. 9 shows pulse timing for driving the element shown in FIG. 8. 81 to S5 are voltages applied to each terminal in FIG. Note that in this example, each switch is an N-channel switch, and in the case of a P-channel switch, the polarity of the clock signal may be inverted. The operation of this example will be explained below.

When entering the horizontal blanking period, first, the DC output voltage of each row when there is no signal charge and only smear charge is read into the memory capacity 13-1 of the unity gain buffer. SL, S2. S3. The potential of S5 goes high and switches 72, 75.14-1.16 open. At this time, the vertical signal line 8 is reset and the amplifier 71 is biased to a high gain region. Further, the input terminal of the unity gain buffer amplifier 12 is reset to the bias voltage Vν. Furthermore, the input terminal voltage of the output buffer amplifier 17 becomes the offset voltage of the output buffer amplifier 17 (tr in FIG. 9). Switch 72 is then closed and preamplifier 71 is activated. At this time, the vertical signal line fluctuates by Vh due to the kTC noise, but since the switch 75 is open, this noise is not transmitted beyond the buffer amplifier 12 (12 in FIG. 9). After this, the switch 75 is closed and the unity gain buffer amplifier 12 is activated, and the potential fluctuation of the vertical signal line 8 after this time is reflected by the preamplifier 71, the coupling capacitor 74, and the unity gain buffer]2.
is transmitted to the memory capacity] 3-1 (t8 in FIG. 9). After this, after a time period of Ts+ has elapsed, the switch 14-] is closed, and the DC output voltage of the buffer amplifier 12 when there is no signal charge and only 5 smear charges is maintained at one electrode of the memory capacitor 13-1. (9th
1+) in the figure. Similarly, the DC output voltage when there are signal charges and smear charges is read out to the memory capacity 13-2 of the unity gain bath sofa. Switch 72, 7
5.14-2 is opened and the vertical signal line 8 and the input terminals of the buffer amplifier 12 are reset. Thereafter, after the switches 72 and 75 are closed in sequence, the potential of a certain vertical gate line 3 selected by the vertical scanning circuit 2 becomes high, the vertical switch 4 is opened, and signal charges are sent from the photodiode to the vertical signal line 8. Time TS2 after switch 75 closes
After , the switch 14-2 is closed and the unity gain buffer amplifier 1 when there is a signal charge and a smear charge.
A DC output voltage of 2 is held at one electrode of the memory capacitor 13-2. Thereafter, the switch 16 is closed, and the offset voltage of the output buffer amplifier 1-7 is held at the other electrodes of the memory capacitors 3-1 and 13-2.

When the horizontal scanning period begins, the signal of the unity gain buffer amplifier 12 held in each memory capacity and the DC output when there is a smear charge and when there is no signal and only a smear charge are sequentially read out. In other words, by the horizontal scanning circuit,
When a certain column (referred to as column n) is selected, the horizontal switch 6-2 and readout switch 15-2 of column n are opened, and the terminal O is opened.
UT 2 has n columns held in memory capacity 13-2.
The DC output voltage of the buffer amplifier 12 when there is a column signal is displayed. At the same time, the horizontal switch 6-1 and the readout switch 5-1 in the n+1 column are also opened, and the terminal ○U is opened.
In the TI, n is held in the memory capacity 13-1 for n+1 columns.
The DC output voltage of the buffer amplifier 12 when there is no signal charge in the +1 column is represented.

Therefore, by delaying the output voltage of terminal ○UTI by one clock and taking the difference from the output voltage of terminal ○UT2, it is possible to obtain the true signal component without mixing in the potential fluctuation of the vertical signal line due to smear charge. .

According to this example, by providing a correlated double sampling circuit for each vertical signal line 8, it is possible to obtain a signal output free from kTC noise, which is one of the main noise sources of conventional MOS solid-state image sensors. . In addition, by providing an amplifier circuit for each vertical signal line 8, the band required for the operation of the amplifier circuit can be lower than that required for the amplifier circuit of conventional elements, and this eliminates the problem of another main noise source of conventional elements. It can significantly reduce the noise of certain amplifiers. As a result, a high S/N can be achieved. Furthermore, the generation time of excess charge mixed into the signal is the time from when the self-bias switch 75 closes to when the sample-hold switch 14 closes, which can be significantly reduced compared to the conventional one horizontal scanning period. We independently read the potential fluctuation of the vertical signal line due to the smear charge and the signal charge, and
By taking the difference, a true signal without smear is obtained, making it possible to reduce smear.

By the way, in this solid-state imaging device, the preamplifier circuit 7
1. Three amplifiers are used: a unity gain buffer amplifier 12 and an output buffer amplifier 17. During the period when these amplifiers need to operate, for the preamplifier circuit 71 and the unity gain buffer amplifier 12, the DC output voltage of the unity gain buffer amplifier 12 is held in the memory capacities 13-1 and 13-2. The horizontal blanking period in which the operation is performed (1 (1) in FIG. 9; no operation is required in the period other than the fidgeting period, that is, the horizontal scanning period (H2 in FIG. 9); and the output buffer]-7 , a certain column is selected by the horizontal blanking period and the horizontal scanning circuit, and the memory capacities 13-1 and 13-2 are
The operation is necessary during the period in which the voltage held at 0UT1 and OUT2 is outputted to the terminals 0UT1 and OUT2, but the operation is not necessary during the non-selection period when no output is made during the horizontal scanning period. On the other hand, when these amplifiers are in operation, a direct current always flows from the power supply to the ground line inside the circuit. Therefore, the operation of the amplifier is a factor directly linked to the power consumption of the entire device. In the solid-state imaging device described above, the amplifier remains in operation even during a period when the amplifier is not required to operate, and no consideration has been given to power consumption.

An object of the present invention is to minimize the operating period of the preamplifier circuit, unity gain buffer amplifier, and output buffer amplifier to reduce the power consumption of the entire device.

[Means to solve the problem]

The above purpose is to introduce a means to open and close the current path from the power supply to the ground line in each amplifier (preamplifier circuit, unity gain buffer amplifier, output buffer amplifier), and synchronize the amplifier operation with the period when necessary. This is achieved by closing the current path by closing the current path, and opening the current path when no operation is required to prevent current from flowing.

[Effect]

The current path opening/closing means closes the current path of the preamplifier and unity gain buffer amplifier during the horizontal blanking period, and opens the current path during the horizontal scanning period. As a result, the power consumption during the horizontal scanning period becomes zero, making it possible to reduce power consumption. Regarding the output buffer amplifier, the current path is closed during the horizontal blanking period, and during the horizontal scanning period, the output buffer amplifier of the nth column and the n+1th column is synchronized with the time when the horizontal scanning line of the nth column is selected. Only improve to work. As a result, during the horizontal scanning period, it is possible to prevent the output buffer amplifier from consuming current in all stages, which is a wasteful operation, and to reduce power consumption.

〔Example〕

FIG. 1 shows a circuit diagram from the preamplifier 71 to the unity gain buffer amplifier output line 20 shown in FIG. 8 in a first embodiment of the present invention.

8.72, 73, 74, 75, 20, 81 in the figure. .

32, S5 are the same as those in FIG. 41°42.
43 is an MO constituting the preamplifier 71 in FIG.
4] is a driver MO8, for example PMO8, 42 is a cascade MOS, for example PMO8,
Reference numeral 43 denotes a load MO8, which can be made of NMOS, for example. Further, 44° and 45 are MOS transistors forming the unity gain buffer amplifier 12 in FIG. 8, 44 is a driver MO8, for example, PMO8, and 45 is a load MO8, for example, PMO8 can be used. 18
is an amplifier power supply line, 19 is an amplifier ground line (wire for setting the reference voltage of the amplifier), VB2°VBll is a bias voltage terminal of the preamplifier, and VB4 is a bias terminal of the unity gain buffer amplifier. 21 is a preamplifier activation switch, and 22 is a unity gain buffer amplifier activation switch, which can be composed of, for example, NMOS. In this embodiment, one MOS is set for one preamplifier. shows an example in which it is connected to terminal S5. Here, multiple MOSs are required for one preamplifier.
may be provided. The operation of this embodiment will be explained below.

When the horizontal blanking period begins, the potential of S5 becomes high, and the preamplifier activation switch 21 and unity gain buffer amplifier activation switch 22 are turned on. As a result, current flows from the amplifier power supply line 18 to the amplifier ground line 19 in both the preamplifier and the unity gain buffer amplifier, and the amplifiers become activated. When this amplifier is activated, the memory capacity 13-1 in FIG.
At step 13-2, an operation is performed in which the DC output voltage of the unity gain buffer amplifier is held.

When the horizontal scanning period begins, the potential of S5 becomes low (reference level), and the preamplifier activation switch 21 and unity gain buffer amplifier activation switch 22 are turned off. As a result, both the preamplifier and the unity gain buffer amplifier are connected from the amplifier power supply line 18 to the amplifier ground line 19.
The current path to the amplifier is cut off (ie, current no longer flows), and the amplifier becomes inactive. In FIG. 1, the preamplifier activation switch 21 and unity gain buffer amplifier activation switch 22 are introduced on the amplifier ground line side, but they may be introduced on the amplifier power supply line side. In this case, the switch is configured with PMO8, for example, and an inverting circuit is inserted between terminal S5 and the gate of the switch, so that when the potential of S5 becomes high, a reference level potential is applied to the gate of the switch, and the amplifier ground You can get the same effect as if you turned on the switch on the line side.

In this embodiment, power consumption can be reduced by providing a switch in series for each current path of each amplifier, turning it on and off, and operating each amplifier only during the horizontal blanking period.

FIG. 2 shows another embodiment of the present invention, with an eighth embodiment similar to FIG.
A portion from the preamplifier 71 to the unity gain buffer amplifier output line 20 in the figure is shown. 8.72 in the figure,
73,74,75,20°Sl,,S2,85,18,
1.9. VB2. VB8°V B4141 + 42.
43+44+45 are the same as those in FIG. The gate of the preamplifier load MOS transistor 43 is connected to V B 8 or Vs via two anti-conducting type switches driven by the inverted voltage of S5.

For example, to V B8 via PMO8 transistor 26,
For example, through the NMOS transistor 25, the reference level V
connected to s. On the other hand, the gate of the load MOS transistor 45 of the unity gain buffer amplifier is connected to VB4 or VD via a switch of the same conductivity type driven by the voltage of the terminal S5 or its inverted voltage. That is, it is connected to Vo via, for example, a PMOS transistor 46 driven by the voltage at terminal S5, and to Vaa via, for example, PMO8I-transistor 47, which is driven by the inverted voltage at terminal S5. The operation of this embodiment will be explained below.

When entering the horizontal blanking period, the potential of S5 becomes high, the output of the inverter 48 becomes low, the NMOS transistor 25 turns 0FFL, the PMOS transistor 26 turns on, and the gate potential of the preamplifier load MO8 becomes VB8. As a result, the preamplifier becomes activated. At the same time, the output of the inverter 49 also becomes low, the PMOS transistor 47 is turned on, and the PMOS transistor 46 is turned off, so the gate potential of the load MO8 of the unity gain buffer amplifier becomes VB4, and the unity gain buffer amplifier is activated. Become.

When entering the horizontal scanning period, the potential of 85 is low (standard level)
As a result, the output of the inverter 48 becomes high, the NMO8I- transistor 25 turns ON, and the PMO3+- transistor 26 turns OFF, so the gate potential of the preamplifier load MO8 becomes the reference level Vs, and this load MOS, which is NMO8,
The transistor is turned off. As a result, amplifier power line 1
8 to the amplifier ground line 19 is cut off,
No current flows and the preamplifier becomes inactive. At the same time, the output of the inverter 49 becomes high, and the PMOS transistor 47 turns OFF'' FL, and the PMOS transistor 46 turns ON, so the gate potential of the load MO8 of the unity gain buffer amplifier becomes VD, and this load MOS transistor, which is PMO8, turns OFF. F. As a result, the current path from the amplifier power supply line 18 to the amplifier ground line 19 is cut off, and the unity gain buffer amplifier enters a ruthless state.The bias to the load MOS transistor is switched by 2. There are two cases: one switch is of the anti-conductivity type and the input to its gate is the same pulse, and the other is the case where two switches are of the same conductivity type and the input to the gate is an inverting pulse. M.O.S.
They may be used appropriately depending on the polarity of the transistor and the magnitude of the bias voltage. In this example,
By changing the bias voltage of the constant current load MO8 of each amplifier, each amplifier is activated only during the horizontal blanking period. As a result, the MO
There is an advantage that the number of S transistors is reduced, and the effects of noise generated by the activation switch transistor shown in FIG. 1 and voltage drop inside the transistor are also reduced.

FIG. 3 shows another embodiment of the present invention, and similarly to FIGS. 1 and 2, it shows a circuit diagram from the preamplifier 71 to the unity gain buffer amplifier output line 20. 8.72 in the figure
, 73, 74, 75, 20°SL, 82. S5,18+
1.9. VB8. VB4 has the same reference numeral as in FIG. Reference numeral 27 denotes an amplifier activation switch, for example, one piece is inserted between the amplifier ground line 19 and the terminal Vs (ground level) of the preamplifier and unity gain buffer amplifier (more than one may be provided), for example. NMO3I-
It is composed of a transistor, and its gate is connected to, for example, S5. The operation of this embodiment will be explained below.

When entering the horizontal blanking period, the potential of 85 becomes high,
The amplifier activation switch is turned on, and the preamplifier and unity gain buffer amplifier are activated.

When entering the horizontal scanning period, the potential of 85 is low (standard level)
As a result, the amplifier activation switch becomes OFF, the current paths of the amplifier power supply line 18 and amplifier ground line 19 of the preamplifier and unity gain buffer amplifier are cut off, and the two amplifiers become inactive. In this embodiment, the circuit shown in FIG. 1, which has one activation switch for each amplifier, can be made to function with just one switch.

Although one amplifier activation switch is shown in FIG. 3, two amplifier activation switches may be installed, one on the preamplifier side and one on the unity gain buffer amplifier side. . Furthermore, although the amplifier activation switch is introduced between the amplifier ground line 19 and the terminal Vs in FIG. 3, it may be introduced between the amplifier power supply line 18 and the terminal Vo. In this case, in the same way as the activation switch shown in FIG. 1 was introduced on the amplifier power supply line 18 side, the switch is formed of, for example, a PMOS transistor, and an inverter circuit, for example, is introduced between gate 1 and gate 85.

This makes it possible to function with just one switch instead of one activation switch for each amplifier.

FIG. 4 shows still another embodiment of the present invention, in which the unity gain buffer amplifier output line 20 of FIG. 8 is connected to the horizontal scanning circuit 5.
FIG. 20°14.13,10,1 in the diagram
5,16,5,6,9゜18.19. S3. S4. S5
, 0tJT1, and 0UT2 have the same symbols as in FIG. 5
1.51 is a MOS transistor constituting the output buffer amplifier 17 in FIG. 8, and 50 is a driver MO.
8, for example, NMO8, 51 is a load MO8, for example, PNO
It is 3. VB4 is a bias terminal of the output buffer amplifier, and is shared with the bias terminal VB4 of the unity gain buffer amplifier. 30 is a hold capacitor discharge switch, 31 is a gate voltage hold capacitor, 32 is an output buffer amplifier activation switch, and 33 is a hold capacitor charge switch, which is composed of, for example, NMO8, and one each for one output buffer amplifier.
There are two or more of them (or more than one of them may be provided).

Further, the gate of the hold capacitor discharge switch 30 in the n column is connected to the horizontal scanning line in the n+1 column, and the gate of the hold capacitor charge switch 33 is connected to the horizontal scanning line in the n-1- column. Furthermore, all gates of the output buffer amplifier activation switch 32-1 are connected to the terminal S5. The above configuration is an example, and there are various other configurations and connections. The operation of this embodiment will be explained below.

(2]) When entering the horizontal blanking period, the potential of S5 becomes high and the output sofa amplifier activation switch 32-1 is turned on. As a result, current flows from the amplifier power supply line 18 to the amplifier ground line 1-9 in the output sofa amplifier, and the amplifier becomes activated. With this output buffer amplifier activated, an operation is performed in which the DC output voltage of the unity gain buffer amplifier is held in the memory capacitors 13-1 and 13-2 in FIG.

When the horizontal scanning period begins, an operation is performed in which the DC outputs of the unity gain buffer amplifiers held in each memory capacity when there is a signal and when there is no signal are sequentially read out.

First, the potential of S5 is low (reference level), the output buffer amplifier activation switch 32-1 is set to 0FFL, and all output buffer amplifiers are temporarily inactivated. Thereafter, when the horizontal scanning line in the first column is selected by the horizontal scanning circuit 5, the gate voltage of the hold capacitance charge switch 33 of the output buffer amplifier in the second column increases and the switch 33
is in the ON state. At this time, the hold capacitor discharge switch 30 is in the OFF state because the third horizontal scanning line is not selected, so the gate voltage is at the reference level. As a result, gates 1 to 1 of the output buffer amplifier activation switch 32-2 have the potential of Vo, and the output buffer amplifiers in the second column are activated. At the same time as the above operation, the horizontal switch 6-1 and readout switch 15-1 in the second column are set to 0FFL, and the unity gain buffer amplifier when there is no signal in the second column held in the memory capacity 13-1. The DC output voltage is represented at terminal OtJ T 1. Similarly, when the horizontal scanning line in the second column is selected, the output buffer amplifier in the third column is activated, and the unity gain when there is no signal held in the memory capacitor 13-1 in the third column is activated. The DC output voltage of the buffer amplifier is at the terminal OU.
']” 1. On the other hand, the switch 33 in the second row
The gate voltage remains at Vo, and the output buffer amplifier remains activated. In this state, the second
The DC output voltage of the unity gain buffer amplifier when column horizontal switch 6-2 and readout switch] 5-2 is OFF and there is a second column signal held in memory capacity 1-3-2 is the terminal OUT. 2. Next, when the third column of horizontal scanning lines is selected, similar operations are performed in the fourth and third columns. Further, since the horizontal scanning line in the third column is connected to the gate of the hold capacitor discharge switch 30 in the second column, this switch is turned on.

At this time, the hold capacitor charge switch 33 in the second column is in the OFF state because the horizontal scanning line in the first column is already in the non-selected state. As a result, the gate of the output buffer amplifier activation switch 32-2 in the second column becomes the reference level, this switch is turned off, and the output buffer amplifier in the second column is connected to the amplifier power line 1-8 and the amplifier ground line 19. The current path is cut and the state becomes inactive.

In this embodiment, an output buffer amplifier activation switch is provided in series with the current path of each amplifier, and is synchronized with the selection of the horizontal scanning line, and activates the output buffer amplifier of the n+1 column when the n column is selected. The output sofa amplifier of the n-1 column is deactivated.

As a result, the output buffer amplifier is activated because
This is equivalent to 2 clocks of horizontal scanning, and it is possible to reduce power consumption. In the above embodiments, the case where a signal of one pixel in the vertical direction is read out has been described. On the other hand, in single-chip color solid-state image sensors, there is a vertical 2-image-M readout method that performs interlace scanning as a method of achieving high resolution and high image quality. Requires capacity. In the present invention, this 71
To realize the formula, for example, n
When a column is selected, the output buffer amplifiers in the n+2 column are activated and the output buffer amplifiers in the n-1 column are inactivated. As a result, the output buffer amplifier is in the active state for three clocks of horizontal scanning, making it possible to reduce power consumption.

FIG. 5 is a diagram showing still another embodiment of the present invention, and similarly to FIG. 4, it is a diagram showing from the unity gain buffer amplifier output line 2o of FIG. 8 to the horizontal scanning circuit 5. 20 in the diagram
．． 14, 13, 10, 15° 1.6, 5, 6, 9, 18
, 19, 83. S4゜S5,0UTI,○U R2,V
H2 is the same as in Figure 8, 30, 31, 33.5
0 is the same as in FIG. Reference numeral 52 denotes a load MO8 of the output buffer amplifier, which is composed of, for example, an NMO8, and in this circuit also serves as an output buffer amplifier activation switch. Load MO8) - The gate of transistor 52-1 is connected to VH2 or Vs via two anti-conductivity type switches driven by the inverted voltage of S5. That is, for example, to VH2 via the PMOS transistor 53,
It is also connected to the reference level Vs via, for example, an NMOS transistor 54. The operation of this embodiment will be explained below.

When entering the horizontal blanking period, the potential of S5 becomes high, the output of inverter 55 becomes low, and the gate potential of load MO852-1 becomes VH2. As a result, the output buffer amplifier becomes activated.

When the horizontal scanning period begins, the potential of S5 becomes low (reference level) and the output of inverter 55 becomes high, so that the load MO
The gate potential of the circuit 352-1 becomes the reference level Vs, and the entire output buffer amplifier is temporarily inactivated. Next, this circuit also synchronizes with the selection of horizontal scanning lines as in the case of Fig. 4, and when column n is selected, the output buffer amplifier of column n+1 is activated, and the output buffer amplifier of column n-1 is activated. A series of operations is performed to deactivate the amplifier. As a result, the cover amplifier is active for two clocks of horizontal scanning, allowing for lower power consumption.

The feature of this embodiment is that the load MO8 of the output buffer amplifier is used as the output buffer amplifier activation switch, and the number of component MOS transistors is smaller than that in FIG. It has the advantage of being less affected by internal voltage drops.

FIG. 6 is a diagram showing still another embodiment of the present invention, and FIG.
9 is a diagram showing from the unity gain buffer amplifier output line 20 of FIG. 8 to the horizontal scanning circuit 5 similarly to FIG. 5. FIG.

In the figure 20.1.4, 13°10.15, 16, 5, 6,
9, 18, 19°S3. S4. S5,0UTI,0UT
2. VH2 is the same as in FIG. 8, and 50,3] is the same as in FIG. Reference numeral 30 denotes a hold capacitor discharge switch, which is composed of, for example, NMO8, and all gates of 30-1 are connected to terminal S6.

33 is the hole 1~capacity charge switch, for example NMO
8, and all gates of 33-2 are connected to terminal S5. Reference numeral 52 denotes an output buffer amplifier load MO8, which is composed of, for example, an NMO8. The operation of this embodiment will be explained below.

When entering the horizontal blanking period, the potential of 85 becomes high and the hold capacitor charge switch 33-2 is turned on, so that the potential of output sofa amplifier load MO852 becomes VH2. As a result, the output buffer amplifier becomes activated.

When the horizontal scanning period begins, the potential of S5 becomes low (reference level) and the hold capacitor charge switch is turned off. At this time, the gate potential of the output buffer amplifier load MO352 is held at VH2 by the gate voltage halt capacitor 31, so the output buffer amplifier is in an activated state. Subsequently, the potential of S6 becomes high, the hold capacitor discharge switch 3o-1 is turned on, and the gate potential of the output buffer amplifier load MO352 becomes the reference level, so the output buffer amplifier load MO8 is turned off. As a result, the output buffer amplifier becomes inactive. Next, the potential of 86 becomes low and the hold capacitor discharge switch 30
After -1 reaches 0FFL, the operation of the horizontal scanning circuit is started. The subsequent operation is similar to the case of FIG. 4, in synchronization with the selection of the horizontal scanning line, when column n is selected, the output buffer amplifier of column n+1 is activated, and the output buffer amplifier of column n-1 is activated. A series of operations is performed to deactivate the amplifier. As a result, the output buffer amplifier is in the active state for two tallocks of horizontal scanning, and power consumption can be reduced. In addition, hold capacitance discharge switch 30-1
- is a switch provided to temporarily deactivate the output buffer amplifier before operating the horizontal scanning circuit;
The pulse applied to S6 is generated once from when S5 becomes low until the first horizontal scanning line is selected. The feature of this embodiment is that since no switch is added in series to the current path of the output buffer amplifier, the current path of the output buffer amplifier is the same during the horizontal blanking period and the horizontal scanning period, and the output buffer amplifier is It has the advantage of keeping the characteristics constant.

The operation of the embodiment of the circuit of the present invention has been explained above using FIGS. 1 to 6. However, when configuring the entire circuit of a solid-state image sensor, The same effect can be obtained no matter how the combinations shown in the figure are used, and lower power consumption can be achieved.

Furthermore, although the above embodiment has been explained using an MO8 type image sensor as an example, the present invention is applicable to a CID type image sensor ((, harg
e Injectj, on-view device), or bipolar transistor, junction type effect transistor, ST
It goes without saying that the present invention can be applied in the same manner as the above-described embodiment to an image sensor configured with a static induction transistor (electrostatic induction transistor) or the like.

Let P a , P b , and P c be the power consumed by each preamplifier circuit, unity gain buffer amplifier, and output buffer amplifier within a unit time, respectively.

Also, the horizontal blanking period is set to 81. Set the horizontal scanning period to H2
If Ht +82 is one cycle of horizontal operation,
] When three amplifiers are in continuous operation between cycles, the power P consumed by each set of three amplifiers is expressed by the following equation (1).

P= (H1+H2,) Pa+ (HI+T-
12,) Ph+ (t1x+Hz) Pc
-(]) The above current circuit opening/closing stage is T-I for the preamplifier circuit and unity gain buffer amplifier.
Close the current path with + and open the current path with H2. As a result, the power consumption in H2 becomes O, and the power consumption P can be reduced to P' in the following equation (2).

P' = HIPa + HJ, Pb + (Hz + Hz) Pc
-42) In addition, in the output buffer amplifier, the current circuit opening/closing means described in "2" operates in synchronization with the time t when the horizontal scanning line of the n column is selected, and only the output buffer amplifiers of the n column and the η+1 column operate. work like that. As a result, the power consumed per output buffer amplifier in the horizontal scanning period H2 becomes 2tPc, and the power consumed in one cycle of horizontal operation can be reduced to P' in the following equation (3).

P”=HIPA+HIPb+(H1+2t)Pc
(:()Here, in the NTSC system, one cycle time of horizontal operation T(s + H2 is 63.5 microseconds,
Operating conditions of conventional embodiment: H1-9 microseconds, H2=5
Comparing the effects of the present invention when operating at 4.5 microseconds t - several tens of nanoseconds, the power consumption P in the conventional technology is P''63, 5 P a + 63, 5 P b
+ 63, 5 Pc, and after applying the present invention *
The power p rr is P”= 9 Pa+ 9 Pl, + (
9+2t) Pc, so according to this embodiment, power consumption can be reduced to about one-seventh.

〔Effect of the invention〕

According to the present invention, there is an effect that the power consumption of the entire device can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of a solid-state imaging device according to the present invention from a preamplifier to a unitary-key buffer amplifier output line, and FIG. 2 shows another embodiment of a solid-state imaging device according to the present invention. 3 is a circuit diagram showing still another embodiment of the solid-state imaging device according to the present invention, and FIG. 4 is a diagram showing the solid-state imaging device according to the present invention from the unity gain buffer amplifier output line to the horizontal scanning circuit. FIG. 5 is a circuit diagram showing another embodiment of the solid-state imaging device according to the present invention, and FIG. 6 is a circuit diagram showing still another embodiment of the solid-state imaging device according to the present invention. 7 and 8 are circuit configuration diagrams of a conventional solid-state imaging device, and FIG. 9 is a diagram showing drive pulse timing of the element in FIG. 8. DESCRIPTION OF SYMBOLS 1... Photoelectric wave conversion element, 2... Vertical scanning circuit, 3... Vertical gate line, 4... Vertical switch, 5... Horizontal scanning circuit, 6... Horizontal switch, 7... External amplifier, 8... Vertical signal line, 9...Horizontal signal line, ]O...Horizontal scanning line,
2... Unity gain buffer amplifier, 13... Memory capacity, 14 Sample hold switch, 5. Signal readout switch, 16. Off cell 1 to cancel switch, 17. Output buffer amplifier.

Claims (1)

[Claims] 1. Photoelectric conversion elements arranged two-dimensionally on the same semiconductor substrate, a vertical scanning circuit and a horizontal scanning circuit for selecting the photoelectric conversion elements, and a plurality of signal lines for reading signals from the photoelectric conversion elements. In a solid-state imaging device consisting of
An amplifier provided for each signal line detects and amplifies potential fluctuations of the signal line, and when the amplified outputs are sequentially selected and read out by the horizontal scanning circuit, an activated state or a non-activated state is selected for the amplifier. A solid-state imaging device characterized by being provided with means.