JPH01276349A - Disk cache system - Google Patents

Abstract

PURPOSE:To improve the cache hit rate and the directory checking speed by checking the directories according to the priority order shown by the priority degree information and selecting the entry in a directory memory having the lowest priority degree as an object of replacement in case a cache mistake is decided. CONSTITUTION:The priority degree information on the data blocks stored in a cache data memory 27 in response to the directory information registered in a directory memory 28 is added to said directory information. Then the directories are checked by reference to the priority order shown by the priority degree information which is received when a disk access request is given from a host device. In case the memory 28 includes no idle entry, the entry where the directory information including the information of the lowest priority degree is registered is selected as an object of replacement. Thus it is possible to improve the cache hit rate and the directory checking speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [One Object of the Invention] (Industrial Application Field) The present invention relates to a disk cache system including a cache data memory in which a copy of some data of a disk device is placed.

(Prior Art) Generally, in this type of disk cache system, a directory memory has a plurality of entries for registering directory information including disk address information indicating data blocks (disk blocks) stored in the cache data memory. is provided. For example, when a disk read is requested from a host device, the disk controller first refers to each entry in the directory memory in order, starting from the first entry, and registers directory information including disk address information corresponding to the requested disk access destination. Search for entries that are

If the disk controller is able to find the target entry, it reads the data block in the cache data memory corresponding to the entry and transfers it to the host device.

On the other hand, in the case of a cache miss where the target entry could not be found, the entry to be replaced is selected from among the entries in the directory memory, and the disk corresponding to the disk access destination requested for this selected entry is Register directory information including address information. The disk controller also accesses the disk device, reads the block corresponding to the requested access destination, stores it in the cache data memory in correspondence with the registration entry of the directory information, and sends the requested data to the host device. Forward. To select the entry to be replaced above, use LRU (1, east Recen
tly Used) method is applied.

(Problem to be Solved by the Invention) As mentioned above, in conventional disk cache systems, the reference order of each entry in the directory memory is fixed, so the time required for directory checking is random regardless of the intended access destination, resulting in slow speed. Access to disk blocks that do not require processing is performed at high speed,
There has been a problem in that access speeds that meet the needs cannot be achieved, such as slow access to disk blocks that require high-speed processing. In addition, in conventional disk cache systems, entries to be replaced are selected using the LRU method, so even if the disk blocks require high-speed processing, those that are accessed infrequently are evicted from the cache data memory, making it difficult to increase speed. There was also the problem of not being able to meet the demands of the government.

Therefore, an object of the present invention is to improve the cache hit rate and directory check speed when a disk access request is made for a data block that requires high-speed processing.

[Configuration of the Invention (Means for Solving the Problems) This invention provides a method for determining the priority of data blocks stored in the cache data memory in accordance with directory information registered in the directory memory of a disk cache system. (=I), and when a disk access request including priority information is given from the host device, each entry in the directory memory is arranged in the order of priority indicated by the priority information in the same entry. As a result of this check, if the directory information needs to be registered and there are no free entries in the old directory memory, the day left directory containing the lowest priority information is re-checked. The present invention is characterized in that directory information including priority information given from a host device is registered for entries in the directory check in which information is registered.

(Function) According to the above configuration, each entry in the directory memory is referenced in the priority order indicated by the priority information notified at the time of a disk access request from the host device, so the data block with the highest priority is accessed. In some cases, high-speed directory checking becomes possible. In addition, if there are no free entries in the directory memory, the entry in the directory memory in which the directory information containing the lowest priority information is registered will be selected as the replacement target entry, so the data with the highest priority will be replaced. There is no risk that the block will be evicted from the cache data memory, and the cache hit rate when a disk access request is made for this type of data block is improved.

= 6- (Embodiment) FIG. 1 shows a block configuration of a disk cache system according to an embodiment of the present invention. In the figure, 10 is a disk device, for example a magnetic disk device, and 20 is a magnetic disk control device for accessing the magnetic disk device 10 in response to a disk access request from a host device (not shown).

The magnetic disk control device 20 is a hard disk controller (hereinafter referred to as IDC) 2 that controls the magnetic disk device 10, and is a first-in, first-out type hard disk controller (hereinafter referred to as IDC) 2] that controls the magnetic disk device 10. Buffer (hereinafter referred to as FIFO buffer) 22, interface with host device (host interface) 2
3, a microprocessor 24 that controls the entire magnetic disk control device 20, and an internal lotus 25.

The magnetic disk control device 20 stores a disk address (consisting of a head address, cylinder address, and sector address) indicated in a disk access request from a host device, or a disk address register (hereinafter referred to as D) held therein.
(referred to as AR) 26, a copy of some data of the magnetic disk device 10 is stored in a cache data memory 27 in which data blocks of a predetermined size (here, one track) are stored, for example. It has a directory memory 28 having a plurality of entries in which directory information of data blocks is registered. The directory information registered in this entry in the directory memory 28 includes disk address information ADR indicating the position of the corresponding data block on the magnetic disk device 10 (for example, consisting of a head address and a cylinder address), and indicating the priority of the block. It includes priority information P1 and next pointer information NP for specifying an entry having priority information P having the next highest priority after the corresponding entry. The priority information P is given by the host device when the host device requests disk access.

The magnetic disk controller 20 further includes a cache controller 2.
It has 9. The cache control unit 29 controls the directory memory 2 at the time of a disk access request from the host device.
8, an access function that accesses the cache data memory 27 according to the directory check result, and a directory check function that performs a directory check by referring to each entry of 8 in the order of priority indicated by the priority information P in the same entry; an access function that accesses the cache data memory 27 according to the directory check result; It has a direct information registration function that selects one of the entries and registers the direct information.

Next, the operation of the configuration shown in FIG. 1 will be explained using disk read as an example. First, it is assumed that a disk access request indicating a disk read is given to the magnetic disk control device 20 from the host device. This disk access request includes commands specifying disk read/write, etc., disk address (consisting of head address, cylinder address, and sector address), and well-known information such as size.
Contains priority information. This priority information is used by the host device (software processing) for accessing frequently used data blocks, or for accessing data blocks that are infrequently used but require high-speed processing (high-speed access). It is now set as a high priority.

A disk access request from the host device is transmitted to the microprocessor 24 via the post interface 23. The microprocessor 24 issues a seek command and sets it in the IDC 21 in accordance with a disk access request from the host device.

Thereby, the IDC 21 controls the magnetic disk device 10 to seek the designated track (cylinder). The microprocessor 24 also sends the requested disk address to the DAR2G.

After that, the cache control unit 29 is activated to perform the directory check cycle described below.

When the cache control unit 29 is activated by the microprocessor 24, it first refers to the entry with the highest priority indicated by the priority information P in each valid entry in the directory memory 28. In this embodiment, the cache control unit 29 is provided with a pointer (not shown) (highest priority entry pointer) pointing to the entry with the highest priority indicated by the priority information P. Therefore, the cache control unit 29 first refers to the entry in the directory memory 28 pointed to by the highest priority entry pointer.

The capture control unit 29 compares the disk address information ADR of the referenced entry contents with a predetermined field of the disk address held in the D A R2G (here, a concatenated address of the head address and cylinder address), and determines whether they match. A directory check is performed to determine the presence or absence of a cache hit. If a match is not detected, the catch control unit 29 searches the end of the directory memory 28 pointed to by the next pointer information NP of the referenced entry contents (that is, the priority information P with the next highest priority is set). Check the directory in the same way as before.

The cache control unit 29 performs the above directory check cycle based on the disk address information A in the reference entry.
This process is repeated until a match between the DR and the above-mentioned I/Response from the DAR2G is detected and a cash hit is determined. However, an entry for which a null value is set in the next pointer information NP indicating that there is no subsequent entry.
(In other words, the entry with the lowest priority indicated by the priority information P)
If no match is detected even after proceeding to the directory check targeting , the cache control unit 29 determines a cache miss and ends the directory check cycle.

When the cache control unit 29 completes the directory check cycle, it notifies the microprocessor 24 of the result (cache hit/cache miss) and performs the following operations.

First, when a cache hit is determined in a state where a disk read is requested as in this embodiment, the cache control unit 29 controls the cache data memory 2 corresponding to each entry in the directory memory 28 on a one-to-one basis.
A well-known read operation is performed on the block in the cache data memory 2 which corresponds to the entry in the directory memory 28 that is the target of the cash hit determination. The data read from the cache data memory 27 by this read operation is temporarily stored in the FIFO buffer 22 via the internal bus 25, and transferred to the host interface (as much data as requested by the host device) by well-known transfer control. It is transferred to the host device at 23 Kyozan.

On the other hand, if it is determined that a disk read is requested and a disk read is requested, the cache control unit 29 reads the same entry if there is a free entry in the directory memory 28, or executes the directory check cycle if there is no free entry. The last referenced end (the end with the lowest priority indicated by the priority information P) is created as a new directory information registration target entry (replacement target entry).
Select as. Then, the cache control unit 29 controls the DA
The linkage of the head address and cylinder address from R2G is disk address information ADR, and the priority information received from the host device by the microprocessor 24 is priority information P.
It is registered in the selected entry in the cache control unit 29.

At this time, the cache control unit 29 performs the following operation based on the priority indicated by the priority information from the host device and the priority indicated by the priority information P in each entry registered in the directory memory 28. .

First, if the priority is lower than either the priority indicated by the former (priority information from the host device) or the latter (priority information P in each entry registered in the directory memory 28), the cache The control unit 29 sets the next pointer information NP of the selected entry to a null value. Further, if the priority indicated by the former is higher than either of the priorities indicated by the latter, the cache control unit 29 sets the next pointer information NP of the selected entry to point to the previous highest priority entry, In addition, the highest priority entry pointer is updated to point to the selected entry, and the next pointer information NP of the lowest priority entry at that time is set to a null value. Further, if the priority indicated by the former or the priority indicated by the latter is higher than the lowest priority and lower than the highest priority, the cache control unit 29 transfers the next pointer information NP of the selected entry to the next priority entry. and the next pointer information N of the entry with the next lowest priority after the former.
Update P to point to the selected entry and also update the next pointer information NP of the entry with the lowest priority at that point.
Let be a null value. As described above, the valid entries in the cache control unit 29 including the selected entry are correctly linked in order of priority by the next pointer information NP.

On the other hand, the microprocessor 24
When notified of a cache miss from the HDC 21, the HDC 21 causes the disk read from the track (data block) on the magnetic disk device 10 that was being sought. The data block read from the magnetic disk device]O by this discrete is stored in the block of the cache data memory corresponding to the entry in the directory memory 28 selected above, and (as much as the data requested from the host device) is stored in the cache data memory block. Interf-1
5 = Transferred to post device via Ace23.

In the above embodiment, the valid entries in the cache control unit 29 are linked in order of priority by the next pointer information NP, and the cache control unit 29 is linked by the next pointer information NP.
We have explained the case where each entry can be referenced in the order of priority by tracing the directory information, or the registered entries of the directory information are managed so that the order of the entries in the directory memory 28 matches the order of priority. You can. However, in this method, the registered directory information is rearranged every time a new directory information registration operation occurs. In addition, in the above embodiment, 1
We have explained the case where the data block corresponds to 1 track, but for example] data block corresponds to 2" (n is 0
The above integer) sectors can also be applied by changing the configuration of the disk address information ADR. Furthermore, even when one data block is not a fixed size, the disk address information ADR is the disk address (consisting of head address, cylinder address, and sector address) from the host device, and the size information is added to the directory information, and the corresponding data block is This can be applied by adding (=I) pointer information to the cache data storage location in the memory.

[Effects of the Invention] As detailed above, according to the present invention, a directory check is performed by referring to each entry in the directory memory in the priority order indicated by the priority information notified at the time of a disk access request from the host device. Therefore, when accessing a data block with a high priority, a high-speed directory check is possible. In addition, if a cache miss is determined by the directory check, the entry in the directory memory that has the lowest priority information set is selected as the replacement target entry, so the data block with the highest priority is cached. There is no fear that the data block will be evicted from the data memory, and the cache hit rate when a disk access request is made for this type of data block is improved.

That is, according to the present invention, high-speed processing is required = 1
7- The cash hit rate and directory check speed when requesting disk access to a data block are improved, making it possible to access this type of data block at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a disk cache system according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 10... Magnetic disk device, 20... Magnetic disk control device, 24... Microprocessor, 27... Cache data memory, 28... Directory memory,
29... Cache control unit. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] In a disk cache system equipped with a cache data memory in which a copy of some data of a disk device is placed, disk address information indicating a data block stored in the cache data memory and a priority indicating the priority of the block. A directory memory having multiple entries for registering directory information including information, and when a disk access request including the above priority information is given from the host device, each entry in the directory memory is assigned the above priority among the same entries. a directory checking means for checking whether the data to be accessed on the target disk exists in the cache data memory by referring to the order of priority indicated by the priority information; and an entry in the directory according to the check result of the directory checking means. and a directory registration means for registering the directory information including the priority information from the host device, and the directory information registration means registers the directory information having the lowest priority when there is no free entry in the directory memory. A disk cache system characterized in that the entry in which the directory information including priority information is registered is set as a new entry to be registered.