JPH01265609A - Pseudo random number generator - Google Patents

Abstract

PURPOSE:To output a pseudo random number with simple constitution by using a shift register having a feedback circuit so as to generate a numeral being a base of a random number at each prescribed interval, extracting the signal by a random number request signal, storing part or all bits into a register and outputting the result. CONSTITUTION:A shift pulse is inputted to shift registers 11, 12, 13 and 14 from a shift clock generating circuit 18 at a prescribed time interval. Thus, the shift register is shifted through a feedback circuit comprising exclusive OR circuits 15, 16 and 17 and the output is an M series code whose level is varied at a prescribed time interval. When a random number request signal is generated, the output value of the low-order 8-bit of the shift registers 11, 12 is stored by the register 19 to form a random number output. Since the shift register in use has 12bits, the low-order 8-bit is outputted at the same probability for the value to be taken and a random series with high uniformity is obtained.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a device for executing probabilistic models, staining, etc., a communication control device for realizing a protocol using random numbers, and a cryptographic generation device using random numbers. - Placed.

This invention relates to a pseudorandom number generator used in game machines and the like.

(Prior art) Conventionally, this type of pseudo-random number generator
It is configured as shown in FIG. 3 (described in Japanese Patent No. 846). In FIG. 3, 31 is a self-running counter that increases the output value at fixed time intervals, and 32 is a free-running counter 31.
33 is a multiplier, and 34 is a register that stores the output of the multiplier 33 and outputs it as a random number.

Next, the operation of the above conventional example will be explained. In FIG. 3, the output value of the free-running counter 31 always increases at regular intervals regardless of external signals. When a random number request signal is generated, the value of the free-running counter 31 at that time is stored in the intermediate bit position of the parameter register 32. The most significant bit and the least significant bit of the parameter register 32 are always fixed at 1. The output of the parameter register 32 including the most significant bit and the least significant bit fixed to 1 is input to a multiplier 33, where the multiplication output is multiplied by the fed back value.

As a result of the multiplication process, the output value of the multiplier 33 is stored in the register 34, and at the same time is fed back to the input of the multiplier 33 to be used when generating the next random number request signal. The multiplication result stored in the register 34 becomes a random number output.

In this way, even with the above-mentioned conventional pseudo-random number generator.

If the random number request signal is generated at a time interval that is sufficiently larger than the time interval at which the output value increases, it is possible to generate a random number sequence that approximates natural random numbers.

(Problems to be Solved by the Invention) However, in the above-mentioned conventional pseudo-random number generator, random numbers are generated by a free-running counter and a multiplier;
The problem was that a large circuit was required. 1 more
Since complex processing such as multiplication is performed, there is a problem in that there is a considerable time delay between the generation of the random number request signal and the output of the random number. The present invention is intended to solve these conventional problems, and aims to provide an excellent pseudorandom number generation device that has a simple configuration and can extract random numbers without time delay.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a shift register that includes a feedback circuit and generates an M-sequence code.

Shift clock generating means for generating shift pulses at regular time intervals to change the output value of the shift register;
When a random number request signal is generated, the shift register stores some or all of the bits output from the shift register at that time, and outputs the contents as a random number.

(Function) The present invention has the following effects due to the above configuration. In other words, when the shift clock generating means generates shift pulses at regular time intervals, the shift register that includes a feedback circuit and constitutes an M-sequence code generator shifts, so that all values other than those in which all bits are 0 are shifted. is cursed at the same rate as the output of the above shift register. , when a random number request signal is generated, some or all of the bits output from the shift register at that time are stored. The memory contents are the output of the shift register sampled at the time the random number request signal was generated, so
It can be output as a random number that approximates a natural random number.

Furthermore, since the random numbers are generated using a simple configuration using a shift register, it has the advantage that it can be realized with a small circuit.

(Embodiment) FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, reference numerals 11, 12, 13 and 14 are shift registers, and an M-sequence generator is constituted by a feedback circuit consisting of an exclusive OR circuit 15, 16 and 17.

18 is a shift clock generation circuit that generates shift pulses at regular time intervals, and 19 is a register.

Next, the operation of the above embodiment will be explained. In the above embodiment, shift pulses are input from the shift clock generation circuit 18 to the shift registers 11, 12, 13, and 14 at regular time intervals. For this reason, the exclusive OR circuit 15.
The shift registers 11, 12, 13, and 14 are shifted through the feedback circuit constituted by 16, 17, and the output of the shift register becomes an M-sequence code that changes at regular time intervals. When a random number request signal is generated, the output value of the lower 8 bits of the shift registers 11 and 12 at that time is stored in the register 19 and used as a random number output.

In this way, according to the above embodiment, a 12-bit shift register is used to obtain an 8-bit random number output, so the lower 8 bits can take on all possible values, including a value in which all bits are O. can be output with the same probability, and the random number output that is the result of sampling it at the time when the random number request signal is generated can be a highly uniform random number sequence. Further, according to the above embodiment, since the output of the lower 8 bits of the output of the 12-bit shift register has a property close to a uniform random number, if the input interval of the shift pulse does not become larger than the generation interval of the random number request signal, For example, it has the advantage that it is not necessary to reduce the input interval of shift pulses too much.

FIG. 2 shows another embodiment of the invention.

In FIG. 2, 21 is a shift register, 22.23.24 is an exclusive OR circuit, 25 is a shift clock generation circuit, and 26 is a register.

In this embodiment, a simple feedback type M-sequence generator is constructed using an 8-bit shift register and three exclusive ORs. Therefore, the 8-bit shift register has the effect that values other than values in which all bits are 0 can be output with the same probability, and the circuit can be made smaller.

(Effects of the Invention) As is clear from the above embodiments, the present invention generates numerical values on which random numbers are based at regular time intervals using a shift register having a feedback circuit, and when a random number request signal is generated, samples the numerical values that are the basis of random numbers, and This method stores bits or all bits in a register and outputs them as random numbers, and has the effect of outputting pseudo-random numbers that approximate natural random numbers with a simple configuration. Also, since the output sequence of the shift register has properties similar to a uniform random number sequence, if the input interval of shift pulses to the shift register is not larger than the generation interval of the random number request signal, the input interval of shift pulses should be made too small. This has the advantage that high-speed operation of the circuit is not required. Further, since no complicated procedure is required to output random numbers, it has the advantage that random numbers can be generated immediately when a random number request signal is generated.

[Brief explanation of the drawing]

FIG. 1 is a schematic functional block diagram of a pseudorandom number generator in one embodiment of the present invention, FIG. 2 is a schematic functional block diagram of a pseudorandom number generator in another embodiment of the invention, and FIG. 3 is a conventional pseudorandom number generator. FIG. 2 is a schematic functional block diagram of a random number generator. II, 12.13.14.21...Shift register. 15, 16.17.22.23.24... Exclusive OR circuit, 18.25... Shift clock generation circuit, 1
9.26... Register, 31... Free running counter,
32...Parameter register. 33... Multiplier, 34... Register. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 1 +1. +2j3. +4・Shift register +5,16.
17... Alternative physical logic knowledge circuit diagram 2

Claims (1)

[Claims] a shift register that includes a feedback circuit and generates an M-sequence code; a shift clock generating means that generates shift pulses at regular time intervals to change the output value of the shift register; and a shift register that generates a random number request signal when the random number request signal is generated. 1. A pseudo-random number generator comprising means for storing some or all bits of a plurality of bits output from a register and outputting the contents as a random number.