JPH01265358A - Bit reversing circuit - Google Patents

Abstract

PURPOSE:To realize the fast Fourier transform with use of an inexpensive memory of small capacity by rearranging the output data of a counter in a reverse sequence of bits and reading the data stored in a prescribed address of a 1st memory means in the prescribed timing via 2nd and 3rd memory means. CONSTITUTION:The output of a counter 100 is applied to a bit reversing means 300 and the bits of the output data on the counter 100 are rearranged in a reverse sequence. Then the 1st memory means 200 supplies the data to show the output address of a selection means 700 and the data is read out of the address. While the data stored in a 2nd memory means 800 and a 3rd memory means 900 are read out in the prescribed timing decided by the output control signal of a control means 650 and written into the prescribed address. Furthermore both means 800 and 900 read the data out of the prescribed address of the means 200 in the prescribed timing decided by the output control signal of the means 650 and then write them. In such a constitution, the high-speed Fourier transform is performed by an inexpensive memory of small capacity.

Description

[Detailed description of the invention] [(Already required)] Digital signal processing processor (hereinafter referred to as DSP)
Regarding the data rearrangement (bit reverse) circuit required when performing fast Fourier transform (hereinafter referred to as FFT) in , a counter that outputs data indicating the address of the first storage means in a predetermined order, a bit reversing means that rearranges the bits of the output data of the counter in reverse order, and a comparison that compares the magnitude of the outputs of the counter and the bit reversing means. a selection means for selecting and outputting one of the outputs of the counter and the bit reversing means according to a control signal output from the control means in accordance with the output of the comparison means; and data indicating an address of the output of the selection means. a first storage means for reading out the data stored in the address in the second and third storage means at a predetermined timing determined by an output control signal of the control means, and writing the data stored in the second and third storage means in the predetermined address; The second and third storage means read and write data stored at a predetermined address in the first storage means at a predetermined timing determined by an output control signal from the control means.

[Industrial application field]

The present invention relates to an improvement of a bit reverse circuit required when performing FFT in a DSP.

At this time, there is a demand for a bit reverse circuit that performs FFT using a small-capacity, low-cost memory.

[Conventional technology]

FIG. 6 is a block diagram of a circuit configuration of a conventional example.

FIG. 7 is a diagram explaining the operation of the conventional example.

In FIG. 6, it is assumed that the counter 1 sequentially generates signal data indicating an address consisting of, for example, 3 bits. This is shown in FIG. 7 using input addresses. The input address signal is input to a random access memory (hereinafter referred to as RAM) 2, and data stored at the address indicated by the input address signal is read from the RAM 2.

On the other hand, the input address signal output from the counter 1 is input to the bit reverse circuit (hereinafter referred to as REV) 3, and
As shown in the figure, the bits are rearranged in reverse order and output. REV 3 output selection circuit (hereinafter referred to as SEL)
Add to 4. The other input terminal of SEL 4 has a DSP
(not shown), and one of them is selected and output based on a control signal from the DSP. In this case, select the output of REV 3 and add it to RAM 5. As shown in FIG. 7, when the input address to RAM 2 is, for example, "001", that is, the first address, the bit reverse address is converted to "100#," that is, the fourth address, and is input to RAM 5. .And the above-mentioned RA
The data stored at the first address of M2 is read and written to the fourth address of RAM5.

Also, the input address to RAM 2 is "100", that is, 4.
At the 4th address, the data stored at the 4th address is read. On the other hand, in the RAM 5, bits are reversed by REV 3 and "001", that is, the first address signal is input. Then, the data read out from RAM 2 and stored at the fourth address is written into the 501st address of the RAM.

Also, if the input address signal is “000”, “111”, “
010" and "101" are the same even if the bits are reversed, so the data stored in RAM 5 is written at the same address as RAM 2.

In this way, data was bit reversed.

[Problem to be solved by the invention]

However, in the above-mentioned bit reverse circuit, for example, 2N memories are required for N data, resulting in a large capacity and high cost.

Therefore, an object of the present invention is to provide a bit reverse circuit that performs FFT using a small-capacity, low-cost memory.

[Means to solve the problem]

The above problem is solved by the circuit configuration shown in FIG.

That is, in FIG. 1, 100 is a counter that outputs data indicating the address of the first storage means 2°O in a predetermined order.

300 is a bit reversing means for rearranging the bits of the output data of the counter in reverse order.

Reference numeral 600 denotes comparison means for comparing the magnitude of the outputs of the counter and bit reversing means.

Reference numeral 700 denotes a selection means for selecting and outputting one of the outputs of the counter and the bit reversing means using a control signal output from the control means 650 in accordance with the output of the comparison means.

200 inputs data indicating the address of the output of the selection means, reads out the data stored in the address, and selects the second output at a predetermined timing determined by the output control signal of the control means.
and a first storage means that reads data stored in the third storage means 800 and 900 and writes it to a predetermined address.

Reference numerals 800 and 900 denote second and third storage means that read and write data stored at predetermined addresses in the first storage means at predetermined timings determined by output control signals from the control means.

[For production]

In FIG. 1, a counter 100 outputs data indicating addresses of a first storage means 200 in a predetermined order. The bit reversing means 30 converts the output of the counter 100 into
In addition to 0, the bits of the output data of the counter are rearranged in reverse order.

Comparing means 600 compares the outputs of the counter and bit reversing means, and selecting means 700 selects one of the outputs of the counter and bit reversing means according to the output of the comparing means using the control signal of the output of control means 650. and output it.

In the first storage means 200, data indicating the address of the output of the selection means is input and the data stored at the address is read out. Further, the second and third storage means 800 are stored at a predetermined timing determined by the output control signal of the control means.
．． The data stored in 900 is read out and written to a predetermined address.

In the second and third storage means 800 and 900, data stored at a predetermined address in the first storage means is read and written at a predetermined timing determined by an output control signal from the control means.

As a result, FFT can be performed using a small-capacity, low-cost memory.

〔Example〕

FIG. 2 is a circuit configuration block diagram of an embodiment of the present invention.

FIG. 3 is a diagram illustrating the operation of the embodiment.

FIG. 4 is a time chart explaining the operation of the embodiment.

FIG. 5 is a flowchart explaining the operation of the embodiment.

The same reference numerals indicate the same objects throughout the figures.

In FIG. 2, the address signal generated by the counter 10 is connected to a comparator (hereinafter referred to as CMP) created by software.
The address signal is input to one input terminal (a) of REV 60, and the address signal is inverted by REV 30 and sent to the other input terminal (b).
) is entered. Compare the two with CMP60, and the value directly input from the counter (a) is the output value of REV30 (bl
Only when it is smaller, the output of the CMP 60 becomes "1" as shown in FIG. 4, and this output is applied to a control circuit (hereinafter referred to as C0NT) 65. This is the case, for example, when the input address shown in FIG. 3 is "001" (number 1) and the bit reverse address is "100"' (number 4). The control signal shown in FIG. 4A is then applied to 5EL70. In the first section {circle around (2)} which divides the period of "1" of the output of the CMP 60 into four equal parts, A becomes 0'', and the 5EL 70 selects and outputs the output of the counter 10.

When the above output is applied to the RAM 20, the data stored in the first address (“001” mentioned above) is read out in the RAM 20, and the pulse “0” of the output control signal B of the C0NT65 shown in FIG. Register (hereinafter referred to as REG) 80 using the rising portion to 1”
will be written to.

Next, A shown in Figure 4 becomes 1'', and 5EL70 becomes REV.
30 outputs are selected and output. As a result, the above “0”
124M20 is “100” which is bit reversed from “01”.
The data stored in the fourth address ("100") is read out, and using the rising part of the pulse of control signal C from "0" to "1" shown in FIG.
Write to G90. (section ■ in Figure 4).

Next, a control signal is applied to the gate 85 in the section 3 shown in FIG. 4, and in this section the gate 85 is turned on and becomes conductive, and the data stored in the REG 80 is read out. 4 of the RAM 20 by the control signal F shown in FIG.
written to the th address.

Next, in the section (■) shown in FIG. 4, the control signal A becomes "0", and the 5EL70 selects the output address signal of the counter 10 (in this case "001") and adds it to the l'lAM20.

At the same time, a control signal E is applied to the gate 95, the gate 95 is turned on during this period, and the data stored in the REG 90 is read out. Then, using the rising edge of the pulse of the control signal F shown in FIG.
It is written to the first address of 20.

As a result, in the RAM 20, the data of the fourth address is written to the first address (001"),
This means that the data of the first address has been written to the fourth address.

In the case where the input address shown in FIG. 3 is "011" and the bit reverse address is "110", processing is performed in the same manner as in the above case.

Incidentally, FIG. 5 shows a flowchart of the operation of the embodiment.

In this way, bit reversal of data can be performed.

〔Effect of the invention〕

As explained above, according to the present invention, FFT is performed with a small capacity,
This can be done using low-cost memory. The larger the number of input data, the greater the effect.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is a circuit configuration block diagram of an embodiment of the invention, Fig. 3 is a diagram explaining the operation of the embodiment, and Fig. 4 is a timing diagram explaining the operation of the embodiment. FIG. 5 is a flowchart explaining the operation of the embodiment, FIG. 6 is a circuit configuration block diagram of the conventional example, and FIG. 7 is a diagram explaining the operation of the conventional example. In the figure, 100 is a counter, 200 is a first storage means, 300 is a bit reverse means, 600 is a comparison means, 650 is a control means, 700 is a selection means, 800 is a second storage means, 900 is a third storage means shows. Figure 1 Single 2 Figure /l/ = 11/ O RAM2θ Hole Drilling Timer 1 Operation 2 Diagram Explaining Single Figure 3 Figure Sheep Figure 4 *A work in row f? Flowchart rod that takes off the mouth 51 troubles

Claims (1)

[Scope of Claims] A counter (100) that outputs data indicating the address of the first storage means (200) in a predetermined order, and a bit reversing means (300) that rearranges the bits of the output data of the counter in reverse order. a comparing means (600) for comparing the magnitude of the outputs of the counter and the bit reversing means; and a control signal of the output of the control means (650) according to the output of the comparing means. a selection means (700) for selecting and outputting one of the outputs; inputting data indicating the address of the output of the selection means and reading out the data stored at the address; The first storage means (reads the data stored in the second and third storage means (800, 900) at a timing and writes it to a predetermined address.
200), and second and third storage means (8) for reading and writing data stored at a predetermined address of the first storage means at a predetermined timing determined by an output control signal of the control means.
00, 900).