JPH01263728A - Microprocessor equipped with relative instructable register group - Google Patents

Microprocessor equipped with relative instructable register group

Info

Publication number
JPH01263728A
JPH01263728A JP9210688A JP9210688A JPH01263728A JP H01263728 A JPH01263728 A JP H01263728A JP 9210688 A JP9210688 A JP 9210688A JP 9210688 A JP9210688 A JP 9210688A JP H01263728 A JPH01263728 A JP H01263728A
Authority
JP
Japan
Prior art keywords
register
routine
reference pointer
registers
relative
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9210688A
Other languages
Japanese (ja)
Inventor
Naoki Shiraishi
奈緒樹 白石
Hiroshi Nittaya
洋 新田谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP9210688A priority Critical patent/JPH01263728A/en
Publication of JPH01263728A publication Critical patent/JPH01263728A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To secure a register only by the number needed with a process routine by moving a reference pointer, securing the necessary register only and defining and using the use at the relative position from the reference pointer when a new processing is started by a programmer. CONSTITUTION:In a system having N+1 registers (0 to N), when a newly used register is secured, the position of a reference pointer is moved to a register 0 side and when the register during the use is abandoned, the position of the reference pointer is moved to a register N side. A program executes a certain routine R1, at this time, the reference pointer of the register points n1, and when the routine R1 calls a routine R2, the routine R2 moves the reference pointer to n2, secures newly j2+1 registers and defines and uses registers n2 to (n2+j1); (n2+j1+1) to (n2+j2+j2); n1 to (n1+i1). When the routine of R2 is completed, the reference pointer is returned to n1 and n2 to (n2+j2) are abandoned.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は各処理ルーチンが必要とする数だけ演算用レ
ジスタ、ポインタを確保出来るとともに、ルーチン間の
パラメータ受は渡し用レジスタを任意の数だけ確保出来
る相対指示可能なレジスタ群を備えたマイクロプロセッ
サに関する。
[Detailed Description of the Invention] (Field of Industrial Application) This invention can secure as many operation registers and pointers as required by each processing routine, and can use any number of passing registers to receive parameters between routines. The present invention relates to a microprocessor equipped with a register group that can be secured and relatively designated.

(従来の技術) 従来レジスタの選択は絶対指定であるため、プログラマ
はサブ−チンコールや割り込み処理に際し、常にレジス
タの保存状態を管理しなければならなかった。そこで、
この問題を解決する方法として、複数のレジスタ群を持
ち、使用するレジスタ群を適時切シ替えるという手段が
主に用いられる。この際、ルーチン間のパラメータ受は
渡し用としてレジスタ群の一部を重複させる事もある。
(Prior Art) Conventionally, register selection is an absolute designation, so programmers must always manage the storage state of registers when performing sub-chip calls or interrupt processing. Therefore,
As a method to solve this problem, a method is mainly used in which a plurality of register groups are provided and the register group to be used is changed over at appropriate times. At this time, a part of the register group may be duplicated for passing parameters between routines.

(第2図: BLKO−BLKMはM+1組のレジスタ
群、REGI〜REGNはそれぞれのレジスタ群が選択
されている時の各レジスタの絶対位置を示す。)(発明
が解決しようとする問題点) しかしながら、上記手段では l)一つのレジスタ群の中のレジスタ数が固定でるるた
め、処理によってはレジスタが余って使用効率が悪くな
ったシ、逆に複雑な処理ではレジスタが不足する。
(Figure 2: BLKO-BLKM indicates M+1 register groups, and REGI to REGN indicate the absolute position of each register when each register group is selected.) (Problem to be solved by the invention) However, In the above means, l) Since the number of registers in one register group is fixed, there are excess registers depending on the processing, resulting in poor usage efficiency, and conversely, there may be a shortage of registers in complex processing.

2)ルーチン間のパラメータ受は渡し用レジスタ数も固
定のため、レジスタ使用時の制約となる場合が多い。
2) Since the number of registers for passing parameters between routines is fixed, this is often a constraint when using registers.

等の欠点がある。There are drawbacks such as.

(問題を解決するための手段) この発明の相対指示可能なレジスタ群を備えたマイクロ
プロセッサは、レジスタの選択を基準ポ1インタから相
対指定する手段と、処理ルーチン毎に各々基準ポインタ
を任意の位置に動かす手段とを備え、処理ルーチンが必
要とする数だけレジスタを確保できるようにした事を特
徴とする。
(Means for Solving the Problem) A microprocessor equipped with a register group that can be relatively designated according to the present invention has a means for relatively designating register selection from a reference pointer, and a means for specifying register selection relative to a reference pointer, and an arbitrary reference pointer for each processing routine. The present invention is characterized in that it is equipped with a means for moving the registers to a certain position, so that as many registers as required by the processing routine can be secured.

(作 用) プログラマは新しい処理を開始するときに、基準ポイン
タを移動させ必要分だけレジスタを確保し、基準ポイン
タからの相対位置で用途を定義し使用する。処理が終了
すると、基準ポインタを元の位置に戻し、確保したレジ
スタを放棄する。
(Function) When starting a new process, the programmer moves the reference pointer to secure as many registers as necessary, and defines and uses the registers based on the relative position from the reference pointer. When processing is completed, the reference pointer is returned to its original position and the reserved register is discarded.

(実施例) 第1図はこの発明に係るマイクロプロセッサのレジスタ
使用状態を示す図である。なお、pは基準ポインタ、D
−Nはレジスタの絶対位置、rl。
(Embodiment) FIG. 1 is a diagram showing the register usage state of a microprocessor according to the present invention. Note that p is the reference pointer, D
-N is the absolute position of the register, rl.

、r2はそれぞれルーチンR1,R2でのレジスタ使用
範囲、n1+n2は基準ポインタの指示する位置、i、
〜i3及びj、+j2はレジスタの使用数を示している
, r2 are the register usage ranges in routines R1 and R2, respectively, n1+n2 is the position indicated by the reference pointer, i,
~i3, j, and +j2 indicate the number of registers used.

図において、レジスタを°N+1本(0〜N)持つシス
テムにおいて、新しく使用レジスタを確保する時は基準
ポインタの位置をレジスタO側に、使用中のレジスタを
放棄する時は基準ポインタの位置をレジスタN側に移動
させるとする。プログラムは現在あるルーチンR1を実
行中であり、この時、レジスタの基準ポインタはnlを
指しており、このルーチンR,は n1〜n、+i、    :これからコールするルーチ
ンへ渡すパラメータ格納用のレ ジスタ n + + + r ++−n、++ 2 :このルー
チンでノワーク用レジスタ n 、 + i 2+l〜n、+i3:このルーチンを
コールしたルーチンから受は取ったパラ− メータを格納したレジスタ として使用している。
In the figure, in a system with °N+1 registers (0 to N), when securing a new register to be used, the position of the reference pointer is placed on the register O side, and when discarding a register in use, the position of the reference pointer is placed on the register side. Let's move it to the N side. The program is currently executing a certain routine R1, and at this time, the reference pointer of the register points to nl, and this routine R is set to n1 to n, +i, : register n for storing parameters to be passed to the routine to be called from now on. + + + r ++-n, ++ 2: This routine uses registers for work as n, + i 2+l~n, +i3: Used as registers to store parameters received from the routine that called this routine. .

この状態でルーチンR,がルーチンR2をコールすると
、ルーチンR2は基準ポインタを02に移し、新たにj
2+1本のレジスタを確保し、n2〜n2+j、   
 :これから(R2から更に)コールするルーチンへ渡
スパラ ーメータ格納用のレジスタ n2+ji+1−n2+j2:このルーチンでのワーク
用レジスタ 01〜nl+1.:このルーチンをコールしたルーチン
(この例の場合R+ ) から受は取ったパラ−メータ を格納したレジスタ として定義し、使用する。ここで、n1〜n 1 +1
1  にはルーチンR,からルーチンR2への入力パラ
−メータが格納されている。
When routine R, calls routine R2 in this state, routine R2 moves the reference pointer to 02 and newly
Secure 2+1 registers, n2 to n2+j,
: Register for storing parameters passed to the routine to be called from now on (from R2) n2+ji+1-n2+j2: Registers for work in this routine 01 to nl+1. : Define and use a register that stores the parameters received from the routine that called this routine (R+ in this example). Here, n1 to n 1 +1
1 stores input parameters from routine R to routine R2.

ルーチンR2は所定の処理を総て終了すると、基準ポイ
ンタをnlに戻しレジスタn2〜n2+j2を放棄する
。この時、n1〜n、十i、にはル−チンR2からルー
チンR,への出力パラ−メータが格納されている。
When routine R2 completes all predetermined processing, it returns the reference pointer to nl and abandons registers n2 to n2+j2. At this time, output parameters from routine R2 to routine R are stored in n1 to n and i.

この間、各ルーチン内では総てのレジスタは基準ポイン
タに対する相対位置で指定される。例えば、ルーチンR
,の中で MV REG 、 REG4 という命令は「レジスタn1+4の内容をレジスタn1
+2に転送する。」という事を意味する。
During this time, all registers within each routine are specified by relative positions to the reference pointer. For example, routine R
, the instructions MV REG and REG4 "transfer the contents of register n1+4 to register n1".
Transfer to +2. ” means.

上記のようなアーキテクチャ−と操作手順により、プロ
グラマはサブルーチンコールや割シ込み処理に際し、い
つも新たにレジスタを確保し定義出来るので、レジスタ
の保存状態を管理する必要はなく、また、処理ルーチン
毎に確保、定義するレジスタの数は任意であるので、レ
ジスタ定義の自由度が高く、プログラマへの負担も軽く
なる。
With the architecture and operating procedure described above, programmers can always secure and define new registers for subroutine calls and interrupt processing, so there is no need to manage the storage status of registers, and Since the number of registers to be secured and defined is arbitrary, the degree of freedom in register definition is high and the burden on the programmer is lightened.

(発明の効果) プログラマはサブルーチンコールや割シ込み処理に際し
、いつも新たにレジスタを確保し定義出来るので、レジ
スタの保存状態を管理する必要はなくなる。また、処理
ルーチン毎に確保、定義するレジスタの数は任意である
ので、複数のレジスタ群を切り替える方式に比べ、レジ
スタ定義の自由度が高く、プログラマへの負担も軽くな
る。
(Effects of the Invention) Since the programmer can always secure and define new registers during subroutine calls and interrupt processing, there is no need to manage the storage state of registers. Further, since the number of registers to be secured and defined for each processing routine is arbitrary, the degree of freedom in register definition is higher than in a method of switching between a plurality of register groups, and the burden on the programmer is reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

を示す図、第2図は従来の複数のレジスタ群を持ったシ
ステムを示す図である。 Pは基準ポインタ、0〜Nはレジスタの絶対位置、J+
12は基準ポインタの指示する位置、11〜i3及びj
、 + j2 はレジスタの使用数。
FIG. 2 is a diagram showing a conventional system having a plurality of register groups. P is the reference pointer, 0~N is the absolute position of the register, J+
12 is the position indicated by the reference pointer, 11 to i3 and j
, + j2 is the number of registers used.

Claims (1)

【特許請求の範囲】[Claims] 1、レジスタの選択を基準ポインタから相対指定する手
段と、処理ルーチン毎に各々基準ポインタを任意の位置
に動かす手段とを備え、処理ルーチンが必要とする数だ
けレジスタを確保できるようにした事を特徴とする相対
指示可能なレジスタ群を備えたマイクロプロセッサ。
1. Equipped with a means for specifying register selection relative to a reference pointer and a means for moving the reference pointer to an arbitrary position for each processing routine, making it possible to secure as many registers as required by the processing routine. A microprocessor equipped with a register group that allows relative instructions.
JP9210688A 1988-04-14 1988-04-14 Microprocessor equipped with relative instructable register group Pending JPH01263728A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9210688A JPH01263728A (en) 1988-04-14 1988-04-14 Microprocessor equipped with relative instructable register group

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9210688A JPH01263728A (en) 1988-04-14 1988-04-14 Microprocessor equipped with relative instructable register group

Publications (1)

Publication Number Publication Date
JPH01263728A true JPH01263728A (en) 1989-10-20

Family

ID=14045185

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9210688A Pending JPH01263728A (en) 1988-04-14 1988-04-14 Microprocessor equipped with relative instructable register group

Country Status (1)

Country Link
JP (1) JPH01263728A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6252637A (en) * 1985-08-30 1987-03-07 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Digital processor control

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6252637A (en) * 1985-08-30 1987-03-07 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Digital processor control

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