JPH01260930A - Decoding method for error correction code - Google Patents

Abstract

PURPOSE:To simplify the error detection calculation of <=2 symbols by selecting 2n kinds of syndromes obtained at decoding, obtaining an error location and an error pattern in n-symbol error and checking whether or not the pattern is in a prescribed relation with the remaining syndrome. CONSTITUTION:A digital signal from a recovered data input terminal 1 is processed by a syndrome arithmetic circuit 2 to obtain 6 kinds of syndromes S0-S5. An error check circuit 4 applies check of null/non null to 4 kinds of the syndromes S0-S3, and when the condition of 2-symbol error is satisfied, that is, in case of Anot equal to 0, Bnot equal to 0, Cnot equal to 0, tentative error locations i', j' and error patterns Ei', Ej' are obtained from a location polynomial. On the other hand, equation II is established in syndromes S4, S5 when a 2-symbol error takes place. Then the values i', j',Ei',Ej' are substituted in the equation II to check whether or not the result is equivalent to the case with the substitution of the values S4,S5, the the detection condition to 2-symbol error is incorporated with the condition of the values S4, S5 and the number of times of multiplication, and addition is decreased more than those of a conventional method.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for decoding an error correction code in an apparatus for recording and reproducing (or transmitting) digital signals, and in particular a decoding method for performing error detection. Regarding.

[Conventional technology]

Error correction codes are widely used in systems that handle digital data for the purpose of improving reliability. Examples include digital audio discs (CDs) and digital VTRs that record and reproduce digitized audio and video signals.

In these f211, code errors (errors) occur due to level fluctuations or lack of reproduction signals.

To correct such errors, it is first necessary to determine in advance the number of errors that have occurred in the data blocks that constitute the error correction code.

For example, Information Processing Society of Japan Journal VOL25, N(L5
.

1) 842-848's "2n and triple error correction method"
ed-8 "Decoding of Olomon Code" proposes a method of detecting errors using six parity symbols. Figure WI2 shows the above decoding procedure.

First, from the reproduced data, six types of syndromes so, s
1+S2, s3. s4. Find s5. Next, each syndrome is tested for zero or non-zero, and if all are zero, it is determined that there is no error, and if all are non-zero, it is determined that there is an error. If it is determined that there is an error, perform the following calculations.

(1) If both X and Y are zero, it is determined that there is an error of two symbols or less, and if they are non-zero, it is determined that there is an error of three symbols. If it is determined that there is an error of 2 symbols or less, the following calculation is further performed.

A-so-s2+st And if all of ABC are zero, it is one symbol error.
If it is non-zero, it is considered as a 2-symbol error.

[Problem to be solved by the invention]

On the other hand, error correction using 6al parity symbols can correct errors of 3 symbols or less.

However, in the above error detection, when an error of four or more symbols occurs, it is not possible to distinguish between an error of three symbols and an error of four or more symbols. If a three-symbol error is corrected when such a situation occurs, an error will occur due to incorrect correction.

This is because the correction error determination in 3-symbol error correction is not taken into consideration. Therefore, by limiting the correction operation to errors of two symbols or less and determining that errors of three or more symbols are uncorrectable, errors caused by the above-mentioned erroneous correction can be reduced.

In this case, it is determined whether the correction is possible or not by looking at the calculation result of the above formula (1), but as can be seen from the calculation formula, it requires a large number of multiplications and additions, so the calculation process takes time. This also increases the scale of the implementation circuit.

In particular, the above formula (1) is an i&optimized formula on the premise that errors of 3 symbols are corrected, and decoding efficiency decreases in an error correction operation that outputs and corrects errors of 2 symbols or less. .

An object of the present invention is to provide an error correction code decoding method that can simplify the error detection function S of two symbols or less.

[Means to solve the problem]

The above purpose is, for example, to select 4 types of syndromes in the first process among 6 types of syndromes obtained during decoding.
Obtaining the error location and error pattern of the symbol error, and testing in a second process whether a certain relationship holds between the error location and the error pattern with respect to the remaining two syndromes that were not used in the first process. This is achieved by

[Effect]

Below, FIG. 1 shows the decoding procedure of the present invention. Among the 61M syndromes obtained during decoding, SOt Sl es21
The above equation (2) is calculated using S3. If the two-symbol error condition is satisfied, then A←0. B
~0. From the position polynomial when C~0, on the other hand, syndrome S4 when a two symbol error occurs. S5 is established. Therefore, by substituting the above provisional error location and error pattern into the above equation (3) and testing whether they are equivalent to S4 and S5, the condition of 84185 can be incorporated into the detection condition for two symbol errors.

Here α is the generator polynomial used in parity generation〇(X)−
It is one root when set to 0.

Similarly, when a one-symbol error occurs, that is, when the condition ABC-0 is satisfied in the calculation of equation (2) above, syndrome 84. S5d is established.

At this time, the error pattern ftEi = So r ”j
If ``'O'' is substituted into the above equation (3), the above equation (4) is obtained.In other words, the above equation (3) can be regarded as a general equation for testing error locations and error patterns of two symbols or less.

Therefore, the error detection calculation for 2 symbols or less is as described in (3) above.
Since it is only necessary to perform nt operations on the expression, the number of multiplication and addition operations can be reduced compared to the conventional operation of the above-mentioned expression (11).

Although the method for detecting an error of 2 symbols or less using 6-symbol parity has been described above, this decoding method is also effective when detecting an error of 3 symbols or less using 8-symbol parity. In this case, six syndromes SO* Sl pS2. S3. S4. From S5, the error location 1°j, kj15 and the error pattern E1 v ``j r ''k can be found and it is checked whether the results are established.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained using a W2B diagram. In the figure, 2 is a syndrome calculation circuit, and 3 is a circuit that detects 2-symbol errors and 1-symbol errors from four types of syndromes to obtain error locations and error patterns. Also, 19, 20, 21, 22.2
3 is an arithmetic circuit added according to the present invention.

The digital signal from the playback data input terminal 1 is processed by the syndrome calculation circuit 2, and the syndrome SO of 6M is processed.
+ Sl + S3 t S4 + S5 The zero-factor test circuit 4 is zero for four out of six syndromes SOr Sl e S2 # S3,
A non-zero test is performed, and if all are zero, it is assumed that there is no error and 7 lags with no error are output to the terminal 18.

If it is non-zero, it is determined that there is an error and the calculation shown in equation (2) above is performed. At this time, if the calculation results A, B, and C are all zero, it is determined that there is a one-symbol error, and a one-symbol error flag is output to the terminal 17. As a result, the switch Kl*K2 switches to 3, and the terminal 13 receives the data of the terminal 7, that is, the error butter ySO of 1 symbol error, and the terminal 14 receives the data of the terminal 9, that is, the 1 symbol factory location. Yon calculation circuit 5
Outputs the error location of the one-symbol error determined by Output the data zero of terminal 11 to terminal 15,
The calculation result of the multiplication circuit, which will be described later, is made to be zero.

If any of the calculation results A, B, or C is non-zero, the error verification circuit 4 determines that it is a 2-symbol error, and the 2-symbol error location and error pattern calculation circuit 6 calculates the 2-symbol error error pattern. g, ,
gj is outputted to output terminals 13 and 15 via terminals 8 and 12. The error location i is output through the terminal 10 to the output 14, and the error location j is directly output! I!
! Output to terminal 16.

19.20 is a circuit that performs multiplication and addition, and terminals 13,
14, 15. Output data i from 16.

i F'l + J + "J, respectively (α ・E
i+α”-Ej) and (αS1・Ei+α5j-Ej).These operations are performed using the calculation result f:R in advance.
It can be stored in OM (read only memory) and searched by table lookup.

Further, when one single error occurs, the error pattern So is output to the terminal 13 and zero is output to the terminal 15. That is, since the data is manually entered into the arithmetic circuit 19.20 as Ei-8o and Ej-0, the arithmetic output becomes 4i si α ·S(1+α ·So), and the result of the arithmetic operation on the right side of equation (4) is obtained.

21.22.23 shows the calculation results of the calculation circuit 19.20 and the syndrome S4. The coincidence of S5 is verified and the result is output to the terminal 26.

In executing the correction, first, the output from the terminal 18 is used to determine whether or not there is an error. If it is determined that there is an error, the output from the terminal 26 is used to determine whether correction is possible or not. If it is determined that the error is correctable, that is, the error is 2 symbols or less, the terminals 24, 25, 27 .
Select the error location and error pattern output to 28, and add the error pattern to the data indicated by the error location.

〔Effect of the invention〕

According to the present invention, since the number of additions and multiplications in the calculation for detecting errors of two symbols or less is reduced, it is possible to suppress an increase in the circuit size of the decoder.

Furthermore, since the time required for calculation can be shortened, decoding can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a flow chart showing a decoding procedure according to the present invention, FIG. 2 is a flow chart showing a conventional decoding procedure, and FIG. 3 is a circuit diagram showing an embodiment of the present invention. Explanation of symbols ゛2...Syndrome calculation circuit, 4...
Error verification circuit, 1 symbol engineer location calculation circuit, 6... 2 symbol error location and error pattern calculation circuit, 19.20.
...Multiplication and addition circuit, 21, 22.23...
...Coincidence agent Patent attorney Akio Namiki 1t1 Figure 12 Figure

Claims (1)

[Claims] 1. Using m types of parity symbols, n symbols or less (
However, in the decoding method of an error correction code that corrects code errors (n is a natural number equal to or less than (m/2-1)), 2n types of syndromes are selected from among the m types of syndromes obtained during decoding, and these are also a first step of determining the error location and error pattern of n symbol errors; A method for decoding an error correction code, comprising: a second step of testing whether there is a relationship.