JPH01255933A - Sweeping-out control system - Google Patents

Abstract

PURPOSE:To attain the control to delay the re-writing of a main storage device up to the completion of an instruction by adding an instruction completion flag to an instruction unit for a storing request issued in the storing instruction. CONSTITUTION:At present, the content of a sweeping-out pointer 19 is 1 and the content of an arithmetic result concerning the instruction A of a storing buffer 7 is swept out to the main storage device 8 by a memory access control part 11. At this time, for the content of the arithmetic result concerning an instruction B, when a storing action to the buffer 7 is started, 1 is stored into an instruction completion flag buffer 6 and the value of a buffer sweeping-out points 19 is updated to 2. When the sweeping-out to the main storage device 8 of the instruction A is completed, 1 from the buffer 6 is detected, the value of the pointer 19 is 1 and the content of the arithmetic result concerning the instruction B is stored into the main storage device 8.

Description

TECHNICAL FIELD The present invention relates to a flushing control system, and more particularly to a flushing control system for flushing from a store buffer to a main memory in arithmetic processing of instructions requiring 10 or more stores.

Pipeline processing in a conventional pipeline processing type information processing apparatus is performed as follows. Referring to FIG. 4, in this example of pipeline processing, an instruction fetch (IF) is used to retrieve an instruction from the instruction cache using an address means.
Operand address (AC) stage, in which the instruction fetched at this stage is stored in the instruction register and then a logical address is generated by an address adder based on the operand of this instruction. The address translation (AT) stage converts the logical address into a physical address in the address translation buffer after storing it in the address register.The physical address translated in this stage is stored in the physical address register, and then the operand cache is accessed using this physical address. The operand cache access (CA) stage reads out the operands, the operation execution (EX) stage stores the operands read in this stage in the execution register, and then performs calculations on the arithmetic unit. It is divided into six stages: a result storage (ST) stage that stores the results obtained.

Referring to FIG. 5, in the conventional pipeline processing type information processing device of this type, storage to the main memory device is inhibited until all - instructions are stored in the store buffer. In other words, instruction A, which is 4 bytes, is converted to instruction A at timing 10.
After the fourth byte of instruction A is stored, the first byte of instruction A is cleared at the next timing 11. Also, instruction B, which is a 2-byte instruction, is flushed from the store buffer to the main memory at timing 15 after all of instruction A has been flushed out.

Therefore, an instruction that requires many store operations in one instruction, such as instruction A, has the disadvantage that the period during which the instruction cannot be retried becomes longer.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a sweeping control method which eliminates the above-mentioned drawbacks.

The sweep control method according to the present invention includes a store buffer means for storing information related to one instruction by multiple slear operations;
The value is increased or decreased in response to a final store operation of information related to one instruction stored in the store buffer means, and the value is decreased or increased in response to a purge operation from the store buffer means. store buffer flushing pointer means; and inhibiting means for inhibiting a flushing operation from the store buffer means when the value of the store buffer flushing pointer means indicates that there is no instruction-related information to be flushed from the store buffer means. The configuration includes the following.

Ju Fengqiang Next, one embodiment of the present invention will be described in detail.

First, a circuit on which an embodiment of the present invention is based will be briefly described. Referring to Figure 1, the instruction retrieval (1F)
An instruction cache that stores instructions read out from the main memory 8 for stage processing; an address register 8 IC1 that supplies addresses to this instruction cache I Cache; an incrementer that updates the contents of this address register ^IC; +1, instruction cache I
It is provided with an instruction buffer IB for temporarily storing instructions from the Cache, and a selector 21 for selecting an instruction from either the instruction cache I Cache or the instruction buffer 1B.

In the operand address generation <^C) stage, an instruction register lR2O stores the changed instruction selected and output by the selector 21, and a register 8R stores an address from this instruction register lR2O or an address indexed by its value. and GRl, this instruction register lR2O, and address calculators AD and ^DD for calculating values from registers BR and GR and generating addresses.
ER is required.

For the address translation (AT) stage, there is a logical address register LAR that stores the logical address given from 〇〇ER to the address calculator AD, and an address translation buffer that reads the physical address in response to this logical address. TLB is provided.

Next, a physical address register PAIt for storing the physical address given from the address translation buffer TLB for the processing of the cache access (CA) stage;
Operand cache OC'achc, register groups BR and GR are used to store operands from main memory 8 at locations indicated by address information from address register PAR, and read out the stored operands.
1. Furthermore, a selector 22 is provided for selecting contents from these register groups Bft and Glt.

For the arithmetic execution (EX) stage, arithmetic units FLT and ADD for performing arithmetic operations, a shifter SHT for performing digit alignment, these arithmetic units FLT and ADD, and a shifter S
Execution register EXIt for storing operation results from HT and operand cache OCache, operation intermediate results, and operands, contents from selector 22, operation results from arithmetic unit FLT, ADD address, and shifter SHT, and operation intermediate results are stored. An arithmetic control unit 1 is provided which inputs information from a register REGISTER 2, an execution register EXR and a register REGISTER, and outputs an instruction to update the instruction counter 15 to a line 101.

At the result storage (ST) stage, arithmetic units FLT and ADD
In addition to the read data register RDII 5 for storing the operation result from the shifter SHT, a write address register 2 for setting the write address, an incrementer 3 for increasing the write address from this register WA2 by +1, Register A'4, which sets the instruction end flag provided via line 102, this register W
an instruction end flag buffer WFB6 that stores the flag from F4 in the location indicated by write address register 2;
A store buffer 7 for storing the contents of the read data register 5 applied via the line 103 in a position indicated by the address from the register Δ^2, and a subsequent address for storing the subsequent address for this store buffer 7. register 9, incrementer 10 for updating the contents of this successive address register 9, store buffer 7
A memory access control unit 11 outputs an instruction signal to a line 105 for controlling buffer flushing from to the main memory.
, a register H^R12 that sends the contents from the store buffer 7 to the main storage device 8 via the line 104 in response to an instruction signal applied from the memory access control unit 11 via the line 105, and a register H^R12 from the arithmetic control unit 1. In response to an instruction counter update instruction signal given via line 101, an instruction to output "1" as an instruction end flag to line 102 if the instruction counter is updated, and "0" to line 102 if the instruction counter is not updated. Counter (hereinafter referred to as IC) update control circuit 13, instruction counter 16, register TC15 that sets a value from the instruction counter 16 in response to a signal applied from the IC update control circuit 13 via line 102, IC update control A register WF117 that stores signals from the circuit 13, this register WF117, and an instruction end flag buffer W
A jx selection control circuit 18 that selects either one of the outputs from the FB 6, and a store buffer that selects and stores the incrementer 23, decrementer 24, or the output as is in response to a signal from the selection control circuit 818. Contains a sweep pointer 19.

Next, the operation of one embodiment of the present invention will be explained in detail with reference to FIGS. 1 to 3. Referring to FIGS. 1 and 2, in cycle 1, instruction cache I is transferred from main memory 8 to instruction cache I.
Instruction A is stored in Cache. Instruction A is a 4-word instruction. In cycle 2, instruction B is stored from the main memory 8 to the instruction cache I Cache, and instruction A is transferred from the instruction cache I Cache to the adder via the selector 21 and instruction register IR2O. Addresses are generated using AD and ADDER. In this manner, the processing of instructions A, B, and C proceeds. Instruction B is a 2-word instruction, and instruction C is a 1-word instruction.

Referring to FIGS. 1 to 3, the first word operation result regarding instruction A stored in read data register RDR5 in cycle 6 is stored in address 1 of store buffer 7 via line 103 in cycle 7. Ru.

Since no IC update instruction is output via the line 101, the value "0" stored in the register WFO4 from the IC update control circuit 13 via the line 102 is
Along with the operation of storing the word-th operation result in the store buffer 7, '0' is stored in the corresponding word of the instruction end flag buffer 6.

In cycle 10, the contents of the instruction counter register 15 become “A”.
"1" is stored in the instruction completion flag buffer 4, the incrementer 23 operates, and the contents of the store buffer flush pointer 19 change from "0" to "1".

This indicates that there is one instruction in the store buffer 7 that can be flushed out.

When the value of one store buffer flush pointer is “02”, there is no data that can be flushed out in the store buffer 7, so the memory access control unit 11 registers an instruction signal to suppress the flushing operation from the store buffer 7 to the main memory device 8. Give to 12.

Now, the content of the sweep pointer 19 is 1''',
The memory access control unit 11 instructs the register 12 to transfer the contents of the store buffer 7 to the main storage device 8 via the line 104. In response to this instruction, the register 12 begins to flush out the instruction A from the store buffer 7 to the main memory 8 in units of instructions.

In cycle 1o, the storage of the fourth word of instruction A to the store buffer 7 is completed, and in cycle 11, instruction B is stored in the store buffer 7.
The operation of storing the first word in the store buffer 7 is started.

When the contents of the instruction counter register 15 are updated in cycle 12, "P1" is stored in the instruction end flag buffer 6 in synchronization with this. At this time, the data is transferred from the store buffer 7 of the third word drawer of instruction A to the main memory 8, the instruction unit of instruction B cannot be flushed to the main memory 8, so the value of one store buffer flush pointer is counted up from 1" to 2". indicates that there is store data for two instructions that can be flushed out in the store buffer.

In cycle 13, the contents of the instruction counter register 15 are updated from "2" to "3" by the instruction counter 16, and when the operation result regarding instruction C is stored, the value "1" is set in the instruction end flag buffer 6 in synchronization with this. is stored. At this time, the fourth word of instruction A is stored in store buffer 7.
t1 is issued to the main storage device 8 from the command C.
It is not possible to flush out the calculation results related to the main storage device 8 to the main storage device 8.

Therefore, the value of one store buffer flush pointer is “2”.
” to “3” and store buffer 7
This indicates that there are three instructions worth of store data that can be flushed out.

In cycle 13, when the operation result of the fourth word of instruction A is flushed to the main memory 8 and ``1'' is output from the instruction end flag buffer 6, cycle 14
At this point, the contents of one store buffer 7 flush pointer are decremented by the decrementer 24, and the contents of one pointer change from "3" to "2°°." Indicates that there are two store data instructions.

In cycle 14, the operation result of the first word of instruction B is started to be flushed to the main memory 8, and in cycle 15, the operation result of the second word of instruction B is flushed to the main memory 8. It is done. When "1" is detected from the instruction end flag buffer 6, the value of the store buffer flush pointer 19 is decremented by the decrementer 24 and becomes "1". This indicates that there is one instruction worth of store data that can be flushed out in the store buffer 7.

When the instruction C is flushed out from the store buffer 7 in cycle 16, '1' is detected from the instruction end flag buffer 6, and in cycle 17, the value of one store buffer flush pointer is counted down by the decrementer 24 and becomes '0'. This indicates that there is no data in the store buffer 7 that can be flushed out.

Note that the instruction end flag buffer 6 has a buffer structure as shown in FIG. At other times, "0" is written.

Furthermore, if the flag stored in the instruction end flag buffer 6 at the same timing is "1", the value of the store buffer flush pointer 19 is counted up, and if it is "0", the value of the pointer 19 at that time is not counted up. is retained.

Further, the reading operation of the instruction end flag buffer 6 is also performed at the timing of flushing the instruction end flag buffer 6 from the store buffer 7 to the main memory device 8. If the value of the read instruction end flag is 1'',
The value of the store buffer purge pointer 19 is counted down, and if the value of the instruction end flag is "0", the value of the purge pointer 19 at that time is held without being counted down.

Next, we will explain the operation when a failure is detected in the execution stage.6For example, the cycle master E of instruction A
When a failure is detected in the Sweeping is inhibited, and command A instructs a paste try (retry).

The present invention adds an instruction completion flag to each instruction to a store request issued in a store instruction.
This has the advantage that it is possible to control the rewriting of the main storage device 8 until the end of the instruction.

Furthermore, by providing one store buffer purge pointer, the present invention can also purge old instructions stored in the store buffer 7 to the main memory 8, resulting in an effect that the retry rate can be improved. .

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a time chart for explaining the operation of an embodiment of the present invention, and Fig. 3 is a diagram showing an embodiment of the present invention.
The figure is a diagram showing the relationship between a store buffer, an instruction end flag buffer, and a store buffer flush pointer, FIG. 4 is a diagram for explaining pipeline processing, and FIG. 5 is a time chart for showing an example of a conventional technique. . Explanation of symbols of main parts 1...Arithmetic control unit 2...Write address register 3...Read data register 6...Instruction end flag buffer 7.・・・・・・
Store buffer 8...Main storage device 9...Continuation address register 11...Memory access control unit 13...
- Instruction counter update control circuit 15...Instruction counter register 16...Instruction counter 18...One selection control circuit...Store buffer flush pointer 20.
...Instruction register

Claims (1)

[Claims] (1) Store buffer means for storing information related to one instruction through multiple store operations, and whether the value of the information related to one instruction stored in this store buffer means is increased in response to the final store operation. a store buffer purge pointer means for decreasing or increasing a value in response to a purge operation from said store buffer means; and an instruction association whose value is to be purged from said store buffer means. and a suppressing means for suppressing a purge operation from the store buffer means when the information indicates that there is no information.