JPH01246927A - Satellite communication synchronizing network system - Google Patents

Abstract

PURPOSE:To prevent appearance of the Doppler variation of a satellite in the terminal equipment of a slave station by completely suppressing the variation of delay time caused by the Doppler variation at a main station and absorbing the varying quantity of the Doppler variation of demodulated main signals after clocks are reproduced at the slave station. CONSTITUTION:At a main station M ground system synchronizing network reference clocks 21 are received by means of a satellite communication network reference clock circuit 22 and satellite communication network reference clocks 22a controlled to have a fixed frequency relation are produced. Since control is performed at the main station M so that the phase after satellite turning route can become constant at the main station receiving point, the delay time variation caused by the Doppler variation of a satellite 6 is completely suppressed. At a slave station A, on the other hand, received signals are demodulated at a demodulator circuit 11 for main signal and slave station clock distributing channel demodulator circuit 12 and main signals and clocks are inputted to a Doppler buffer 13 and sent to a terminal 14 for digital synchronization as phase-shaped main signals. The clocks reproduced from the circuit 12 of the slave station are suppressed to small values in residual variation value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a satellite communication system, and more particularly to a digital synchronization network for a satellite communication system.

[Conventional technology]

Conventionally, when constructing a digital synchronous network using satellite communication, as shown in Fig. 2, - A reference station and a sub-station are defined for each satellite communication link, and the reference station 23 uses the terrestrial synchronous network reference clock 21 for satellite communication. The network reference clock circuit 22 receives this signal as a satellite communication network reference clock signal 22a with a fixed frequency ratio.
After converting the signal to the substation 24, it was used as a signal to be transmitted to the substation 24, a read clock for the Doppler buffer 25 for data signals received from other stations, and a clock to be passed to the terminals 26 and 26'.

Operates in one clock. What is the problem at this time?

Due to delay time fluctuations due to the diurnal fluctuations of the satellite.

The clock phase of the entire substation fluctuates accordingly. This is not a special issue in the case of a closed network consisting only of a satellite communication network, but when a terminal that edits the route is connected to a terrestrial synchronous network, the satellite communication route will slip on a daily basis. causes an error.

The present invention aims to solve this drawback and suppress Doppler fluctuations to the point where they can be almost ignored when viewing the satellite communication channel route from a terminal.

[Measures to solve problems]

According to the present invention, communication via a satellite is made up of a main station and a plurality of slave stations scattered in each region, using a satellite communication network reference clock controlled to have a fixed frequency relationship with respect to a terrestrial synchronous network reference clock. In a satellite communication system that performs

A phase variable control circuit capable of changing the phase of the satellite communication network reference clock using a control signal.

A clock distribution channel modulation circuit that emits a modulated signal triggered by the clock after this phase variable control circuit, a receiver that receives this modulated signal via the satellite, and a main station clock distribution channel demodulation circuit that demodulates the received signal. , comprising a means for comparing the phases of the regenerated reception clock and the satellite communication network reference clock at regular intervals and issuing the control signal, and the clock phase variable control circuit is configured such that the regenerated reception clock is connected to the satellite communication network reference clock. The slave station is controlled to always have a constant phase with respect to the network reference clock, and the slave station is provided with means for receiving the clock distribution channel signal emitted by the master station and regenerating the clock, and the regenerated clock is A satellite communication synchronization network system is characterized in that a signal to be passed to a slave synchronized terminal, a signal to be transmitted to a master station and a slave station, and C: a source of a clock for reading a Doppler buffer of a data signal received from another station is provided. can get.

〔Example〕

FIG. 1 shows the configuration of an embodiment of the present invention. The main station uses the terrestrial synchronous network reference clock 1 as the satellite communication network reference clock circuit 2.
A satellite communication network reference clock 2a with a constant frequency relationship is generated. After passing through the variable clock phase control circuit 3, this clock 2a is used as a modulation signal source clock of the modulation circuit 4 for the clock distribution channel. When this modulated clock distribution channel and network supervisory control device 4a is sending meaningful data, the data is.

Main station satellite communication transceiver5. The signal is received by the main station M, slave stations A, B, etc. via the satellite 6. In the main station M, this signal is regenerated by the main station clock distribution channel demodulation circuit 7, and the oil beetle clock and the satellite communication network reference clock 2a are phase-compared by the phase comparator circuit 8C2, and the two phase difference output is the clock phase variable control circuit. 3C2 sent. In this clock phase variable control circuit 3, the output clock phase is controlled so that the input phase difference output is always within a fixed phase difference. In this sense, the phase difference output is named a control signal.

In the 10,000 slave stations A and BC, the received signal is demodulated by the main signal demodulation circuit 11 and the slave station clock distribution channel demodulation circuit 12, and the main signal which is the output of the former and the latter The output clock is sent to the Doppler buffer 13 and sent to the digital synchronization terminal 14 as a main signal with two phases adjusted. Further, the data output from the latter is sent to the subordinate supervisory control device 15.

Here, the delay time caused by Doppler fluctuations of the satellite will be explained.

Considering the main station M, since the main station reception point controls the phase after the satellite return route to be constant, the delay time fluctuation due to satellite Doppler fluctuation can be avoided as long as the received recovered clock of the clock distribution channel is used. It can be said that at least the main station M is completely suppressed.

Case of slave stations located far apart 2 For example, consider the case of slave stations A and B in Figure 1. If the distance from the main station is approximately 2000, then the delay time to the satellite 36000 h above the equator is If the diurnal fluctuation is corrected to 0 at the master station, the clock regenerated from the slave station clock distribution channel and demodulation circuit 12 of the slave station will be far beyond the point where the terminal will cause operational problems (= The residual fluctuation value can be suppressed to a small value.For example, if the delay time diurnal fluctuation in Tokyo is corrected to "0" for satellite JC8AT2, and the delay time at Wakkanai, which is about 1l100K north of Tokyo, is calculated, the delay time in Tokyo The distance from to the satellite is 37345.82
3-±1956h, distance from Wakkanai to the satellite is approximately 380
72.322h±7.940 Km. Therefore, when the Doppler delay in Tokyo is corrected while checking the reception timing, the residual delay distance is -0,015-. This distance of approximately 15m is equivalent to 30fi in terms of path length.

The residual time is approximately 102 ns. This value is 64
This is a completely negligible small value compared to the kHz clock interval of about 16 μS. Therefore, if corrections are made in Tokyo, a clock without Doppler fluctuations can be provided in Wakkanai. In fact, it is possible to provide a clock whose Doppler fluctuations are practically negligible even at a point further north (outside Japan) of about 1000 Kl11. Note that the residual delay distance in Kagoshima is extremely small at approximately -1 m.

In this way, in the slave station, at least in an area the size of Japan, it is possible to create a clock source with almost no Doppler fluctuations without receiving a clock supply from a terrestrial synchronous network.

Therefore, in slave stations A and Bl2, the main signal is modulated using the regenerated phase-stable synchronization clock as a source, and if it is assumed that this is communication between slave stations A and B, the main signal modulation circuit 10 and The main signal demodulation circuit 11 transmits and receives the signal.

This received signal includes Doppler fluctuations of the satellite.

Each was absorbed using a Doppler buffer 13.

A signal without fluctuation is sent to the terminal 14. The terminal transmits a transmission signal slave-synchronized to the received signal to the modulation circuit 10 in the same way as a general synchronous terminal. This signal is sent to the opposite station, processed in the same manner as described above on the receiving side, and then passed to the terminal.

〔Effect of the invention〕

In the present invention, delay time fluctuations caused by Doppler fluctuations of the satellite are completely suppressed at least in the main station, and the slave stations completely suppress the delay time fluctuations caused by the Doppler fluctuations in the main signal demodulated by regenerating the suppressed clock. By absorbing this, it became possible to construct a satellite communication digital synchronization network in which the slave station (-) relies on the terrestrial clock supply and does not show the Doppler fluctuations of the satellite to the terminal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention, and FIG. 2 is a system diagram showing the master-slave relationship of clocks in a conventional digital synchronous satellite communication network. Explanation of symbols 21: Terrestrial synchronous network reference clock. 2... Satellite communication network reference clock semi-circuit, 3... Clock phase variable control circuit, 4... Clock distribution channel modulation circuit, 5... Main station satellite communication transceiver, 6...
... Satellite, 7... Main station clock distribution channel, demodulation circuit, 8... Phase comparison circuit, 9... Slave station satellite communication transceiver 1, 10... Main signal modulation circuit, 11...・Main signal demodulation circuit, 12...Slave station clock distribution channel demodulation circuit, 16...Tombler buffer, 14...
・Digital synchronous network terminal, 15...Subordinate monitoring and control device. early morning gourd

Claims (1)

[Scope of Claims] 1. Comprised of a main station and a plurality of slave stations scattered in various regions, the system uses a satellite communication network reference clock that is controlled to have a fixed frequency relationship with respect to the terrestrial synchronous network reference clock. In a satellite communication system that performs communication using A modulation circuit for a clock distribution channel that generates a clock, a receiver that receives this modulated signal via the satellite, a main station clock distribution channel demodulation circuit that demodulates the received signal, and a clock distribution channel demodulation circuit that demodulates the received signal. The clock phase variable control circuit is provided with means for comparing the phases at each cycle and issuing the control signal, and the clock phase variable control circuit is controlled so that the regenerated reception clock always has a constant phase with respect to the satellite communication network reference clock. The slave station is provided with means for receiving the clock distribution channel signal emitted by the master station and regenerating the clock, and transmitting a signal to pass the reproduced clock to the slave-synchronized terminal and to the master station and the slave station. A satellite communication synchronous network system characterized in that the signal is used as a source of a readout clock for a Doppler buffer of data signals received from other stations.