JPH01245728A - Intermittent transmission and reception system - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution of each relay station and a terminal station by allowing a base station to generate and manage the information for intermittent control centralizingly and allowing each relay station and a terminal station to transit to the intermittent processing mode at a point of time of receiving a pattern bit for the intermittent control in a time division multiplex communication system. CONSTITUTION:An intermittent control pattern based on start/release for intermittent control, turn-on/turn-off ratio and repetitive period is set to an intermittent processing information setting means 151 in a base station 10, the pattern is multiplexed with other time slot data in a timing from a timing generating means 154, the result is sent as an intermittent control pattern bit and the transmission of all data including a frame pattern is stopped from the base station 10. The intermittent control pattern bit is set to an intermittent processing control information storage means 281 in a relay station 2(i) or a terminal station 3(i) to bring an intermittent processing means 282 into the intermittent processing to stop part of power supply and clock start in the inside.

Description

[Detailed Description of the Invention] [Summary] When transitioning to intermittent processing mode in a time division multiplex communication system, the base station sets conditions consisting of the on/off rate and repetition period for starting/releasing the device intermittently. Regarding the intermittent transmission/reception method that performs centralized processing, the purpose of this system is to realize an intermittent transmission/reception method with a smaller overall circuit configuration. An intermittent processing information setting means for setting in Bakun, a control time slot data insertion means for inserting an intermittent control pattern focus outputted from the intermittent processing information setting means into a control time slot 1-, and a means for multiplexing the intermittent control pattern bit with data. The base station is provided with timing generation means for generating timing signals to be multiplexed and transmitted at the base station, and intermittent processing control information storage means for storing intermittent control pattern bits transmitted from the base station, and intermittent processing control information. An LJ configuration in which the relay station and the terminal station are equipped with an intermittent processing means that shifts the internal to an intermittent processing mode based on the intermittent control pattern bit stored in the storage means and turns on/off the activation of some internal power supplies and clocks. do.

[Industrial application field]

The present invention relates to an intermittent transmission/reception system in which a base station centrally processes conditions consisting of an on/off ratio and a repetition period for starting/releasing a device intermittently when transitioning to an intermittent processing mode in a time division multiplex communication system.

For example, when installing a telephone line in a remote area for a small number of subscribers, in order to save the cost and time of laying cables, it is necessary to install a terminal station to accommodate subscribers and multiple terminal stations to accommodate subscribers. By setting up multiple relay stations to accommodate wireless communication,
Data is wirelessly relayed to these base stations that serve as centers.

Further, this base station has this multi-stage relay station under its control, and a digital data wireless communication system has been put into practical use in which data received from these stations is converted and connected to a telephone station via wire.

In other words, a base station has a plurality of relay stations and terminal stations under its control, and data transmission between these stations is performed using a time division multiple access system (hereinafter referred to as a TDMA system) using the same frequency. .

When relaying data in multiple stages in this TDMA system, the data is inserted into a predetermined time slot 1- to perform data relay processing.

However, when the data to be transmitted is not always present, such as at night or when data is lost, the system switches to an intermittent transmission/reception mode that activates the system intermittently when data is generated, reducing power consumption. The method is implemented.

In implementing such an intermittent transmission/reception method, it is necessary to simplify the intermittent transmission/reception mode processing functional block and downsize the entire system.

[Conventional technology]

FIG. 5 is a block diagram explaining a conventional example of a base station, FIG. 6 is a block diagram explaining a conventional example of a block that performs intermittent processing, FIG. 7 is a diagram explaining an overview of the configuration of a multi-stage relay system, and FIG. The figure is a diagram explaining the configuration overview of a base station/one intermediate phase station,
FIG. 9 shows diagrams each explaining the frame format of data in a wireless section.

FIG. 7 shows the configuration of a TDMA digital wireless communication system, which consists of each terminal station 3(i) and relay stations 2(i), 2 serving as the center of the TDMA digital wireless communication system.
(j) Converts the speed and formant of the voice concentrated from the PCM highway (al Terminal 3(i)
and a base station 1 that transmits to relay stations 2(i) and 2(j),
A relay station 2 each accommodates a plurality of terminal stations 3(i) and terminals of a plurality of telephone subscribers, etc., and performs relaying in a maximum of 12 stages.
(i), 2(j), a plurality of terminal stations 3(i) located at the final rung of the digital wireless communication system and accommodating terminals such as a plurality of telephone subscribers, and a PCM highway (al It is comprised of a concentrator 4 that converts the voice that is received via a 2-wire (2W) line and accommodates it in an exchange 5, and an exchange 5 that accommodates a plurality of telephone subscribers.

FIG. 8 shows part of the configuration of the base station 1 and relay station 2(i) described above, and the base station 1 in the figure is a processor (hereinafter referred to as MPII) that controls processing operations within the station based on a predetermined program. 1
1, and a control circuit (hereinafter referred to as C0NT) 1 that can specify a processing job routine to be executed based on MPU II by operating a terminal (not shown) connected to the concentrator 4.
2, a transmitter/receiver (hereinafter referred to as TRX) 13 that transmits and receives data using the TDMA method, and a preamble (as shown in Fig. 9 (C) and (b)) for each of the plurality of transmission data to be transmitted to the downlink. A transmission control unit (hereinafter referred to as DTX) 14 inserts a frame synchronization signal FC+ of a time slot (a string of information for the purpose of synchronization) into the beginning of a data frame and multiplexes the data frame.
The reception control unit (hereinafter referred to as UR) extracts and reproduces the received data transferred from the uplink in the time slot TS.
(referred to as X) 15 and a speed conversion circuit 19a that mutually converts the data transmission speed between 2 Mbps and 704 Khps. and a downlink reception control unit (hereinafter referred to as DRX) 22 that controls the reception of downlink data.
and an uplink transmission control unit (hereinafter referred to as UTX) 23 that controls the transmission of data on two lines, and a delay adjustment control unit that adjusts the deviation in time slot transmission timing within its own station based on instructions from the upper station. (hereinafter referred to as DL C0NT) 24, a control unit (hereinafter referred to as C0NT) 25 that controls processing operations within the station, and a control unit (hereinafter referred to as C0NT) 25 that sets and executes intermittent processing conditions and timing according to the contents of the control time slot. An intermittent processing/interface unit (hereinafter referred to as B, 5AVE/INF) 26 that provides an interface for sending out data to the downlink, and an interface unit (hereinafter referred to as TNT) that interfaces with and controls telephone subscriber terminals, data terminals, etc.
(referred to as F) 27.

Note that the terminal station 3(i) shown in FIG. 7 has substantially the same functions as the central station 2(i) except for processing such as interface with the downlink.

The control time slot 1- (corresponding to TSO) in the downlink received data is a synchronization pulse for creating a synchronization clock, etc. for the subsequent data, as shown in FIG. 9(C). Preamble pulse (b), frame synchronization signal (C) that checks synchronization for each data frame
)2 intermittent control data (dl) and call control data (el) to instruct intermittent processing are inserted.

Note that FIGS. 9(A) and 9(B) show the data frame format of a wireless section of 5632 bits per frame.
FIG. 9(A) shows upstream data transmitted from a lower station to an upper station, and FIG. 9(B) shows downlink data transmitted from an upper station to a lower station.

In addition, the intermittent control data (dl) includes a signal instructing intermittent processing, an on/off ratio for performing intermittent processing, a repetition period of intermittent processing, and the like.

Next, as shown in FIG. 6, the functional block of B, S/IVE/lNF 26 shown in FIG. The activation/cancellation pattern detection circuit 261 detects activation/cancellation instruction signals for processing, and the intermittent control data (dl) of the control time slot (TSO) in the downlink data. The on/off ratio/repetition period launch circuit 262 latches instruction data for setting the processing repetition period, and the activation/cancellation instruction signal detected by the activation/cancellation pattern detection circuit 261 and the on/off ratio/repetition period latch. An intermittent control signal generation circuit 263 that generates signals for intermittent control based on the on/off ratio, etc. launched in the circuit 262, and various timing signals necessary to operate each functional block for intermittent processing are sent from IIRX22. The control signal generating circuit 264 generates a control signal based on the obtained reference signal.

Incidentally, FIG. 5 shows an outline of the configuration of the DTX 14 in the base station 1,
T to insert conditions related to intermittent control (intermittent activation/cancellation, on/off ratio, repetition period, etc.) set by the MPU II based on the program into the control time slot TSO.
S○ control data circuit 141 and preamble pulse (
A preamble generation circuit 142 that generates a frame synchronization signal (C1), a synchronization pattern generation circuit 143 that generates a frame synchronization signal (C1), and a multiplexer (hereinafter referred to as MU) that multiplexes a plurality of data and signals.
A scrambling circuit 145 that scrambles the multiplexed data output from the MUX 144, and a parity addition circuit 146 that adds a parity bit to the scrambled multiplexed data and sends it out as downlink transmission data. Equipped with

Base station 1-relay station 2(i) and terminal station 3(i) shown in FIG.
9 is a wireless section in which data is transmitted and received using microwaves, for example, and the data transmitted and received in this wireless section is shown in Fig. 9 (A
), the frame format shown in (B) is preserved.

That is, when the DTX 13 in the base station 1 transmits a downlink data frame, a 16-bit preamble (b) is placed at the beginning of the time slot TSO, as shown in FIGS. Subsequently, the 16-bit frame synchronization signal (SYNC) (C1) and the intermittent control data (di
and call control data (e).

In addition, "G" shown in FIGS. 9(A) and 9(B) indicates the time slot numbers of guard pins 1 to TSO to TS18.

In addition, the intermittent control data fdl is the condition for intermittent control specified from the base station 1 in the base station 1. It is inserted into the time slot TSO by the l data circuit 141.

This intermittent control condition inserted into the time slot SO 1-TSO is based on other time slot SO I-TSi data and the pudding pulse (b) generated from the pudding ampule circuit 142.
, the frame synchronization signal (C1) output from the synchronization pattern transmission circuit 143, and is multiplexed by the MUX 144 and transmitted.

Relay station 2 (i) or terminal station 3 (i)
The activation/cancellation instruction signal for intermittent control is detected by the activation/cancellation pattern detection circuit 261 from the received and processed signals, and the data regarding the on/off ratio and repetition period for intermittent processing are turned on/off. It is latched into the off ratio/repetition period latch circuit 262.

Next, the intermittent control signal generation circuit 263 is operated with the instruction signal detected by the activation/cancellation pattern detection circuit 261, and a mode instruction signal for intermittent control is generated and sent at the timing from the control signal generation circuit 264. .

The mode instruction signal for this intermittent control is used to stop the clock supply to stop the subscriber's incoming and outgoing calls and to stop the power supply for functions other than the data relay function.The set intermittent on/off ratio and repetition period have and control it.

[Problem to be solved by the invention]

As mentioned above, conventional intermittent control is performed from base station 1 to relay station 2.
(i) or the terminal station 3(i), multiplex and transmit the conditions regarding the on/off ratio and repetition period of the activation/cancellation intermittently for intermittent control, and Based on these conditions, station 3(i)
/lNF26 generates a mode instruction signal for intermittent internal processing.

Therefore, conventionally, B of each relay station 2(i) or terminal station 3(i)
.

There was a tendency for the configuration of 5AVE/lNF26 to become larger.

An object of the present invention is to realize an intermittent transmission/reception method in which the circuit configuration of the entire system is miniaturized.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

Reference numeral 10 in the block diagram of the principle of the present invention shown in FIG. Intermittent processing information setting means 151 set by a control pattern, and intermittent processing information setting means 151
control time slot data insertion means 1 for inserting intermittent control pattern bits output from the control time slot into the control time slot;
52, multiplexing means 153 for multiplexing control time slot data with other data and pulses, and timing generation means 154 for generating a timing signal for transmitting intermittent control pattern bits, and 20( i)/30(i) is an intermittent processing control information storage means 281 that stores the intermittent control pattern bits transmitted from the base station 10, and the intermittent control pattern bits stored in the intermittent processing control information storage means 281 are These relay stations and terminal stations are equipped with an intermittent processing means 282 that performs intermittent processing, and these means are used as means for solving the problem by controlling intermittent processing.

[For production]

An intermittent control pattern based on activation/release, on/off ratio, and repetition period for intermittent control is set in the intermittent processing information setting means 151 in the base station 10, and other time slots are set at the timing from the timing generation means 154. It is multiplexed with i.data and transmitted as an intermittent control pattern bit, and at the same time, the base station 10 stops transmitting all data including frame patterns.

In the relay station 2(i) or the terminal station 3(i), this intermittent control pattern bit is set in the intermittent processing control information storage means 281, the intermittent processing means 282 is shifted to intermittent processing, and some internal power supplies and clocks are switched off. Stop starting.

That is, based on the intermittency ratio and the contents of the repetition cycle, when intermittent processing is on, the clocks and power supplies in relay station 2 (i) or terminal station 3 (j) other than the predetermined functional blocks are turned off and the data transmission processing operation is performed. When the relay station 2 is stopped and turned off, the relay station 2 returns to normal operation status upon receiving the frame pattern whose transmission is started from the base station 10.
(i) or the circuit configuration related to intermittent control at the terminal station 3(i) can be simplified.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 to 2.

FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a block diagram explaining an embodiment of the relay station/terminal station according to the present invention, and FIG. 4 is an overview of the configuration of the base station according to the present invention. A block diagram explaining each is shown. Note that the same reference numeral indicates the same object throughout the drawings.

The embodiment shown in FIGS. 2 and 3 is a block diagram for explaining an embodiment of the DTX 140 in the base station 10a that centrally controls the intermittent processing of the present invention, and the relay station/terminal station.

The base station 10a of this embodiment has the same function as that explained in FIG. 2(j)
If there is no time slot for sending a call and the call processing sequence is not in progress, turn off the activation of each terminal station 3(i) and relay stations 2(i) and 2(j), and wait until a call has occurred. In some cases, it has a function to centrally perform intermittent control to turn on the activation.

Further, in the present embodiment shown in FIGS. 2 and 3, the intermittent processing information setting means 151 explained in FIG.
An intermittent activation/cancellation ratio setting circuit 151a (not shown) is configured based on instructions from the sub-MPU 19c, and is set in a pattern of several bits. A TSO control data circuit 152a that inserts the contents of the intermittent start/cancellation ratio setting circuit 151a into the time slot TsO at startup, and a multiplexing means 153 to the intermittent startup/cancellation ratio setting circuit 151a as described in FIG. 70 shown in FIG.
In this example, the timing generating circuit 154a reproduces and outputs the multiplexed data from the timing outputted from the timing generating circuit 19d at the multiplexed data sending timing.

Further, as the intermittent processing control information storage means 281, DTXI
A TSO that holds tie 1, slot 1 information sent from /10 and has intermittent all pattern bits inserted.
The control time slot separation/sending circuit 281a separates and sends the TSO to the intermittent processing circuit 282a, and as the intermittent processing means 282, the intermittent control Bakun Bisoto inserted in the TSO separated by the control time slot separation/sending circuit 281a is set. and an intermittent processing circuit 282a that shifts to an intermittent processing mode for executing intermittent processing.

Note that the PCM highway (a
) is assumed to be 2 Mbps.

Also, a double series of DTX 140 at the base station 10a
As shown in FIG. 4, the other functional blocks include a PCM highway reception processing circuit 1.6a that performs reception processing and transmission processing of data that is left behind via the PCM highway (AL) with the concentrator 4; , PCM highway transmission processing circuit 16b, PCM highway reception processing circuit 16a, PCM highway timing generation circuit 17 that generates processing timing for PCM highway transmission processing circuit 16b, and data received and processed by PCM highway reception processing circuit 16a. 2Ml] IIS and a clock regeneration circuit 18 that regenerates the 704Kbps clock, a speed conversion circuit 19a that converts the data transmission speed between 2Mbps and 704Kbps, and a main MPU that controls the conversion process of the speed conversion circuit 19a.
19b, a SAF'MPUL9c that controls a series of processing between the DTX 140, the URX 15, and the speed conversion circuit 19a, a timing generation circuit 19d at 704 that generates the timing when converting to 704 Kbps in the speed conversion circuit 19a, and an eighth
It is equipped with the same URX 15 as explained in the figure.

The Sub MPU 19C accesses the DTX 140 and sets the on/off ratio, repetition period, and intermittent activation/cancellation information for intermittent processing to the intermittent activation/cancellation ratio setting circuit 151a, and also performs intermittent control based on these. Set the related data in a pattern of several bits.

Then, together with the TSO control data circuit 152a and the timing generation circuit 154a, the intermittent activation/cancellation ratio setting time-1!
1. The activation of the path 151a is also delayed. Note that from this point forward, transmission of the frame synchronization signal (C1) from the base station 10a is stopped.

The intermittent activation/cancellation ratio setting circuit 151a inserts the intermittent control pattern bit set in the TS○ control data circuit 152a into the control time slot 1-TSO according to the timing from the timing generation circuit 154a, and generates a preamble pulse (b) and frame synchronization. Signal (C) and time slot 1
- MU with time slot I-TSi data other than TSO
Multiplex with X144.

This multiplexed data is scrambled according to the timing from the timing generation circuit 154a, has a parity bit added thereto, and is transmitted as downlink transmission data in the format shown in FIG. 9.

The relay station 2(j) or the terminal station 3(i) receives and processes this downlink transmission data via the TRX21 and DRX22, separates the control time slot TSO, and stores it in the control time slot separation/sending circuit 281a.

MPU 283a in relay station 2(i) or terminal station 3(i),
The intermittent control pattern bits stored in the control time slot isolation/transmission circuit 281a are sent to the intermittent processing circuit 282a, and the incoming and outgoing calls of the subscriber are stopped via the INFT 27. do.

On the other hand, the intermittent processing circuit 282a
1-1, the system enters an intermittent processing mode in which intermittent processing is executed, thereby turning off power related to internal data processing and stopping clock supply.

Next, when the base station 10a returns from the intermittent processing mode, the relay station 2(i) or the terminal station 3(i) receives the frame synchronization signal (C), etc., and returns to the normal operating state.

As described above, the base station 10a centrally generates and manages information for intermittent control, and each relay station 2(i) or terminal station 3(
In i), the circuit configuration at each relay station 2(i) or terminal station 3(i) is It will be more simplified.

〔Effect of the invention〕

According to the present invention as described above, it is possible to provide a relay station or a terminal station having a more simplified circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a block diagram explaining an embodiment of the relay station/terminal station in the present invention, 4 is a block diagram illustrating an overview of the configuration of a base station according to the present invention; FIG. 5 is a block diagram illustrating a conventional example of a base station; FIG. 6 is a diagram illustrating a conventional example of a block that performs intermittent processing; Figure 7 is a diagram explaining the configuration overview of the multi-stage relay system, Figure 8 is a diagram explaining the configuration overview of the base station/relay station, and Figure 9
The figure shows a diagram explaining the frame format of data in a wireless section. In the figure, L 10.10a is the base station, 2(i), 2(j), 20(i) are the middle 21111 stations, 3(i), 30(i) are the terminal stations, 4 is the concentrator station, 5
11, 283a is MPU, 12.25 is C
QNT, 13.21 baTl1X, 14,
140ba DTX. 15 is URX, 16a is PCM highway reception processing circuit, 16h is PC
M highway transmission processing circuit, 17 PCM highway timing generation circuit, 18 clock regeneration circuit, 19a speed conversion circuit, 19b main MI'll, 1
9c is a nub MPU, 19d is a timing generation circuit at 704, 22 is a DRX, and 23 is a UTX. 24 is DCC0NT, 26 ban, 5AVE
/INF. 27 is INTF, 14L152a is a TSO control data circuit, 142 is a preamplifier generation circuit, 143 is a synchronization pattern generation circuit, 144 is MIIX, 145 is a scrambler circuit, 146 is a parity addition circuit, 151 is an intermittent processing information setting means, 151a 152 is a control time slot data insertion means; 153 is a multiplexing means; 154 is a timing generation means; 154a is a timing generation circuit; 261 is an activation/cancellation pattern detection circuit; 262 is an on/off pattern detection circuit;
OFF ratio/repetition period launch circuit, 263 is an intermittent control signal generation circuit, 264 is a control signal generation circuit, 281 is an intermittent processing control information storage means, 281a is a control time slot separation/sending circuit, 282
is an intermittent processing means; 282a is an intermittent processing circuit;

Claims (1)

[Claims] A plurality of relay stations (20
(i)) and a terminal station (30(i)), information for intermittently controlling activation of the relay station (20(i)) and terminal station (30(i)) is provided. an intermittent processing information setting means (151) for setting an intermittent control pattern of several bits; and a control time slot data insertion means (for inserting intermittent control pattern bits outputted from the intermittent processing information setting means (151) into a control time slot). 152), and means (153) for multiplexing the intermittent control pattern bits with data.
A timing generating means (154) for generating a timing signal to be multiplexed and transmitted at the base station (10).
), and an intermittent processing control information storage means (281) for storing the intermittent control pattern bits transmitted from the base station (10); An intermittent processing means (intermittent processing means) that shifts the internal part to an intermittent processing mode based on the control pattern bit and turns on/off some internal power supplies and clocks.
282) and the relay station (20(i)) and the terminal station (30(i)).
(i)), and transmits intermittent control pattern bits, which are patterned based on the activation/cancellation instruction of intermittent control, the intermittent on/off ratio, and the repetition period, at the base station (10) to the relay station (20(i)). )
) and the terminal station (30(i)) by setting it in the intermittent processing means (282) in the relay station (20(i)) and the terminal station (30(i)).
30(i)) is centrally controlled by the base station (10).