JPH01243639A - Modem device - Google Patents

Modem device

Info

Publication number
JPH01243639A
JPH01243639A JP63070068A JP7006888A JPH01243639A JP H01243639 A JPH01243639 A JP H01243639A JP 63070068 A JP63070068 A JP 63070068A JP 7006888 A JP7006888 A JP 7006888A JP H01243639 A JPH01243639 A JP H01243639A
Authority
JP
Japan
Prior art keywords
modem
hdlc
data
deframing
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63070068A
Other languages
Japanese (ja)
Other versions
JPH0775361B2 (en
Inventor
Takaani Enokida
榎田 孝兄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic System Solutions Japan Co Ltd
Original Assignee
Matsushita Graphic Communication Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Graphic Communication Systems Inc filed Critical Matsushita Graphic Communication Systems Inc
Priority to JP63070068A priority Critical patent/JPH0775361B2/en
Publication of JPH01243639A publication Critical patent/JPH01243639A/en
Publication of JPH0775361B2 publication Critical patent/JPH0775361B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To reduce burden on hardware and software by providing an HDLC framing part and an HDLC deframing part in a MODEM and executing HDLC framing and deframing on the side of the MODEM. CONSTITUTION:Functions for executing high level data link control(HDLC) framing and deframing are given to the internal part of a control DSP 13 which executes the digital signal processing of the MODEM 11. A MODEM controller 10 gives a control signal, makes the MODEM 11 in a reception state and transmits data to the MODEM 11. In the MODEM 11, received data is HDLC- framed in an HDLC framing part 17 and is modulated so as to be transmitted on a line 14. At the time of data reception on the other hand, the MODEM 11 demodulates received data, executes HDLC deframing and transmits data to the MODEM controller 10. Thus, the MODEM controller 10 can execute only MODEM control, and burden on hardware and software is reduced.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はモデム装置、特に送受信データのHDLC処理
を効率的に行ない得るモデム装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a modem device, and more particularly to a modem device that can efficiently perform HDLC processing of transmitted and received data.

従来の技術 近年、ファクシミリ等の通信システムにおいて、回線の
品質等の原因による通信データエラーを検出するために
、通信データをHDLC(ハイレベル・データ・リンク
Φコントロール)のフォーマットにして通信する方法が
多くとられている。HDLCのフレーミング或はデフレ
ーミングを行なうために、従来は、モデム制御装置内に
HDLCフレーミング、デフレーミング処理部を設けて
いた。このようなモデム装置の一従来例を第2図に示す
。このモデム装置は、モデム制御用の回路1とこのモデ
ム制御回路1に接続され、送信データに対してHDLC
フレーミング、受信データに対してHDLCデフレーミ
ングを行なうHDLC回路2とを有するモデム制御装置
3、及びモデム制御装置3と回線4との間に配置され、
データの入出力を行なうI10回路5と、CPUから構
成されデジタル信号の制御を行なう制御用デジタル・シ
グナル・プロセッサ6と回線4との間でアナログ通信を
行なうアナログ回路7とを有するモデム8とから成る。
BACKGROUND OF THE INVENTION In recent years, in communication systems such as facsimiles, a method has been developed to convert communication data into HDLC (High Level Data Link Φ Control) format in order to detect communication data errors caused by line quality, etc. A lot is taken. In order to perform HDLC framing or deframing, an HDLC framing/deframing processing section has conventionally been provided in a modem control device. A conventional example of such a modem device is shown in FIG. This modem device is connected to a modem control circuit 1 and this modem control circuit 1, and is connected to an HDLC for transmission data.
a modem control device 3 having an HDLC circuit 2 that performs framing and HDLC deframing on received data; and a modem control device 3 disposed between the modem control device 3 and a line 4;
A modem 8 having an I10 circuit 5 for inputting and outputting data, a control digital signal processor 6 composed of a CPU for controlling digital signals, and an analog circuit 7 for performing analog communication between the line 4. Become.

そして、モデム制御装置3は、モデム2に対して制御線
IA、IB、データ線2A。
The modem control device 3 connects the modem 2 with control lines IA, IB, and data line 2A.

2Bを通してデータ授受と制御信号の送受を行なう。ま
た、モデム制御装置3内では、制御回路1とHDLC回
路2は信号線3A、3Bで接線されデータの授受を行な
う。
Data is exchanged and control signals are exchanged through 2B. Further, within the modem control device 3, the control circuit 1 and the HDLC circuit 2 are connected to each other by signal lines 3A and 3B to exchange data.

例えばデータ送信時、モデム制御装置3内の制御回路1
は、制御線IA、IBを使ってモデム8を受信状態にす
る。次に制御回路1は信号線3A。
For example, when transmitting data, the control circuit 1 in the modem control device 3
puts the modem 8 into the receiving state using control lines IA and IB. Next, the control circuit 1 has a signal line 3A.

3Bにより、モデム制御装置1内部のHDLC回1路2
を制御すると共に送信データを書き込む。HDLC回路
2によってHDLCフレーミングされたデータは信号線
2Aを通してモデム8に送られる。モデム8はそのデー
タを変調し、回線4に送出する。また、受信時は、回線
4より入力した信号をモデム8で復調し、復調されたデ
ータは、信号線2Bを通してモデム制御装置3内部のH
DLC回路2に入力される。そして制御回路1は、信号
線3Bを介して、デフレーミングされたデータを受けと
る。
3B, HDLC circuit 1 circuit 2 inside modem control device 1
control and write the transmission data. Data subjected to HDLC framing by the HDLC circuit 2 is sent to the modem 8 through the signal line 2A. Modem 8 modulates the data and sends it out on line 4. Also, during reception, the signal input from the line 4 is demodulated by the modem 8, and the demodulated data is sent to the H within the modem control device 3 through the signal line 2B.
The signal is input to the DLC circuit 2. The control circuit 1 then receives the deframed data via the signal line 3B.

発明が解決しようとする課題 しかしながら、前記のような従来のモデム装置にあって
は、HDLC回路2がモデム制御装置3内に組込まれて
いるため、このモデム制御装置3は、本来の役割シであ
るモデム8の制御に加えてHDLC回路2の制御をしな
ければならずハードウェア及びソフトウェアの負担が大
きかった。
Problems to be Solved by the Invention However, in the conventional modem device as described above, since the HDLC circuit 2 is incorporated in the modem control device 3, this modem control device 3 does not play the original role. In addition to controlling a certain modem 8, the HDLC circuit 2 had to be controlled, which placed a heavy burden on the hardware and software.

課題を解決するための手段 本発明は上記課題を解決するため、モデムの制御DSP
内部にHDLCフレーミング及びデフレーミングを行な
うための機能を持たせ、モデム側でHDLCフレーミン
グ及びデフレーミングを行ない得るようにしたことを要
旨とする。
Means for Solving the Problems In order to solve the above problems, the present invention provides a modem control DSP.
The gist is that a function for performing HDLC framing and deframing is provided internally, so that HDLC framing and deframing can be performed on the modem side.

作用 モデム制御装置は制御信号を発してモデムを受信状態に
し、データをモデムに送る。モデム内では受信したデー
タをHDLC回路のフレーミング部でHDLCフレーミ
ングを行ない、これを変調して回線上に送出する。他方
データ受信時は、モデムは受信データを復調し、その後
HDLCデフレーミングを施してモデム制御装置に送る
。これによってモデム制御装置はモデム制御のみを行な
えばよく、ハードウェア又はソフトウェア上の負担が軽
くなる。
The operating modem controller issues control signals to place the modem in a receive state and send data to the modem. In the modem, received data is subjected to HDLC framing in a framing section of an HDLC circuit, and the data is modulated and sent onto the line. On the other hand, when receiving data, the modem demodulates the received data, then performs HDLC deframing and sends it to the modem control device. As a result, the modem control device only needs to control the modem, which reduces the burden on hardware or software.

実施例 第1図は本発明によるモデム装置の一実施例を示すブロ
ック図である。この実施例に係るモデム装置は、制御回
路9を有するモデム制御装置10とこのモデム制御装置
10によって制御され送受信データの変調及び復調を行
なうモデム11とから成る。
Embodiment FIG. 1 is a block diagram showing an embodiment of a modem device according to the present invention. The modem device according to this embodiment includes a modem control device 10 having a control circuit 9, and a modem 11 controlled by the modem control device 10 to modulate and demodulate transmitted and received data.

モデム11は、モデム制御装置とのインタフェースを行
なうI10回路12と、デジタル信号処理を行なう制御
D S P 13と回線14に接続されるアナログ回路
15とを備えている。更に制御D S P 13はI1
0回路12に信号線16によって接続されたHDLCフ
レーミング部17と、HDLCフレーミングされた後の
データを格納するメモリ18と、送信データを変調する
変調部19と、受信データを復調する復調部加と、復調
されたデータを格納するメモリ21と、受信データに対
してHDLCデフレーミングを施し信号線nを通してI
10回路に出力するHDLCデフレーミング部nと、バ
ス冴を介して各機能部に接続されこれらの機能部を制御
する制御部5とを備えている。この制御D S P 1
3の内部において、変調部19及び復調部加とアナログ
回路15との間はバスが及び信号線rによりて接続され
ておシ、また信号線16からはメモリバス羽へ向けて分
岐信号線画が延びる一方、メモリバス(9)から信号線
nへは分岐信号線31が延びている。
The modem 11 includes an I10 circuit 12 that interfaces with a modem control device, a control DSP 13 that performs digital signal processing, and an analog circuit 15 that is connected to a line 14. Furthermore, the control D S P 13 is I1
0 circuit 12 through a signal line 16, a memory 18 that stores data after HDLC framing, a modulation section 19 that modulates transmission data, and a demodulation section that demodulates reception data. , a memory 21 for storing demodulated data, HDLC deframing is performed on the received data, and the I
10 circuits, and a control section 5 that is connected to each functional section via a bus and controls these functional sections. This control D S P 1
3, a bus is connected between the modulator 19 and the demodulator and the analog circuit 15 by a signal line r, and a branch signal line is connected from the signal line 16 to the memory bus. On the other hand, a branch signal line 31 extends from the memory bus (9) to the signal line n.

かかる構成を有するモデム装置について、その動作を以
下に述べる。モデム11はモデム制御装置よシ信号線3
2を介してHDLCモード指定のコマンドとデータ送信
のコマンド及び送信データを受取る。これにより、モデ
ム11は)IDLCモードでおることを確識し、信号線
16を介して送信データをHDLCフレーミング部17
に入力しHDLCフレーミングを行なう。HD’LCフ
レーミングをされたデータはメモリ18を経由して変調
部19に送られ、ここで変調された後信号線rを通して
アナログ回路15に入力され、公衆回線14に出力され
る。
The operation of the modem device having such a configuration will be described below. The modem 11 is connected to the modem control device through the signal line 3.
2, it receives an HDLC mode designation command, a data transmission command, and transmission data. As a result, the modem 11 confirms that it is in the IDLC mode, and sends the transmission data to the HDLC framing unit 17 via the signal line 16.
input to perform HDLC framing. The HD'LC framed data is sent to the modulation section 19 via the memory 18, where it is modulated, then input to the analog circuit 15 through the signal line r, and output to the public line 14.

他方、データ受信に際しては、モデム11はモデム制御
装置lOよシ信号線32を介してHDLCモード及び受
信モードのコマンドを受けとシ、受信モードに入る。モ
デム11は次いで、公衆回線14に接続されるアナログ
回路15から信号線ゴを介して受信信号を得る。制御D
 S P 13は復調部加において受信信号を復調した
後、この復調データをHDLCデフレーミング部nでH
DLCデフレーミングを行ない、I10回路12に信号
線nを介してHDLCデフレーミングを行なったデータ
を送り、工10回路12は信号線33を介してモデム制
御回路9に受信データを送る。
On the other hand, when receiving data, the modem 11 receives HDLC mode and reception mode commands from the modem control device 10 via the signal line 32, and enters the reception mode. The modem 11 then obtains a received signal from an analog circuit 15 connected to the public line 14 via a signal line. Control D
After the S P 13 demodulates the received signal in the demodulation section, the demodulated data is sent to the HDLC deframing section n.
DLC deframing is performed and the HDLC deframed data is sent to the I10 circuit 12 via the signal line n, and the I10 circuit 12 sends the received data to the modem control circuit 9 via the signal line 33.

以上のようにして、モデム11においてHDLCフレー
ミングを行なった上でデータの送信が行なわれ、更にH
DLCデフレーミングを行ないつつデータの受信が行な
われるのである。
As described above, data is transmitted after HDLC framing is performed in the modem 11.
Data is received while performing DLC deframing.

発明の詳細 な説明したように、本発明によればモデム内にHDLC
フレーミング部及びデフレーミング部を設け、モデム側
でHDLCフレーミング、デフレーミングを行なうよう
にしたため、モデム制御装置においてハードウェア、ソ
フトウェア上の負担が軽減せしめられ、効率的なデータ
送受信を行なうことが出来るようになる。
As described in detail, according to the present invention, an HDLC is installed in the modem.
Since a framing section and a deframing section are provided and HDLC framing and deframing are performed on the modem side, the burden on hardware and software on the modem control device is reduced, allowing efficient data transmission and reception. become.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるモデム装置の一実施例を示すブロ
ック図、第2図は従来のモデム装置の例を示すブロック
図である。 10・・・モデム制御装置、11・・・モデム、13・
・・制御DSP、14・・・回線、17・・・HDLC
フレーミング部、19・・・変調部、加・・・復調部、
乙・・・HDLCデフレーミング部。
FIG. 1 is a block diagram showing an embodiment of a modem device according to the present invention, and FIG. 2 is a block diagram showing an example of a conventional modem device. 10...Modem control device, 11...Modem, 13.
...Control DSP, 14...Line, 17...HDLC
Framing section, 19...Modulation section, Addition...Demodulation section,
B...HDLC deframing section.

Claims (1)

【特許請求の範囲】[Claims] モデム制御手段を有するモデム制御装置、及び送信用デ
ータにHDLCフレーミング処理をする手段と、このフ
レーミング処理されたデータを変調する手段と、受信デ
ータを復調する手段と、この復調された受信データに対
してHDLCデフレーミング処理をする手段と、を備え
たモデムから成るモデム装置。
A modem control device having a modem control means, a means for performing HDLC framing processing on transmission data, a means for modulating the framed data, a means for demodulating the received data, and a means for demodulating the received data. A modem device comprising a modem and means for performing HDLC deframing processing.
JP63070068A 1988-03-24 1988-03-24 Modem device Expired - Lifetime JPH0775361B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63070068A JPH0775361B2 (en) 1988-03-24 1988-03-24 Modem device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63070068A JPH0775361B2 (en) 1988-03-24 1988-03-24 Modem device

Publications (2)

Publication Number Publication Date
JPH01243639A true JPH01243639A (en) 1989-09-28
JPH0775361B2 JPH0775361B2 (en) 1995-08-09

Family

ID=13420850

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63070068A Expired - Lifetime JPH0775361B2 (en) 1988-03-24 1988-03-24 Modem device

Country Status (1)

Country Link
JP (1) JPH0775361B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09121235A (en) * 1996-09-02 1997-05-06 Matsushita Graphic Commun Syst Inc Facsimile equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6048641A (en) * 1983-08-27 1985-03-16 Nippon Telegr & Teleph Corp <Ntt> Adaptor for communication
JPS62147844A (en) * 1985-12-23 1987-07-01 Ricoh Co Ltd Data communication control system
JPS6330044A (en) * 1986-07-23 1988-02-08 Nec Corp Mode carrier control system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6048641A (en) * 1983-08-27 1985-03-16 Nippon Telegr & Teleph Corp <Ntt> Adaptor for communication
JPS62147844A (en) * 1985-12-23 1987-07-01 Ricoh Co Ltd Data communication control system
JPS6330044A (en) * 1986-07-23 1988-02-08 Nec Corp Mode carrier control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09121235A (en) * 1996-09-02 1997-05-06 Matsushita Graphic Commun Syst Inc Facsimile equipment

Also Published As

Publication number Publication date
JPH0775361B2 (en) 1995-08-09

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