JPH01243167A - Data processor - Google Patents

Abstract

PURPOSE:To eliminate the overhead of a command transfer to a co-processor and to improve the execution performance of a co-processor and command by decoding a command even in the co-processor at the same time as the command decoding of the pipeline processing of an MPU. CONSTITUTION:A co-processor 200 is composed of a command decoder 230 and a co-processor command executing circuit 240, the command decoder 230 receives the command to execute the decoding from a command register 120 of a microprocessor (MPU) 100 through the use of an exclusive-use command transfer bus 250, and when a command decoding start instructing signal 180 is asserted, the decoder 230 decodes the command. As a result, when the command is the command to be executed by the co-processor 200, a decoded result is sent to the co-processor command executing circuit 240, and a processing according to the command is executed. Thus, the overhead can be eliminated, and the processing performance of the co-processor 200 can be improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention mainly relates to a control method for a coprocessor connected to a microprocessor (MPU), and in particular, to eliminate the overhead of command transfer from the MPU and achieve high-speed control. The present invention relates to a coprocessor control method suitable for realizing execution of coprocessor instructions.

[Conventional technology]

In conventional microprocessors (for example, Motorola's MC68020, hereinafter referred to as MPU) to which a coprocessor such as a floating-point arithmetic circuit can be connected externally to the chip, the MPU first reads and decodes instructions for the coprocessor. After that, it was transferred in the form of a command using a bus cycle. For details, see Motorola, M.
C68881 floating point coprocessor
User's Manual (Motorola Inc.
C6888] Floating-PojntCopr
Occessor User's Manual, 198
5).

[Problem to be solved by the invention]

In conventional coprocessors, the computing power of the coprocessor was not very high, so the command transfer time was not as noticeable compared to the computing time. However, recently,
Advances in LSI technology have improved the computing power of coprocessors, and the computing time has become extremely short. However, the time for command transfer using bus cycles has not become much shorter, and as a result, the time for command transfer using bus cycles has become shorter. Overhead has become noticeable.

Therefore, an object of the present invention is to eliminate the above-mentioned overhead, maximize the computing power of the coprocessor, and
An object of the present invention is to provide a coprocessor control method that can further improve processing performance.

[1llll! [Means for Solving the Problem] The above objectives are: (1) an instruction signal for the coprocessor to start decoding instructions at the same time as the MPU; (2) for the MPU or coprocessor to start executing the decoded instructions. (3) a signal to report that execution of an instruction has been completed in the MPU or coprocessor.

[Effect]

MP that performs high-speed data processing by connecting a coprocessor
In U, operations inside the MPU are processed in a pipeline manner. In other words, it is divided into stages such as instruction fetch, instruction decode, and execution, and the next instruction to be executed is processed in advance. As a result, the time required for instruction fetch and instruction decoding is hidden, and it appears that one instruction can be executed using only the execution stage time.

However, if there is an instruction that must be processed by the coprocessor, the pipeline processing described above is disrupted, resulting in instruction fetch, instruction decoding, and command transfer.

The processing stage is command decoding and execution. If the execution time by the coprocessor was long, the time required for command transfer and command decoding was not so much of a problem, but with advances in LSI technology, the execution time has been shortened, and the time required for command transfer and command decoding has become a problem. It has become.

Therefore, when the MPU decodes an instruction, the coprocessor also decodes the same instruction at the same time, and if the instruction is a coprocessor instruction, it is executed in synchronization with the MPU. You can hide time.

Therefore, first, a dedicated means is provided to transfer instructions to be decoded by the M-PU to the coprocessor, and an instruction signal for starting decoding of the transferred instructions is transmitted from the MPU to the coprocessor.

Thereafter, the MPU sends an instruction signal to the coprocessor to start executing the decoded instruction.

At this time, the coprocessor starts executing the decoded instruction if it is a coprocessor instruction. When the execution of the coprocessor instruction is completed, the coprocessor sends an instruction execution completion report signal to the MPU.

This signal instructs the MPU to start the next instruction.

As described above, the MPU and coprocessor perform processing after instruction decoding at the same time, but they operate in synchronization with each other using the instruction decoding start instruction signal, instruction execution start instruction signal, and instruction execution end report signal mentioned above. , there is no need to worry about malfunction.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a data processing device that is an embodiment of the present invention. The data processing device is a microprocessing unit (MPU) 100 and a coprocessor (CP) 200.
and a main memory 300, which are connected to the pass line 4.
Connected with 00. M P' [J 1. OO is a control circuit 110, an instruction register 120, and an instruction decoder 1
30 and an instruction execution circuit 140. Control circuit 110 reads an instruction from main memory 300 and sets it in instruction register 120 . The instruction decoder 130 decodes the instruction set in the instruction register 120 and sends the result to the instruction execution circuit 140. Instruction execution circuit 140
uses this decoding result to execute processing according to the instruction.

Generally, the instruction register 120 serves as a buffer circuit between an instruction reading stage and an instruction decoding stage, and is therefore implemented as a FIFO (first in, first out) type register that can hold a plurality of instructions.

On the other hand, the coprocessor 200 includes an instruction decoder 230 and a coprocessor instruction execution circuit 240.

The instruction decoder 230 receives an instruction to be decoded from the instruction register 120 of the MPU 100 using a dedicated instruction transfer path 250, and receives an instruction signal 180 for starting instruction decoding.
When is asserted, decode the instruction. As a result, if the instruction is an instruction to be executed by the coprocessor, the decoding result is sent to the coprocessor instruction execution circuit 240. Coprocessor instruction execution circuit 240 uses this decoding result to execute processing according to the instruction. Note that in order to synchronize the execution of the MPU and the coprocessor, the MPU control circuit 110 outputs a next instruction execution start instruction signal 150 to the MPU instruction execution circuit 140 and the coprocessor instruction execution circuit 240. ing.

The MPU control circuit 1]-〇 receives a signal 160 from the instruction decoder 130 indicating whether the instruction is to be processed by the MPU or the CP, and determines whether the currently executing instruction is processed by the MPU.
MPU instruction execution end signal 170
is received from the M I) U instruction execution circuit 140 and generates the next instruction execution start instruction signal 150. Also, C.P.
If the CPU is being processed in
A next instruction execution start instruction signal 150 is generated.

FIG. 2 is a time chart showing the state of pipeline processing in the data processing apparatus of this embodiment. MPU10
Since the instruction can be decoded in the coprocessor 200 at the same time as the instruction 0 is decoded, the pipeline processing of the MPU 100 is not disturbed.

FIG. 4(a) is a flowchart showing the processing of the instruction decoder 130 of the MPU 100. Below, the processing of each step will be explained in order.

Process 501: When the instruction decoding start signal 180 is asserted, the process advances to process 502. Process 501 is repeated until then.

Process 502: Decode the command and proceed to process 503.

Process 503: If the decoded instruction is a coprocessor instruction, go to process 505. If not, the process advances to step 504.

Process 504: Send the decoding result to the instruction execution circuit 140 and proceed to process 501.

Process 505: Assert the signal 160 indicating that the decoded instruction is a coprocessor instruction.

Further, FIG. 4(b) is a flowchart showing the processing of the instruction decoder 230 of the coprocessor 200.

Process 511: When the instruction decoding start signal 180 is asserted, the process advances to process 512. Processing 511 is repeated until then.

Process 512: Decode the command and proceed to process 513.

Process 513: If the decoded instruction is a coprocessor instruction, go to process 515. If not, the process advances to process 511.

Process 515: Send the decoding result to the instruction execution circuit 240 and proceed to process 511.

Note that in this embodiment, MP indicates that it is a coprocessor instruction.
Although it is detected by the instruction decoder of U, it may be detected by the decoder on the coprocessor side and reported to the MPU.

FIG. 5 is a flowchart showing the processing of the control circuit 110 of the MPU 100.

Process 520: Assert the instruction decoding start instruction signal 180 and proceed to process 512.

Process 521: Assert instruction execution start instruction signal 150, and proceed to process 522.

Process 522: If the signal 160 indicates a coprocessor instruction, proceed to process 525. If not, go to process 523.

Process 523: Assert the instruction decoding start instruction signal 180, and proceed to process 524.

Process 524: When the MPU instruction execution completion report signal 170 is asserted, the process advances to process 521. Until then, the process 524 is repeated.

Process 525: Assert the instruction decoding start instruction signal 180, and proceed to process 526.

Process 526: Coprocessor instruction execution completion report signal 270
is asserted, the process advances to process 521. Until then, process 5
Repeat step 26.

In this embodiment, the signal 160 is used to select whether to set the instruction execution completion report signal to 170 or 270, but when one of the instruction execution circuits 140 and 240 is processing an instruction, the other If control is performed so that the completion report signal is always negated, the above-mentioned branching of process 522 becomes unnecessary, and process 524 only needs to detect the OR of signals 170 and 270.

FIG. 6 is a time chart showing the states of each signal when a coprocessor instruction is executed next to an MPU instruction. When an instruction is set in instruction register 120, signal 180 is asserted and instruction decoder 130 starts decoding. As a result, it is determined that the instruction is to be processed by the MPU, and a signal 160 is set. After that, the control circuit 110 asserts the signal 150 to instruct the MPU instruction execution circuit 140 to start processing. Also, for the decoder, the signal 18
Assert 0 to instruct decoding of the next instruction. The MPU instruction execution circuit 140 asserts the signal 170 when the processing is completed. In response, control circuit 110 asserts signal 150 to start execution of the next instruction. Here, the next instruction is a coprocessor instruction. Since the instruction decoder 230 of the coprocessor decodes instructions simultaneously with the decoder 130 of the MPU in accordance with the signal 180, when the signal 150 is asserted, the coprocessor instruction execution circuit 240 can immediately execute processing. When processing is completed, signal 270 is asserted to report the completion of instruction execution, so that control circuit 110 can assert signal 150 to begin execution of the next instruction.

As described above, by providing the three signals of the instruction decoding start instruction signal, the execution start instruction signal, and the execution end report signal as in this embodiment, the instruction decoding and execution pipelines of the MPU and coprocessor can be easily synchronized. can be done.

FIG. 3 is a time chart when using the conventional command transfer method. Since commands are transferred to the coprocessor 200 using bus cycles, the coprocessor 200 cannot receive commands until it reaches the execution stage of the MPU 100. Therefore, the coprocessor 200 then decodes the command and
Since execution begins, the MPU 100 is forced to wait during this time, resulting in idle time for pipeline processing.

Although this embodiment does not have a decoded instruction queue, in the case of an MPU that does have one, the present invention can be easily applied by having a decoded instruction queue on the coprocessor side as well. .

Furthermore, in this embodiment, a system is shown in which command decoding on the coprocessor side is completed within the time required for instruction decoding on the MPU side, but command decoding on the coprocessor side is completed within the time required for instruction decoding on the MPU side. If the system does not complete the decoding process, the coprocessor outputs a decoding completion report signal to the MPU control circuit, and the MPU
By waiting for this signal and starting decoding the next instruction, the operations of the MPU and the coprocessor can be easily synchronized.

〔Effect of the invention〕

As described above, according to the present invention, in a data processing device that has a coprocessor outside the MPH and executes some instructions in a program by the coprocessor, the MPH
Since instructions can be decoded in the coprocessor at the same time as instructions are decoded in U's pipeline processing, it is possible to eliminate disturbances in pipeline processing, eliminate the overhead of command transfer to the coprocessor, and improve the execution performance of coprocessor instructions. There is an effect that can be improved.

Also, compared to a coprocessor that monitors the memory bus and simultaneously fetches instructions into the coprocessor when the MPU fetches an instruction, there is no need to have an instruction briefetch queue on the coprocessor side. Another advantage is that a control circuit for managing the brief fetch queue in synchronization with the MPU is no longer required.

Furthermore, in the coprocessor control method described above, MP
If a cache memory (particularly an instruction cache) is built into the U, when reading a coprocessor instruction hits the built-in cache memory, the coprocessor will not be able to read the instruction from the memory bus. According to the present invention, since coprocessor commands can be transferred without using a memory bus, there is an effect that a high-speed coprocessor control method can be provided even in a system in which an instruction cache memory is built in the MPU.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a data processing device that is an embodiment of the present invention, FIG. 2 is a time chart showing the pipeline flow of the data processing device of FIG. 1, and FIG. 3 is a data processing device according to the conventional technology. A time chart showing the pipeline flow of the processing device, FIG. 4(a) shows the MPU instruction decoder 13.
4(b) is a flowchart showing the processing of the coprocessor instruction decoder 230, FIG. 5 is a processing flowchart of the MPU control circuit, and FIG. 6 is the operation of the data processing device of FIG. 1. It is a time chart showing. 100... Microprocessor (MPU), 15
0... Next instruction execution start instruction signal, 160... CP instruction detection signal, 180... Instruction decoding start instruction signal, 20
0...Coprocessor, 230...Coprocessor instruction decoder, 250...Instruction transfer path, 270...c
p instruction execution completion report signal, 300...main memory. 2nd flash 2 rabbits] Broyaden lka (jinr) bud 3 figure 4 kyo (mata) (b) Figure 5

Claims (1)

[Scope of Claims] 1. In a data processing device having a first processing device that mainly operates and a second processing device that operates according to instructions from the first processing device, the first processing device is a processing device that performs pipeline processing that has at least three stages: instruction fetch, instruction decode, and execution, and the first processing device performs pipeline processing that has at least three stages: instruction fetch, instruction decode, and execution.
means for transferring a command to a processing device; the second processing device has means for decoding the command transferred by the transfer means; When a next instruction execution start instruction signal is received from a first processing device and the instruction decoded by the second processing device is an instruction that needs to be processed by the second processing device, the next instruction is executed. A data processing device characterized in that processing of the instruction is started in response to a start instruction signal. 2. The first processing device has means for detecting that the instruction being executed is an instruction executed by the second processing device, and the second processing device has a means for detecting that the instruction being executed is an instruction executed by the second processing device. means for reporting to the first processing device that the processing of the instruction being executed by the processing device has ended, the first processing device:
When the second processing device executes the instruction, the second processing device executes the instruction.
2. The data processing device according to claim 1, wherein the next instruction execution start instruction signal is issued after waiting for an execution completion report signal from the processing device. 3. The first processing device and the second processing device are each a separate chip LSI or a separate board,
3. The data processing apparatus according to claim 1, wherein the data processing apparatus is realized by separate mounting means. 4. The data processing device according to claim 1, wherein the second processing device processes command decoding and command execution in a pipeline manner. 5. The first and second processing devices operate while synchronizing each stage of instruction (command) decoding and instruction (command) execution. data processing equipment. 6. Claim 5, wherein the second processing device receives an instruction signal to start decoding an instruction from the first processing device, and synchronizes the start of instruction decoding with the first processing device.
The data processing device described in Section 1.