JPH01242969A - Signal observing device - Google Patents

Abstract

PURPOSE:To display the time difference between the digitized signal of an analog input signal and a digital input signal visually in a measurable state by storing the digitized signal of an analog input signal and a digital input signal and displaying data in a prescribed period centering on the point of time when prescribed logical conditions are satisfied. CONSTITUTION:The analog input signal 101 is supplied to an A/D converter 2, which sends its output signal to a memory 6 with the prescribed-period clock outputted from an oscillator 1. The digital input signal 103 is supplied to a memory 7 through a switch 8. A control part 4 controls the counting operation of a counter 5 which specifies addresses of the memories 6 and 7 according to the clock from the oscillator 1. A trigger generation part 9 sends out a trigger signal to the control part 4 when the prescribed logical conditions of the signal 103 of a prescribed channel are satisfied according to logical condition data supplied from an MPU 10. The control part 4 allows the counter 5 counts for a prescribed point continuously from said point of time, and then stops it and reports the stop to the MPU 10. The MPU 10 reads data out of the memories 6 and 7 during this period and send them out to a CRT 11, where the data are displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a signal observation device suitable for observing a time difference between an analog input signal and a digital input signal.

(Prior Art) Synchronoscopes and digital memory synchroscopes are known as conventional devices for observing analog input signals, while logic analyzers are known as devices for observing digital input signals. However, when detecting the time difference between a digital signal and an analog signal by observing the signal waveform of each part of an electronic device that handles both analog and digital signals, it is necessary to process the analog input signal and digital input signal, and then There was no signal observation equipment that could visually display the time difference in a measurable manner.

(Problems to be Solved by the Invention) As described above, in conventional signal observation devices, the one that handles digital input signals and the one that handles analog input signals are separate; The emergence of a signal observation device that can measurably and visually display the time difference with the input signal has been awaited.

The present invention was made based on such a need, and its object is to provide a signal observation device that visually displays the time difference between an analog input signal and a digital input signal in a measurable manner.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides an A/
A D converter, a storage means in which data is stored, and a surface A/
storage control means for storing the digital signal output from the D converter and the digital input signal in the storage means; display means for displaying the input signal; and detection means for detecting that a predetermined logical condition is satisfied regarding the input signal. a trigger generating section that generates a trigger signal, the trigger providing data stored in the storage means to the display means in response to input signals for a predetermined period before and after the trigger signal generated by the trigger generating section; The signal observation device is provided with display control means for causing the display means to display the waveform of the input signal for a predetermined period before and after the generation of the trigger signal.

(Function) According to the above configuration, the digital signal obtained by digitizing the analog input signal and the digital input signal are sampled by the storage control means and stored in the storage means, and a trigger signal is generated when a predetermined logical condition is satisfied. Then, data for a predetermined period before and after this timing is successively outputted from the storage means and displayed based on the data, so that the analog input signal and the digital input signal are displayed.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. In this signal observation device, an analog input signal arrives via signal lines 101 and 102, and an A/D converter (ADC) 2.
given to 3. The A/D converters 2 and 3 digitize the input signal using a clock of a predetermined period output from the oscillator 1 and output the digitized signal. The output signal of the A/D converter 2 is output to a memory 6 that can be read and written, and the output signal is output to the A/D converter 3.
The output signal is outputted to a writable and readable memory 7 via a switch 8. A digital input signal is given to the switch 8 via the bus 103, and the switch 8
A control signal sent from U 10 selects either the digital input signal or the signal digitized by A/D converter 3 and supplies it to memory 7 . Reference numeral 4 indicates a control unit that controls writing of data into the memory 6.7. This control unit 4 controls the memory 6.7 based on the clock output from the gestational device 1 via the signal line 105.
Controls the increment of the counter 5 which specifies the address. 9
indicates a trigger generation section, and this trigger generation section 9 is an MPLI
Based on logical condition data given from IO, bus 10
3, detects whether a predetermined logic condition of the digital input signal of a predetermined channel is satisfied or not, and when it is detected that the predetermined logic condition is satisfied, sends a trigger signal to the control unit 4 via the signal line 104. Send. From this point on, the control unit 4 that has received the trigger signal continues to increment the counter 5 for a predetermined period of time, then stops the increment, and notifies the MPU of the stop.
Notify l0. The MPU 10 is a microcomputer, and in addition to performing the above-mentioned operations of controlling each section via the bus 105, it starts the control section 4 and receives a notification from the control section 4 that the counter 5 has stopped, and starts processing the memory. The data in 6.7 is read and applied to the CRT display unit 11. C
The RT display unit 11 visually displays the input signal based on the provided data. In addition, this signal observation device is provided with an operation panel unit (not shown), and based on the key operation, logical condition data to be set is sent to the MPU 10.
Data indicating which one of the analog input signal on signal line 102 and the digital input signal on bus 103 should be selected is input.

In the signal observation device configured in this way, the MPU 10 sets logical condition data to the trigger generation section 9 based on input from the operation panel section as described above, and then provides a control signal to the switch 8. to control switching.

First, a case will be described in which the output signal of the A/D converter 3 is selected by the switch 8. Analog input signals arriving via signal lines 101 and 102 are digitized by A/D converters 2 and 3 and provided to memory 6.7. Prior to this, the control unit 4 is activated from MPU10,
The counter 5 is controlled to designate the address of the memory 6.7. Therefore, the digitized data is stored in the memory 6.7 one after another by incrementing the counter 5.

The digitized data is, for example, 8 bits and corresponds to the digital input signal ach.

The data is stored in this way, and at a predetermined time, the trigger generating section 9 detects that the logical condition is satisfied.

Here, the logical condition is a condition such as when the digital input signal A of a certain channel becomes H level and the digital input signal B of another certain channel becomes H level, or the condition that the digital input signal of a certain channel @ The condition is such that A rises for the nth time. When the trigger generation unit 9 detects a logical condition, the signal line 1
A trigger signal is given to the control section 4 via the control section 04. Then, the control unit 4 continues to increment the counter 5 for a predetermined period of time, and then stops the increment, and sends a notification to the MPU 10 to the effect of the stop.
will be notified. At this time, the memory 6.7 stores signal lines 101 for a predetermined period before and after the trigger signal is generated,
The digitized data of the analog input signal via 102 will be stored in the memory 6.7. Here, the MPLIIO takes out the stored data from the memory 6.7 and sends it to the CRT display unit 11 to display the analog input signal. As a result, as shown in FIG. 2, the trigger signal is generated at the time tr1.
The display of analog signals arriving from the signal lines 101 and 102 during a predetermined period before and after is displayed on the CRT display unit 1.
1 is displayed. Specifically, since 8-bit (or 16-bit, etc.) data is stored in the memory 6.7 by one sampling, data indicating this point is connected and displayed as a signal waveform. In FIG. 2, the analog signal suddenly starts to rise after time ti, t2 has passed from the trigger signal generation time t, 1, and the signal line 1
It can be observed that ringing, as indicated by the IR, occurs in the analog signal sent via 01. still,
Trigger signals shown in parentheses are not displayed on the CRT display unit 11.

Next, a case where the bus 103 is selected by the switch 8 will be explained. In this case, the same operation as described in FIG. 2 is performed except that the digital input signal is stored in the memory 7. Then, when the digital input signal is 3ch, a trigger signal is generated at the time point tr2 when the input signal A falls. Data for a predetermined period before and after this point ↑r2 is collected. A display as shown in FIG. 3 is displayed on the CRT display section 11, and the analog signal on the signal line 101 reaches its peak value three times after the fall of the digital input signal A, and the analog signal on the signal line 101 reaches its peak value after the rise of the digital input signal C. It can be observed that the digital input signal B rises before time t4, and that the same signal falls at time ↑5 after the rise of digital input signal C.

There's a problem here. That is, the analog input signal and the digital input signal have different storage delay times until they are stored in the memory 6.7. For example, excavator 1
Assume that the analog input signal has a storage delay time of 100, +3 clocks, and the digital input signal has a storage delay time of 50, +1 clock, and the tallock period of excavator 1 is 100 ns, based on the clock output from the excavator 1. , the analog input signal is 1001. +3 xlOOn5 = 400 ns Digital input signal is 50n, +1 xlOO, = 150 ns
Since it has a storage delay time of t2. t3
When observing and measuring the
It is necessary to perform calculations taking into account that there will be a delay of 400 ns if the delay is delayed by 400 ns.

In this embodiment, the analog input signal is 2ch, and the digital input signal is 8ch or 16ch, but the present invention is not limited to these.

[Effects of the Invention] As explained above, according to the present invention, the data obtained by digitizing the analog input signal and the data of the digital input signal are stored in the storage means, and the data is stored for a predetermined period before and after a predetermined logical condition is satisfied. data is given from the storage means to the display means, so that the display means displays the analog input signal and the digital input signal, making it possible to measure the time difference.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are waveform diagrams showing waveforms displayed by the embodiment of the present invention. 1... Oscillator 2, 3... A/D converter 4.
...Control unit 5...Counter 6.7...Memory 8...Switcher 9...Trigger generator 10...
・MPU11...CRT Display Department Representative Patent Attorney Nori Ken Yudo Sanno - Figure 1 Zumon"J "2"-11"-111111211't,'ts No. Figure 3-] "Public"

Claims (1)

[Claims] an A/D converter that digitizes an analog input signal;
a storage means for storing data; a storage control means for storing a digital signal output from the A/D converter and a digital input signal in the storage means; a display means for displaying the input signal; a trigger generation section that detects that a predetermined logical condition has been satisfied and generates a trigger signal; and display control means for supplying data to the display means to cause the display means to display the waveform of the input signal for a predetermined period before and after the generation of the trigger signal.