JPH01241642A - Dynamic arranging method for common memory - Google Patents

Abstract

PURPOSE:To effectively utilize the address space of a common memory by allowing the size of the common memory not to be a fixed size, allocating an idle space in the common memory according to the size of transfer data and on the other hand, releasing the area when the transfer of the data is ended. CONSTITUTION:The data transfer is executed through a common memory 3 between a main processor 1 and plural I/O processors 2A-2N, the size of the common memory is not made the fixed size and the idle space in the common memory 3 is allocated according to the size of the transfer data. On the other hand, when the data transfer is ended, the area is released. Thus, in the common memory control part of an OS for both the main processor 1 and I/O processors 2A-2N, function is obtained to dynamically manage the memory. Namely, in correspondence to the contents of a data transfer request, processing is executed to lend an occupational memory size, which is not presently used, from the arbitrary area of the common memory 3 and processing is executed to cancel (release) the occupying memory size after the end of the request. Thus, the using efficiency of the common memory 3 can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a main processor and a plurality of input/output control processors (input/output control processors) or a ranal multiprocessor system, particularly a main processor and a plurality of I10 processors. Concerning a method for dynamically arranging common memory shared by

[Conventional technology]

Generally, in a multiprocessor system, as shown in FIG. 5, main processor 1 and I10 processor 2 (2A
~2D) transfers data via a memory 3 called common memory that is accessible from both the main processor and the I10 processor. This common memory 3 is normally allocated to a continuous address space υ on the main processor side, but the continuous address space is generally equally divided for each I10 processor as shown in FIG. Therefore, each I10 processor accesses the divided area as its own address space. The operating systems (O8) of both the main processor and the I10 processor manage the common memory.

For example, from the main processor to I for auxiliary storage
The case where a data READ request is made to the 10 processors will be explained with reference to FIG.

First, the main processor O8 stores a READ request command in the common memory allocated to the requesting I10 processor 2, and generates an interrupt.

When this interrupt is received, O8 of the I10 processor sends a READ request to the external device (in this case, the auxiliary storage device).
After performing the processing specified by the request command and storing the read data in the common memory, a request is issued to the main processor 1 by interrupt.

At this time, assuming that the read data length is 100 KB (kilohydride) and the common memory allocated to one I10 processor is 4 KB, it is obvious that data division (blocking) is not necessary. will be divided into 25 parts. This blocking naturally requires O8 software overhead (processing) time. This overhead time usually takes several tens of times longer than the transfer time between main memory and common memory, so in order to achieve high-speed data transfer, it is necessary to minimize the overhead time. There is a need to keep it to a minimum. Therefore, a method to reduce the number of pushing
That is, it is necessary to increase the size of the common memory allocated to the I10 processor.

Furthermore, regarding the I10 processor that performs auxiliary storage, image control, etc., as described above, the larger the common memory is, the better, in order to transfer a large amount of data. However, I
Depending on the type of LO, there are I10 processors that can only process data of about 100 IWORD axes at a time.

[Problem to be solved by the invention]

However, in the conventional method, it is common to allocate memory equally to each I10 processor, so in some cases data is frequently blocked, and on the other hand, common memory is not used and is wasted. This results in inefficient management, with some parts of the world still having problems.

Therefore, it is an object of the present invention to provide a method that allows efficient use of common memory.

[Means to solve the problem]

When data is transferred between a main processor and a plurality of I10 processors via a common memory, the size of the common memory is not fixed, and free areas in the common memory are allocated according to the size of the data to be transferred. On the other hand, when the data transfer is completed, processing is performed to release the area.

[Effect]

A function to dynamically manage memory in the O8 common memory control unit of both the main processor and I10 processor, that is, according to the content of the data transfer request, the currently unused occupyable memory size is transferred from any area of the common memory. The usage efficiency of the common memory is improved by performing the process of borrowing the memory area, and the process of releasing (releasing) the occupied memory area after the request is completed.

〔Example〕

FIG. 1 is an explanatory diagram for explaining the common memory initialization method according to the present invention, FIG. 2 is an explanatory diagram for explaining the common memory borrowing procedure according to the present invention, and FIG. 3 is an explanatory diagram for explaining the common memory borrowing procedure according to the present invention. These are explanatory diagrams for explaining a memory release procedure, and the present invention will be described below with reference to these diagrams.

The main processor O8 communicates with the I10 processor through common memory and interrupt signals, and which I10 processor is connected to the system (turns on) can be determined by inputting an interrupt signal from the I10 processor when the power is turned on. The interrupt signal is used to determine the interrupt signal. As shown in FIG. 6, the common memory immediately after the power is turned on is equally allocated to each l10-nit unit, and each unit is initialized using this area. After the initialization of the unit is completed, the main processor O8 clears the entire area of the common memory and initializes it as shown in FIG. Thereby, the common memory is managed based on the common memory information (header) 31 shown in the figure, with the minimum unit (block) being, for example, 16 bytes. As shown in FIG. 1, this header 31 is composed of a currently vacant block size (block number) area 31A, a next vacant block first block number area 31B1, and a next vacant block number area 31C. The main processor O8 checks the free space in the common memory based on this information, issues a borrow request, and occupies the space. Therefore, initially any area in FIG. 1 is occupied. However,
If the amount of data to be transferred at this time is larger than the capacity of the free area, an area of an appropriate size is allocated and blocking is performed. Further, a header 31 is attached to the next vacant block position of the occupied area.

Here, when the current common memory occupancy state is as shown in FIG. 2 (a), when the main processor O8 occupies the common memory in order to execute the request,
A free block is searched from the beginning using the header 51, and its size is checked to determine whether the requested size is satisfied. If there is an area that satisfies the request, as shown in FIG.
), occupy this. On the other hand, if the area that satisfies the request is insufficient, an area of an appropriate size is allocated and locking is performed in the same way as above. At this time, the header 31 is attached and replaced in the same manner as described above. In this way, the common memory is dynamically allocated, but the information on the common memory size for the I10 processor side is stored at the beginning of the area as shown in Figure 2 (b).
Store it like this.

Based on this information, the I10 processor recognizes the size currently allocated to itself and accesses the common memory.

After the data transfer is completed, the area is released by performing the opposite operation to the above. For example, the borrowed area shown in FIG. 3(A) is cleared, and the header position is moved to the position shown in FIG. 3(B).

The main processor performs read/write (R/W) on the common memory operated in this way using a hardware select signal, but the select signal is processed by a select signal generation circuit as shown in Figure 4, for example. Created.

This select signal generation circuit is composed of a comparison/selection section 5, a register 6, a decoder 7, etc., and by setting the address and size data of each of the 10 units in the register 6, the signal can be generated via an address bus. A selection signal is generated by determining whether the viewed address falls within the range set in the register 6 in the comparison/selection unit 5.

〔Effect of the invention〕

According to the present invention, it is possible to dynamically allocate common memory, which not only eliminates the common memory blocking that was frequently done in the past, but also eliminates wasted memory areas that are not used, resulting in improved efficiency. The advantage is that good data transfer is possible.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram for explaining the common memory initialization method according to the present invention, FIG. 2 is an explanatory diagram for explaining the common memory borrowing procedure according to the present invention, and FIG. 5 is an explanatory diagram for explaining the common memory borrowing procedure according to the present invention. 4 is a block diagram showing a specific example of a select signal generation circuit, FIG. 5 is a block diagram showing a general example of a multiprocessor system, and FIG. 6 is a common memory FIG. 7 is an explanatory diagram for explaining a data transfer method in a multiprocessor system. Code explanation 1... Main processor, 2 (2A to 2N).
......Eng 10 processor, 3...Common memory, 31...Header, 51A...Free block size area, 51B...Previous Free block number area, 31C... Next free block number area, 4... Internal path, 5 (5A to 5N)...
. . . Comparison and selection section, 6 (6A to 6D) . . . Register, 7 . . . Decoder. Agent Patent Attorney Akio Namiki Agent Patent Attorney Kiyoshi Matsuzaki 1 Figure wi 2 Figure 31111 115 Figure Front 6- (↑64KB) Wealth 7m!

Claims (1)

[Claims] When data is transferred between the main processor and multiple input/output processors that make up a multiprocessor system via a common memory, the size of the common memory is not set to a fixed size. 1. A method for dynamically arranging a common memory, which is characterized in that the address space of the common memory is effectively utilized by allocating a vacant area and releasing the area when data transfer is completed.