JPH01236494A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten the development period of a memory, etc., with a logical function including a delaying circuit by providing a delay circuit to change a delaying time in accordance with a selecting control signal supplied from a prescribed pad or an external terminal. CONSTITUTION:A delay circuit DL1 included in a writing pulse generating circuit, etc., of a memory with a logical function is composed of plural unit delay circuits DC1-DC8 which are a serial mode, and output selecting circuits SEL1 and SEL2 to selectively communicate the output signal of these unit delay circuits DC1-DC8 in accordance with the selecting signal and decoders DEC1 and DEC2 to decode a prescribed selecting control signal and form alternatively a selecting signal are provided. Consequently, after a partially fabricated item or a product is completed, a selecting control signal is supplied from the pad or the external terminal, and without needing the change of a mask, etc., the delay time of the delay circuit can be adjusted. Thus, the development period of the memory, etc., with a logical function is shortened and the product yield can be increased.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and relates to a technique that is particularly effective when applied to, for example, a memory with a logic function whose basic configuration is a bipolar RAM. It is.

[Conventional technology]

There is a bipolar RAM that has a basic configuration of a memory array in which memory cells made of bipolar transistors are arranged in a grid pattern. There is also a logic machine memory which has such a bipolar RAM as its basic configuration.

Regarding bipolar RAM, for example, Japanese Patent Application Laid-open No. 1983. −
It is described in Publication No. 60487 and the like.

(Problems to be Solved by the Invention) The bipolar RAM as described above includes a write amplifier, and the write amplifier includes a plurality of unit circuits provided corresponding to complementary data lines forming the memory array. These unit circuits are selectively activated in accordance with write pulses supplied from the timing generation circuit, and perform write operations on selected memory cells of the memory array.

In the memory with logic function including the bipolar RAM described above, the write vI multiplier signal, ie, the write enable signal WE, inputted from the outside is directly supplied to the write amplifier as a write pulse. Therefore, the write enable signal WE must have a predetermined set amplifier time for address signals, input write data, etc., and a predetermined pulse width that allows the write amplifier to operate stably. These timing conditions for the write enable signal WE are becoming increasingly strict and difficult to implement as memory with logic functions becomes faster and its cycle time becomes shorter.

In order to deal with this, the inventors of the present invention have developed a memory with a logic function that synchronizes its input operation with a clock signal and autonomously forms a write pulse that satisfies the above timing conditions internally.

This memory with logic function includes a timing generation circuit,
This timing generation circuit includes a write pulse generation circuit that selectively forms a write pulse having a predetermined setup time and a predetermined pulse width based on the clock signal according to a write enable signal WE.

However, the inventors of the present invention have discovered that such a memory with logical functions has the following problems. That is, the write pulse generation circuit of the memory with logic function includes a plurality of delay circuits for realizing the set-up time and pulse width by delaying the clock signal and widening the pulse width. The circuit constants of the circuit are determined by simulation and the like performed at the design stage of the memory with logic functions so that the circuit has a predetermined delay time that satisfies the above-mentioned timing conditions. However, at present, the precision of the simulator delay is not sufficient, so it is difficult to ensure that the yl delay circuit of a manufactured memory with logic functions has a precisely predicted and stable delay time. For this reason, a method is adopted in which a predetermined delay time is obtained by preparing several delay circuits for adjustment in advance, changing the mask for manufacturing, and selectively switching and connecting these delay circuits. This increases the development period for a memory with logic functions, etc., and causes a decrease in product yield in a mass production process.

An object of the present invention is to provide a delay circuit whose delay time can be changed. Another object of the present invention is to shorten the development period of a memory with logic functions including a delay circuit, and to increase the product yield in the mass production process.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the delay circuit included in the write pulse generation circuit of the memory with logic function is composed of a plurality of unit delay circuits connected in series, and the output signals of these unit delay circuits are selectively transmitted according to the selection signal. and a decoder that decodes a predetermined selection control signal to selectively form the selection signal.

[For production]

According to the above-mentioned means, by supplying the selection control signal from the pad or external terminal after the semi-finished product or finished product, there is no need to change the mask etc.
The delay time of the delay circuit can be adjusted. This makes it possible to shorten the development period for a memory with logic functions, etc., and increase the product yield.

〔Example〕

FIG. 4 shows a block diagram of an embodiment of a memory with logical functions to which the present invention is applied.

Although the memory with logic function of this embodiment is not particularly limited, the basic configuration is a bipolar RAM, and the circuit elements constituting each block in FIG. 4, including a logic section (not shown), are as follows:
Although not particularly limited, it is formed on one semiconductor substrate such as single-crystal silicon together with circuit elements constituting a logic section (not shown) of the memory with logic functions.

As described later, the memory with logic function of this embodiment includes a memory array MARY, a write amplifier WA, and a timing generation circuit TG.
G autonomously forms a write pulse, that is, a timing signal φW6, having a predetermined cent-up time and pulse width in accordance with a clock signal CK and a write enable signal WE supplied via an external terminal, as will be described later. The IF write pulse generation circuit, including the write pulse generation circuit that supplies the WA, includes two sets of delay circuits DLI and DL2 each consisting of a plurality of unit delay circuits connected in series, and each unit i! ! The write pulse generation circuit, which includes output selection circuits 5EL1 and 5EL2 that selectively transmit output signals of the extension circuits according to selection signals wO to w7 or sO to s3, further receives a selection control signal, that is, supplied via an external terminal. Pulse width selection signal WSO~
Decoders DEC1 and DEC2 are included which decode WS2 and set-up time selection signals SS0, 531 and form the selection signals wQ-w7 and sO~33. As a result, the memory with logic function of this embodiment can adjust the delay time of the delay circuits DLI and DL2 included in the write pulse generation circuit without changing the mask after a semi-finished product or a completed product. Pulse width and set amplifier time can be optimized.

In FIG. 4, the memory array MARY is m+1 arranged in parallel in the horizontal direction of the figure, although it is not particularly limited.
m+1 arranged vertically parallel to the word line of the book
(m+1) x (n+1) arranged in a grid at the intersections of these word lines and complementary data lines.
fi bipolar memory cells.

Word lines constituting memory array MARY are coupled to address decoder AD and are alternatively brought into a selected state.

Address decoder AD is supplied with internal address signal aoxal from address buffer ADB. Although not particularly limited, these internal address signals are complementary signals consisting of a non-inverted signal and an inverted signal. The address decoder AD is further supplied with a signal from a timing generation circuit TG.
A timing signal φce is supplied.

Address decoder AD is selectively brought into operation when the timing signal φce is set to a high level. In this operating state, address decoder AD decodes the internal address signals aO to ai and selectively selects the corresponding word line of memory array MARY.

Address buffer ADB takes in and holds address signals AO to At of l+lBe/) supplied via external terminals, although this is not particularly limited.

Also, based on these address signals A O-A i,
The internal address signals aO to ai are formed and supplied to the address decoder AD.

On the other hand, the complementary data lines constituting the memory array MARY are each coupled to the corresponding unit circuit of the write amplifier WA on one side, and are respectively coupled to the corresponding unit circuit of the read amplifier RA on the other side.

Although not particularly limited, the write amplifier WA is provided corresponding to each complementary data line of the memory array MARY.
These unit circuits including i+1 unit circuits are supplied with corresponding internal write data dwQ to dwn from the data input buffer sofa DIB, respectively. Further, a write pulse, that is, a timing signal φWe, is commonly supplied from the timing generation circuit TG. timing signal φw
As will be described later, when the memory with logic function is in a non-selected state, e is set to a low level, and when the memory with logic function is in a selected state in write mode, it is temporarily set to a low level for a predetermined period at a predetermined timing. It is considered to be at the 1st level.

Each unit circuit of the write amplifier WA is selectively put into an operating state by setting the timing signal φwe to a high level. In this operating state, each unit circuit of the write amplifier WA forms a complementary write signal according to the internal write data dwO to dwn supplied from the data input buffer sofa DIB, and supplies it to the corresponding complementary data line of the memory array MARY. . These write signals are transmitted to n+1 memory cells coupled to the selected word line of memory array MARY via corresponding complementary data lines, respectively.

The data input cover sofa DIB takes in and holds input data DIG to Dln of fi+l bits supplied via an external terminal, although this is not particularly limited. Also, based on these input data DIG-Dln, the internal write data dwo-dwn are formed and supplied to corresponding unit circuits of the write amplifier WA, respectively.

Read amplifier RA amplifies read signals output from n+1 memory cells coupled to a selected word line of memory array MARY via corresponding complementary data lines, and forms internal read data drO to drn. .

These internal read data dro-drn are supplied to corresponding output circuits of the data output buffer DOB.

The data output buffer DOB is f
These output circuits include i+1 output circuits, 1,
Corresponding internal read data d from read amplifier RA
ro to drn are respectively supplied, and a timing signal φos is commonly supplied from the timing generation circuit TG.

Each output circuit of the data output buffer DOB is selectively put into an operating state by temporarily setting the timing signal φOS to a level of 1. In this operating state,
Each output circuit of the data output buffer DOB forms output data DOO-DOn based on the corresponding internal read data dro-drn, and sends it out via an external terminal. When the timing signal φ06 is set to a low level, the output of each output circuit of the data output buffer DOB is set to a high impedance state.

The timing generation circuit TG forms the various timing signals described above based on the clock signal CK and write enable signal WE supplied via external terminals, although not particularly limited thereto, and supplies them to each circuit. Timing generation circuit TO
includes a write pulse generation circuit that forms the timing signal φwe, and this write pulse generation circuit includes two delay circuits DLI and DL2 in which a plurality of unit delay circuits are connected in series, as described above. , the delay times of these delay circuits are selectively changed according to pulse width selection signals WSO to WS2 and set-up time selection signals SSO and SSI supplied via external terminals.

FIG. 1 shows a circuit diagram of an embodiment of the timing generation circuit TG of the memory with logic function of the fourth WJ. Further, FIGS. 2 and 3 show circuit diagrams of an embodiment of a unit delay circuit DCI and a delay gate circuit DGI included in the timing generation circuit TG of FIG. 1. Referring to these figures, the specific structure and operation of the write pulse generation circuit included in the timing generation circuit TG of the logic a burn memory of this embodiment will be explained. Furthermore, in Figure 1,
Of the timing generation circuit TG, the signature pulse generation circuit and its related circuits are partially shown, but the other circuits of the timing generation circuit TG are not directly related to this invention, so explanations are omitted. do. In the diagram below,
The illustrated bipolar transistors are all NPN type transistors.

In FIG. 1, a clock signal CK input through an external terminal is supplied to one input terminal of an OR gate circuit OGI, and is also supplied to a clock input terminal C of a flip-flop circuit FFI. OR gate circuit OGI
The output signal of the AND gate circuit AGI is supplied to the other input terminal of the AND gate circuit AGI.The internal control signal t m c is supplied to one input terminal of the AND gate circuit AGI, and the other input terminal of the AND gate circuit AGI is supplied with the output signal of the AND gate circuit AGI. An inverted output signal n5 of an OR gate circuit OG2, which will be described later, is supplied. OR gate circuit OGI
The output signal of is supplied to the input terminal of the pulse widening circuit PWE. Here, the black signal CK is set to the ECL level, although it is not particularly limited, and is temporarily set to the no level for a predetermined period at a predetermined cycle. Further, the internal control signal t m c is set to a low level when the memory with logic function is placed in a normal operation mode, and is selectively set to a high level when the memory with logic function is placed in a predetermined test mode, although it is not particularly limited. level.

For these reasons, when the logic TA enabled memory is placed in the normal operation mode, the clock signal CK supplied via the external terminal is transmitted to the pulse widening circuit PWH via the OR gate circuit OG1.

Further, when the memory with logic function is in a predetermined test mode and the internal control signal t m c is set to high level, the inverted output signal n5 of the OR gate circuit OG2 is pulsed through the AND gate circuit AGI and the OR gate circuit OGI. The signal is transmitted to the pulse widening circuit PWE, and an oscillation loop including the pulse widening circuit PWE and the delay circuit DLI is formed.

Write enable signal WE supplied via external terminal
is supplied to the data input terminal of the flip-flop circuit FFI. As described above, the clock signal GK is supplied to the clock input terminal C of the flip-flop circuit FFI. As a result, the flip-flop circuit FFI
is triggered by the clock signal CK and takes in the write enable signal WE. Although not particularly limited, the write enable signal WE is selectively set to a high level when the memory with logic function is in write mode. The output signal of the 79717071 circuit FFI is supplied to each circuit of the timing generation circuit TG as a write mode signal, that is, an internal control signal wm.

On the other hand, a 3-bit pulse @selection signal WSO to WS2 supplied via an external terminal as a selection control signal is input to the decoder DECI. The decoder DEC1 decodes the pulse width selection signals WSO to WS2 and selectively sets the corresponding selection signals WO to W7 to a high level. These selection signals are supplied to control input terminals g of corresponding delay gate circuits DCI to DC8 of delay circuit DLI, which will be described later.

Similarly, the 2-bit seven node up time selection signals sso and S are supplied via external terminals as selection v control signals.
S1 is supplied to decoder DEC2. Decoder DE
C2 is the set-up time selection signal SSO and SS.
I is decoded, and the corresponding selection signals SO to s3 are alternatively set to high level. These selection signals are applied to the corresponding ant game 1-circuit AG of the output selection circuit 5EL2, which will be described later.
2 to AG 5, respectively.

Although not particularly limited, the pulse widening circuit PWE delays the clock signal CK etc. supplied via the OR gate circuit 001 by a predetermined time and widens the pulse width by about three times. The non-inverting output signal nl and the inverting output signal 1T of the pulse widening circuit PWH are supplied to the non-inverting input terminal i and the inverting input terminal i of the unit delay circuit DCI constituting the delay circuit DLI, and are also supplied to the OR gate circuit OG2.
is supplied to the first input terminal of.

The delay circuit DLI includes, but is not particularly limited to, four unit delay circuits configured in series by sequentially coupling the non-inverting output signal O and the inverting output satin τ with the non-inverting input terminal 1 and the inverting input terminal T. It is composed of DCI to DC4 and eight delay gate circuits DG1 to DG8.

The unit delay circuits DCI to DC4 have a basic configuration of a pair of differential transistors T1 and T2, as represented by the unit delay circuit DCI in FIG. 2.

Among these, the collector of the transistor Tl is connected to the node na
and is coupled to the ground potential of the circuit via a corresponding load resistor R1. Similarly, the collector of transistor T2 is connected to node nb and connected to the ground potential of the circuit via a corresponding load resistor R2. Differential transistor T1・
A constant current source 151 is provided between the commonly coupled emitters of T2 and the power supply voltage of the circuit. Here, the power supply voltage of the circuit is not particularly limited, but is set to a predetermined negative power supply voltage. The bases of the transistors T1 and T2 are the non-inverting input terminal i and the inverting input terminal T of this unit delay circuit DCI, respectively.

- The collector of transistor T1 is further commonly coupled to the base of transistor T4. Further, a capacitor C1 is provided between the collector of the transistor TI and the ground potential of the circuit. Similarly, the collector of transistor T2 is further commonly coupled to the bases of transistors T3 and T5. Further, a capacitor C2 is provided between the collector of the transistor T2 and the ground potential of the circuit. Although capacitors C1 and C2 are not particularly limited,
It is formed by the emitter capacitance of a bipolar transistor and is designed to have a predetermined capacitance corresponding to the delay time of the unit delay circuit DCI.

The collector of transistor T3 is coupled to the ground potential of the circuit, and a constant current source IS2 is provided between its emitter and the power supply voltage of the circuit. As a result, the transistor T
3 constitutes an output limiter follower circuit together with the corresponding constant current source S2. The emitter of transistor T3 is coupled to non-inverting output terminal 0 of unit delay circuit DCI.

Similarly, the collectors of transistors T4 and T5 are coupled to the circuit ground potential, and between their emitters and the circuit power supply voltage are constant current sources 133 and ! S4 is provided respectively. Thereby, the transistors T4 and T5, together with the corresponding constant currents ii I S 3 and 154, respectively constitute an output limiter follower circuit. The emitter of transistor T4 is coupled to the inverting output terminal i of this unit delay circuit DCI. Further, the emitter of the transistor T5 is coupled to the wired-OR output terminal W of this unit delay circuit DCI. The wired OR output terminal W of each unit delay circuit is directly coupled to the wired OR output terminal W of another unit delay circuit, thereby forming a wired OR circuit.

When the non-inverting input terminal l is set to a low level lower than the inverting input signal i, the transistor T2 is turned on and the transistor T1 is cut off. therefore,
The potential of the collector of the transistor Tl, that is, the node na, is set to a high level such as the ground potential of the circuit, and the potential of the collector of the transistor T2, that is, the potential of the node nb is determined by the '21 current value of the constant current source 131 and the resistance value of the load resistor R2. It is set to a predetermined low level determined by. The high level of the node na is shifted by the base Emink voltage of the transistor T4 and then output as an inverted output signal of the unit delay circuit DC1. Further, the low level of the node nb is shifted by the base-emitter voltage of the transistors T3 and T5, and then the unit delay circuit DCI
A non-inverted output signal 0 and a wired-OR output signal W are obtained.

Next, when the non-inverting input terminal 1 is set to a high level higher than the inverting input terminal i, the transistor T2 goes into a cut-off state, and the transistor T1 tries to turn on instead. Along with this, the potential of the node na changes from a high level to the current value of the constant current source 151 and the load resistance R1.
The potential of the node nb changes from a low level to a high level such as the ground potential of the circuit. However, as described above, capacitors CI and C2 each having a predetermined capacitance are provided between the nodes na and nb and the ground potential of the circuit. Therefore, the levels of nodes na and nb are equal to the capacitance of capacitor C1 and the constant current? Current value of Btst, capacitance of capacitor C2, and load resistance R
2 gradually changes according to a predetermined time constant determined by the resistance value of transistors T1 and T2, and the states of transistors T1 and T2 change accordingly. As a result, the non-inverted output signal O, the inverted output signal τ, and the wired-OR output signal W of the unit delay circuit Del are changed with a delay of a predetermined delay time with respect to the non-inverted input signal i and the inverted input signal i. becomes.

On the other hand, the delay gate circuits DCI to DG8, as represented by the delay gate circuit DGI in FIG. It functions as a unit delay circuit that constitutes the DLI. In FIG. 3, transistors T6 to TIO
and resistance 1?3. R4, capacitors C3 and C4, and constant current source! 85 to IS8 are transistors T1 to T5, resistors R1 and R2, and capacitors CI and C2 in FIG.
and constant currents axst to IS4, respectively. The collectors of transistors T6 and T7 are nodes nc and nd, respectively, and the bases of transistors T6 and T7 are connected to delay gate l?, respectively. 1lv14D
Let the non-inverting input terminal 1 and the inverting input terminal of G1 be below,
Hereinafter, explanations will be added regarding different parts of the unit delay circuits DC1 to DC4' and the delay gate circuits DG1 to DG8.

In FIG. 3, the commonly coupled emitters of differential transistors T6 and T7 are coupled to the collector of transistor T11. The emitter of the transistor Tll is commonly coupled to the emitter of the differential transistor T12, and further coupled to the power supply voltage of the circuit via a constant current source 135. The collector of transistor T12 is connected to node n
d, and its base is the control input terminal g of this delay gate circuit DGI. Transistor Tll
A predetermined reference potential VBB is supplied to the base from a constant voltage generation circuit (not shown) of the logic machine memory.

Here, the reference potential VilB is set to approximately an intermediate level between the low level and the high level of the selection signals WO to W7 supplied to the control input terminal g. As a result, the differential transistors T11 and T12 respond to the reference potential Voo with respect to the selection signals WO to W7 supplied to their control input terminals Bi.
ji-functions as a current switch circuit with logic threshold halt level.

When the corresponding selection signals WO to W7 are set to a low level lower than the reference potential VBB, the transistor T12 is in a cut-off state and the transistor T11 is in an on-state. Therefore, the differential transistors T6 and T7 are put into an operating state, and the non-inverted output signal 0, the inverted output signal 0, and the wired-OR output signal W of the delay gate circuit DGI are in the non-inverted state, similar to the unit delay circuit DCI in FIG. Depending on the inverted input signal 1 and the level of the inverted input signal, it is selectively set to the ``1'' level or the low level.

On the other hand, the corresponding selection signals WO to W7 are at the reference potential Vt1B.
When set to a higher high level, the transistor Tll
becomes a cut-off state, and instead the transistor T12
turns on. Therefore, the differential transistor T6
- T7 is made inactive, and node nd is forced to a predetermined low level via transistor T12.

At this time, the node nc is connected to the differential transistors T6 and T7.
By making it inactive, it becomes a noise level similar to the ground potential of a circuit. As a result, the delay gate circuit D
The non-inverted output signal 0 and the wired-OR output signal W of the GI are fixed at a low level, and the inverted output signal 0 is fixed at a no level, regardless of the corresponding selection signals WO to W7.

In other words, when the selection signals WO to W7 supplied to the control input terminals g of the delay gate circuits DCI to DG8 are set to low level, the delay gate circuits DCI to DG8 operate the non-inverting input terminals i and the inverting input terminals similarly to the unit delay circuits DCI to DC4. It functions as a unit delay circuit that delays a complementary input signal supplied under the input terminal by a predetermined delay time. In addition, the corresponding selection signal WO
~When W7 is set to low level, delay gate circuit D
The output signals of C,1 to DG8 are the non-inverted output signal 0, regardless of the levels of the non-inverted input signal i and the inverted input signal i.
The wired-OR output signal W is set to high level and the inverted output signal τ is set to low level, which is fixed to the logic "O" state.

In FIG. 1, wired-OR output terminals W of unit delay circuits DC1 to DC4 are commonly coupled to form a node n2. As a result, node n2 connects unit delay circuits DCI to D
When any wired-OR output signal W of C4 is set to high level, it is selectively set to high level -. Node n2 is further coupled to a second input terminal of OR gate circuit OG2. On the other hand, delay gate circuit DGI~DC
The wise-OR output terminals W of No. 4 are commonly coupled, and the node n
It is considered to be 3. Thereby, the node n3 is selectively set to a high level when the wired-OR output signal W of any one of the delay gate circuits DG1 to DC4 is set to a high level. The node n3 is further connected to an OR gate circuit OG2.
is coupled to a third input terminal of. Similarly, wired-OR output terminals W of delay gate circuits DG5 to DG8 are commonly coupled to form a node n4. Thereby, the node n4 is selectively set to a high level when the wired-OR output signal W of any one of the delay gate circuits DC5 to DG8 is set to a high level. Node n4 is further coupled to a fourth input terminal of OR gate circuit OG2.

From these facts, the non-inverted output signal n5 of the OR gate circuit OG2 is transmitted to the pulse widening circuit PWE and the unit delay circuit DC.
When the output signal of any one of I to DC4 and delay gate circuits DG1 to DG8 is set to high level, the output signal is selectively set to high level.

The inverted output signal n5 of the OR gate circuit OG2 is set to a high level complementary to the non-inverted output signal n5. As described above, the wired-OR output signals W of the delay gate circuits DGI to DG8 are selectively fixed to a low level by setting the corresponding selection signals WO to W7 to a high level.

As a result, the wired-OR output signals W of all the delay gate circuits connected after the delay gate circuit to which the wired-OR output signal W is fixed are similarly fixed to the low level. In other words, the OR gate circuit OG2 functions as an OR gate circuit for the output signals of the pulse widening circuit PWE, the unit delay circuits DC1 to DC4, and the delay gate circuits DCI to DG8, and also functions as an OR gate circuit for the output signals of the pulse widening circuit PWE, the unit delay circuits DC1 to DC4, and the delay gate circuits DCI to DG8.
Delay gate circuit DCI~ which is selectively enabled according to
Together with DG8, it constitutes the output selection circuit 5EL1.

Needless to say, the output signal n5 of the OR gate circuit OG2
The pulse width becomes the minimum when the selection signal wO is set to high level, and becomes the sum of the pulse width of the output signal n1 of the pulse widening circuit PWE and the total delay time of the unit delay circuits DC1 to DC4. Further, the pulse width of the output signal n5 of the OR gate circuit OG2 becomes maximum when all the selection signals wO to w7 are set to low level,
A unit delay circuit DC1~ is connected to the pulse width of the WE output signal n1.
The value is the sum of the total delay time of DC4 and the delay gate circuits DCI to DG8. As a result, the delay circuit DLI is
It functions as a delay circuit that determines the output signal n5 of the OR gate circuit OG2 and the pulse width of the heating pulse, that is, the timing signal φwe, which will be described later.

The non-inverting output signal n5 and the seven inverting output signals of the OR gate circuit OG2 are supplied to the non-inverting input terminal i and the inverting input terminal i of the unit delay circuit DC5 of the delay circuit DL2, respectively. Further, as described above, the inverted output signal n5 is supplied to one input terminal of the AND gate circuit AGI, and the non-inverted output signal n5 is supplied to one input terminal of the AND gate circuit AG2 of the output selection circuit 5EL2. Ru.

Although not particularly limited, the delay circuit DL2 includes three unit delay circuits configured in series by sequentially coupling the non-inverting output terminal 0 and the inverting output terminal 0, the non-inverting input terminal i, and the inverting input terminal i. It is composed of DC5 to DC7. Although not particularly limited, these unit delay circuits DC5 to DC7 have the same circuit configuration as the unit delay circuits DCI-DC4, and their non-inverted output signals 0 are set to nodes n6 to n8, respectively. The node n6 is further supplied to one input terminal of the analog game circuit AG3 of the output selection circuit 5EL2. Similarly, nodes n7 and n8 are further connected to the AND gate circuit AG of the output selection circuit 5EL2.
4 and one input terminal of AC3, respectively.

The delay circuit DL2 composed of unit delay circuits DC5 to DC7 sequentially and entirely delays the output signal n5 of the OR gate circuit OG2 having a predetermined pulse width without changing the pulse width.

The other input terminals of the AND gate circuits A02 to AG5 include, but are not limited to, the decoder DEC2.
Corresponding selection signals SO to S3 are supplied, respectively. The output signal of the AND gate circuit AG2 is the OR gate circuit O
It is supplied to the first input terminal of G3. Similarly, the output signals of the AND gate circuits AC3 to AG5 are supplied to the second to fourth input terminals of the OR gate circuit OG3, respectively.

Thereby, the output signal of the OR gate circuit OG3 is selectively set to a high level when the output signal of any one of the AND gate circuits A02 to AG5 is set to a high level. That is, the output selection circuit 5EL2 consisting of the AND gate circuits AG2 to AG5 and the OR gate circuit OG3 selects the corresponding output selection circuit SEL1 or the delay circuit DL2 by selectively setting the selection signals SO to S3 to a high level. It has the effect of selectively transmitting the output signals n5 to n8.

The output signal of OR gate circuit OG3 is supplied to one input terminal of AND gate circuit AG6.

The output signal of the flip-flop circuit FFI, that is, the internal control signal wm, is supplied to the other input terminal of the AND gate circuit AG6. As a result, the output signal of the AND gate circuit AG6, that is, the write pulse, in other words, the timing signal φwe, is the output signal of the output selection circuit SEL.
, 2 and the internal control signal wm are selectively set to high level. In other words,
Timing generation circuit T of memory with logic function of this embodiment
At O, the output signal of the OR gate circuit OG3, that is, the output selection circuit 5EL2, formed based on the clock signal r+CK is always formed regardless of the operation mode, and the memory with logic function is in the write mode in that cycle and the internal control signal is output. When wm is set to high level, it is selectively set as a timing signal φwe and is supplied to the write amplifier WA of the bipolar RAM.

FIG. 5 shows a timing diagram of one embodiment of the evening/timing generation circuit TG of FIG. In the figure, the pulse width selection signals WSO to WS2 are combined with the selection signal W6 at a high level, and the set amplifier time selection signal S
A case where S0, 331 is a combination in which the selection signal sl is set to high level is shown as an example. An overview of the operation of the write pulse generation circuit of the timing generation circuit TG of this embodiment will be explained with reference to FIG.

In FIG. 5, the clock signal GK is a periodic pulse having a relatively small duty, although it is not particularly limited. Although the operation of the memory with logic functions is not particularly limited, it is executed with one period of this clock signal GK as one memory cycle, and the operation mode of each memory cycle is as follows.
Determined according to write enable signal WE. Therefore, before the clock signal GK is set to a high level, the output enable signal WE is set from a low level to a high level, and at the same time, the predetermined input data DIO to Din are set to a high level.
is supplied. In addition, pulse width selection signals WSO to WS2
are supplied in a combination in which the selection signal W6 is set to a high level, and set amplifier time selection signals SSO and SSI are supplied in a combination in which the selection signal sl is set to a high level.

In the timing generation circuit TG, the pulse width selection signal WSO
~ Depending on the combination of WS2, the output signal of the decoder DEC1, that is, the selection signal W6 is alternatively set to high level, and the output signal of the decoder DEC2, that is, the selection signal sl is alternatively set to high level. Furthermore, at the rising edge of the clock signal CK, since the write enable signal WE is at a high level, the flip-flop circuit FFI is set, and the write mode signal, that is, the internal control signal wm is set at a high level.

On the other hand, the clock signal CK is supplied to the pulse widening circuit PWE via the OR gate circuit OG1, and as a result, an output signal nl of the pulse widening circuit PWE having a pulse width approximately three times that of the clock signal GK is formed. This output signal n1
is supplied to the OR gate circuit OG2, and its output signal n
5 to a high level, and the unit delay circuit D
The signal is supplied to a delay circuit DLI including CI to DC4 and delay gate circuits DCI to DG8.

In this embodiment, as described above, the selection signal W6 is alternatively set to high level. Therefore, the output signal n1 of the pulse widening circuit PWH is transmitted with the same pulse width to the output terminal of the delay gate circuit DG6, and from the delay gate circuit DG7 to the subsequent delay gate circuit DG? and DG8
The output signal of is fixed at low level. Therefore, nodes n2 and n3 are connected to the output signal n of the pulse widening circuit PWH.
Unit delay circuit DCI corresponding to each pulse width of l
- It is kept at a high level for a period that is the sum of the total delay time of DC4 and delay gate circuits DGI-DG4. Further, the node n4 is set to a high level only for a period that is the sum of the pulse width of the output signal n1 of the pulse widening circuit PWH and the total delay time of the effective delay gate circuits DG5 and DG6.

As described above, the output signal n5 of the OR gate circuit OG2 is set to a high level when the output signal nl of the pulse widening circuit PWH is set to a high level, and is returned to a low level when the node n4 is set to a low level. This results in
The pulse width of the output signal n5 of the OR gate circuit OG2 is the sum of the pulse width of the output signal n1 of the pulse widening circuit PWH and the total delay time of the unit delay circuits DCI to DC4 and the delay gate circuits DCI to DG6 that constitute the delay circuit DL1. value.

The output signal n5 of the OR gate circuit VsOG2 is further delayed with the same pulse width by the unit delay circuits DC5 to DC7 forming the delay circuit DL2, and the output signal n6 of the OR gate circuit VsOG2 is delayed with the same pulse width.
~n8 is formed. These output signals n5 and n6~
As described above, n8 is supplied to the corresponding AND gate circuits AC2 to AG5 of the output selection circuit 5EL2, respectively.

In this embodiment, as described above, the selection signal s1 is alternatively set to high level. Therefore, the AND gate circuit A
G3 is alternatively put into the transmission state, and only the output signal n6 of the unit delay circuit DC5 of the delay circuit DL2 is sent to the output selection circuit 5.
It is transmitted as an output signal of EL2. Output selection circuit 5E
Since the memory with logic function is in write mode in this memory cycle and the internal control signal wm is set to high level, the output signal of L2 is made into a harm pulse, that is, a timing signal φwe, and is supplied to the write amplifier WA. . In this embodiment, the write pulse, that is, the timing signal φwe, has a pulse width of the output signal n1 of the pulse widening circuit PWH, and unit delay circuits DCI to DC4 and delay gate circuits DGI to DG constituting the delay circuit DLI.
It has a predetermined pulse width obtained by adding 60 total delay times, and has a predetermined setup time determined by the total delay time of the pulse widening circuit PWE and the unit delay circuit DC5 of the delay circuit DL2.

As described above, the memory with logic function of this embodiment has a built-in timing generation circuit TG including a write pulse generation circuit, and a clock signal CK and a write enable signal WE.
It has a function of internally autonomously forming a write pulse with a predetermined pulse width and a predetermined amplifier time based on .

The write pulse generation circuit of the timing generation circuit TG includes a delay circuit D that determines the pulse width of the write pulse.
L1 and a delay circuit DL2 that determines the cent-up time. These delay circuits are composed of a plurality of unit delay circuits and delay gate circuits that are selectively enabled according to the pulse width selection signal wso-wS2 or the set amplifier time selection signals sso, ss1 supplied via an external terminal. , whose substantial delay time is the pulse IIg selection signal WSO to WS2 and the set amplifier time selection signal S.
S.O.

Controlled by SSI. Therefore, the memory with logic function of this embodiment can be used even in a semi-finished product or a completed product.
Write pulse timing conditions can be optimized without requiring mask changes. This results in
The memory with logic functions of this embodiment can shorten its development period and increase product yield.

As shown in the above-described embodiment, when the present invention is applied to a semiconductor integrated circuit device such as a memory with a logic function whose basic configuration is a bipolar RAM, the following effects can be obtained. In other words, the delay circuit (included in the write pulse generation circuit, etc. of the 1186 memory with functional functions) is composed of a plurality of unit delay circuits connected in series, and the output signals of these unit delay circuits are selectively output according to the selection signal. By providing an output selection circuit for transmitting the signal and a decoder for selectively forming the selection signal by decoding a predetermined selection control signal, it is possible to control the delay time of the delay circuit.

(2) According to the above (paragraph 11), by supplying the above selection control signal from the pad or external terminal after the semi-finished product or finished product, the signature of the memory with logic function can be created without the need to change the mask etc. This has the advantage of being able to adjust the pulse width of the input pulse, set-up time, etc.

(3) According to the above (11) and (2), it is possible to shorten the development period of a memory with logical functions, etc., and to reduce the cost thereof.

(4) Items (1) and (2) above provide the effect that the product yield can be increased in the production process of memory with logic functions and the like.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without getting the gist of the invention. For example, the pulse width selection signals WSO to WS2 and the setup time selection signal 33
0. The SSI may be supplied via an internal pad at the probe test stage, and the number of focuses may be arbitrary. Furthermore, these pulse width selection signals and setup time selection signals may be directly supplied as selection signals without being decoded by a decoder. In FIG. 1, in the delay circuit DLL, the delay gate circuits DGI-DG8 can be replaced with unit delay circuits. In this case, a selection circuit and an OR gate circuit are separately required to transmit the output signal of the corresponding unit delay circuit according to the selection signal wQ-w7. In the embodiment shown in FIG. 1, a signal having a predetermined pulse width and setup time is formed based on the clock signal CK, regardless of the write enable signal WE, and then the signal is ANDed with the internal control signal wm. By taking the timing (R signal φwe), after taking the AND of the clock signal GK and the enable signal qWE at the stage before the delay circuit DLL, the pulse width and set amplifier time are adjusted. The !F write pulse generation circuit automatically changes the pulse width of the write pulse and the cent amplifier time when the pulse width selection signals WSO to WS2 and the up time selection signals SSO and SSI are not supplied. In FIG. 4, the memory array MARY may be composed of a plurality of memory mats, and the bipolar RAM may have a column selection circuit. Furthermore, the specific circuit configurations of the timing generation circuit TG shown in FIG. 1, the unit delay circuits and delay gate circuits shown in FIGS. 2 and 3, and the logic shown in FIG. Various embodiments can be adopted, such as the block configuration of the functional memory and combinations of control signals and timing signals.

In the above description, the invention made by the present inventor was mainly applied to a write pulse generation circuit for a memory with logic functions, which is the field of application in which the invention was made, but the present invention is not limited to this, and for example, The present invention is also applicable to other pulse generation circuits of memory with logic function and various digital devices including memory with logic function. Widely available for circuit equipment.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, the delay circuit included in the write pulse generation circuit of the memory with logic function is configured with a plurality of unit delay circuits connected in series, and the output signal is configured to selectively transmit the output signals of these unit delay circuits in accordance with a selection signal. By providing a selection circuit and a decoder that decodes a predetermined selection control signal to alternatively form the selection signal, the selection control signal can be supplied from the band or an external terminal after the semi-finished product or product is completed. Accordingly, the pulse width of the write pulse of the memory with logic functions, the setup time, etc. can be adjusted without changing the mask or the like.

This shortens the development period for memory with logical functions, etc.
The product yield can be increased.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a timing generation circuit of a memory with logic functions to which the present invention is applied, and FIG. 2 is an embodiment of a unit delay circuit included in the timing generation circuit of FIG. 1. 3 is a circuit diagram showing an example of the delay gate circuit included in the timing generation circuit of FIG. 1, and FIG. 4 is a circuit diagram of a memory with logic function including the timing generation circuit of FIG. 1. FIG. 5 is a timing diagram showing an embodiment of the timing generation circuit of FIG. 1. FIG. TO...timing generation circuit, PWE...pulse widening circuit, DLl, DL2...delay circuit, DCI-DC
? ... Unit delay circuit, DGI to DG8 ... Delay gate circuit, 5ELI, 5EL2 ... Output selection circuit, DE
Cl, DEC2...decoder, FFI...flip-flop circuit, ACI~AG6...AND gate circuit, OGI~OG3...OR gate circuit. To T1 T12...Transistor, R1-R4...Load resistance, 01-C4...Capacitor, 131-! S8
...constant current source. MARY...Memory array, AD...Address decoder, ADB...Address buffer, WA...Write amplifier, RA...Read amplifier, DrB...Data input cover sofa, l') 013... Data output buffer. Representative Patent Attorney I.L. Mitsumasa Waka Figure 2 Figure 3 G1 y, I+ Figure

Claims (1)

Claims: 1. A semiconductor integrated circuit device comprising a delay circuit whose delay time is changed according to a selection control signal supplied from a predetermined pad or an external terminal. 2. The delay circuit is included in a pulse generation circuit that forms an output signal having a predetermined time relationship and a predetermined time width based on a predetermined input signal, and is connected in series. The pulse generation circuit further includes a decoder that decodes the selection control signal to alternatively form a corresponding selection signal, and a decoder that selectively forms a corresponding selection signal by decoding the selection control signal. 2. The semiconductor integrated circuit device according to claim 1, further comprising an output selection circuit that selectively transmits the output signal of the corresponding unit delay circuit according to the following. 3. The semiconductor integrated circuit device is a memory with a logic function whose basic configuration is a bipolar RAM, the pulse generation circuit is included in a timing generation circuit of the memory with a logic function, and the output signal is 3. The semiconductor integrated circuit device according to claim 1, wherein the write pulse is a write pulse supplied to a write amplifier of the bipolar RAM.