JPH01235363A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the mounting density per package by a method wherein one or more semiconductor chips are piled up on a semiconductor chip and these are pellet-bonded by using a nonconducting adhesive. CONSTITUTION:A lower-part semiconductor chip 1B is pellet-bonded to a tab 2 by using an adhesive 3 for pellet bonding use. An upper-part semiconductor chip 1A is pellet-bonded to the lower-part semiconductor chip 1B by using a nonconducting adhesive 4 for pellet bonding use. The upper-part and lower- part semiconductor chips 1A and 1B are connected individually to lead frames 6 by using bonding wires 5A, 5B, and sealed by using a resin 7 for mold sealing use such as a resin or the like. Individual pads on the upper-part and lower-part semiconductor chips 1A and 1B and the bonding wires 5A, 5B are connected by a wedge ball bonding method. The lead frames 6 and the bonding wires 5A, 5B are connected by a thermal pressure bonding method used together with an ultrasonic oscillation. By this setup, the mounting density per package can be increased by a portion where a semiconductor chip is piled up at the upper-part.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor devices, particularly highly integrated semiconductor devices.

This invention relates to semiconductor devices that require high functionality or that require countermeasures against soft errors caused by alpha rays.

[Prior art]

Normally, in order to promote higher integration in semiconductor devices,
High-density packaging has been progressing. Achieving this high-density packaging requires miniaturization of the package. These include small surface-mount packages such as small outline package (SOP), quad flat package (QFP), plastic leap-fit chip carrier (PLCC), and small outline J-bend (SOJ). .

In addition, impurities in the mold resin have been reduced as a countermeasure against soft errors caused by alpha rays.

[Problem to be solved by the invention]

However, according to the inventor's study, although the above-mentioned conventional technology requires a minimum number of sealed packages for the size of the semiconductor chip, consideration is not given to the increase in the size of the semiconductor chip. Since this has not been done, there has been a problem in that there is a limit to the miniaturization of semiconductor devices, and there is a limit to high-density packaging.

An object of the present invention is to provide a semiconductor device that enables high-density packaging.

Another object of the present invention is to provide a technique that does not require high purity of mold sealing resin.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

A semiconductor device in which an electrode on a semiconductor chip and an external terminal are electrically connected with a metal wire, wherein at least one semiconductor chip is stacked on the semiconductor chip and each is attached to a pellet with a non-conductive adhesive. It is.

(Function) According to the above-mentioned means, by stacking at least one semiconductor chip on top of the semiconductor chip and attaching each semiconductor chip to a pellet with a non-conductive adhesive, the number of semiconductor chips stacked on the upper side is reduced per package. The packaging density can be increased.

Further, by combining the upper and lower semiconductor chips, higher functionality can be achieved.

Further, in the case where a memory chip is used as the lower semiconductor chip, the memory cell portion is shielded by the upper semiconductor chip, so that soft errors caused by α rays can be reduced.

In addition, since the shrinkage stress of the mold resin is borne by the side surface of the upper semiconductor chip, the stress on the bonding pad (electrode) part of the lower semiconductor chip is reduced, causing cracks under the pads of the lower semiconductor chip. can be reduced.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail based on the drawings.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

FIG. 1 is a plan view with part of the sealing material removed for explaining the schematic configuration of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line ■-■ in FIG. 3 are cross-sectional views taken along line mm in FIG. 1.

In the semiconductor device of this embodiment, as shown in FIGS. 1 to 3, the lower semiconductor chip IB is attached onto the tab 2 using a pellet attaching adhesive 3 such as Ag paste (for example, at a temperature of about 350°C). pelletized). The upper semiconductor chip IA is pelletized onto the lower semiconductor chip IB using a non-conductive pelletizing adhesive 4. As the non-conductive adhesive 4 for attaching pellets, silicone (Si)-added resin is used, for example, at about 200°C.
Pelletized at a temperature of

The upper and lower semiconductor chips IA and IB are connected to a lead frame 6 by bonding wires 5A and SB, respectively, and are sealed with a mold sealing resin 7 such as resin (mold temperature is approximately 175° C.). .

After molding, plate the lead frame 6,
Process into a predetermined shape.

The respective pads on the upper and lower semiconductor chips IA and IB are connected to the bonding wires 5A and 5B by the wedge-pole bonding method. Also, a lead frame 6 and a bonding wire 5A.

5B is connected by thermocompression bonding using ultrasonic vibration.

It is preferable to use coated wires as the bonding wires 5A, 5B. By doing so, it is possible to prevent shimmy between the bonding wires 5A, 5B.

The coated wire is, for example, a wire of Au, C:u, An, etc. with a diameter of about 20 to 35 μm, and a wire of 1 to 2 μm of polyurethane, polyester, polyesterimide, polyimide, etc.
A material coated with a thickness of approximately 300 m is used.

Next, an example of the layout of each element on the upper and lower semiconductor chips IA and IB is shown in FIGS. 4 and 5.

FIG. 4 shows an embodiment in which the present invention is applied to a 1 mega (M) dynamic random access memory (DRAM), in which the peripheral circuit of the memory array part is shared.

FIG. 5 shows the upper and lower semiconductor chips IA shown in FIG.
This is an example in which only the bonding wire area is changed in the layout of each element on the IB.

4 and 5, 101 is a memory cell array section, 102 is a column decoder circuit, 103 is a column driver & input/output (Ilo) bus, 104 is a word driver circuit, 105 is a word clear circuit, and 106 is a row decoder circuit. , 107 is an address buffer circuit, 108 is an RA
109 is a data input (Din) buffer circuit, 111 is a data output (Do)
ut) buffer circuit, 112 is a CAS generation circuit, 113
is a bonding wire, 114 is an F7V1 generation circuit, 1
15 is a male ASI generation circuit. [Port 1 and CASI are the memory cell array portions 101 of the upper and lower semiconductor devices.
selection control signal.

A0~A, , Vcc, Vss, πT1. WE and 60
are bonding pads (electrodes) for electrical connection to external devices. Symbols RAS1 and CASI are pads for connecting selection control signal lines of the upper and lower semiconductor chips IA and IB.

Memory cell array section 10 of the upper semiconductor chip IA
As shown in FIG. 4, the peripheral circuits of No. 1 are connected by bonding wires 113 to the address buffer circuit 107 of the lower semiconductor chip IB, the τ lower generation circuit 108, the W1 generation circuit 109, and the data input (Din) buffer circuit. 110 and a data output (Dout) buffer circuit 111, so that the upper semiconductor chip IA and the lower semiconductor chip IB share the upper semiconductor chip IA and the lower semiconductor chip IB. The selection of the memory cell array section 101 is based on the RAS1 generation circuit 114 and σA
This is performed by the S1 generation circuit 115.

Therefore, the degree of integration can be doubled by simply increasing the number of lead pins for electrical connection with external devices by one or two pins.

Furthermore, if a semiconductor chip such as a microcomputer is used as the upper semiconductor chip IA, a highly integrated (large capacity) microcomputer can be realized. Further, by reducing the size of the upper semiconductor chip IA, it is also possible to increase the chip acquisition rate from a semiconductor wafer.

Further, as shown in FIG. 5, the bonding pad forming area of the lower semiconductor chip IB is expanded, and a bonding pad forming area is also provided in the upper semiconductor chip IA. The lower semiconductor chip IB has pads A0 to A, .
Vcc, Vss, RAS.

WE and CAS are provided, and the upper semiconductor chip IA also has pads A6 to A@g Vc similar to the lower semiconductor chip IB.
c, V88g RA S t WE t CA S are provided, and corresponding pads are connected with bonding wires 113. The pads RASI and ml for connecting the selection control signal lines of the upper and lower semiconductor chips IA and IB are provided on the upper semiconductor chip IA.

The selection of the memory cell array portions 101 of the upper and lower semiconductor chips IA and IB is performed by pad balls ASI and C.
This is performed using selection control signals for the upper and lower semiconductor chips IA and IB connected to the ASI, or either external control signal.

With this configuration, as in the example shown in FIG. 4, the degree of integration can be doubled by simply increasing the number of pins for electrical connection with external devices by one or two pins.

Next, the stress applied to the semiconductor chip of the resin-sealed semiconductor device will be explained using FIG. 6.

In the resin-sealed semiconductor device, as shown by P in FIG. 6, the semiconductor chip (
b) On the shear plane stress (S hearS stress
) occurs. This stress P depends on the size W of the semiconductor chip (b), and if the semiconductor chip (b) becomes large, the bonding wire may break or cracks may occur under the pads of the semiconductor chip (b). When a small semiconductor chip is attached to a pellet on a semiconductor chip (b), the shear stress on the semiconductor chip (b) is reduced because stress is applied to the side surface of the small chip.

As can be seen from the above description, according to this embodiment, the non-conductive adhesive 4 for attaching pellets is placed on the lower semiconductor chip IB.
By stacking and pelletizing the upper semiconductor chips IA via the upper semiconductor chips IA, it is possible to increase the packaging density per package by the amount of the upper semiconductor chips IA.

Further, by combining the upper and lower semiconductor chips IA and IB, higher functionality can be achieved.

Furthermore, since the memory section of the lower semiconductor chip IB is shielded by the upper semiconductor chip IA, soft errors due to alpha rays can be prevented.

In addition, since the shrinkage stress of the mold sealing resin is borne by the side surface of the upper semiconductor chip IA, the lower semiconductor chip IA
It is possible to reduce stress in the bonding pad (electrode) portion of B and prevent cracks under the pads of the lower semiconductor chip IB.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, in the embodiment described above, an example was explained in which one small semiconductor chip is stacked, but the present invention can reduce the integration density per package by sequentially stacking a plurality of small semiconductor chips by reducing the size of the chips. The packaging density (packaging density) can be further increased.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

By stacking at least one semiconductor chip on top of a semiconductor chip and attaching each semiconductor chip to a pellet using a non-conductive adhesive, one semiconductor chip is stacked on top of the other.
The packaging density per package can be increased.

In addition, since the shrinkage stress of the mold resin is borne by the side surface of the upper semiconductor chip, the stress at the bonding pad (electrode) part of the lower semiconductor chip is reduced, which causes cracks under the pads of the lower semiconductor chip. can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a plan view with part of the sealing material removed for explaining the schematic configuration of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line ■-■ in FIG. 3 and 3 are cross-sectional views taken along the line ■-■ in FIG. FIG. 6, a plan view showing the embodiment, is a diagram for explaining stress applied to a semiconductor chip of a resin-sealed semiconductor device. In the figure, IA... upper semiconductor chip, IB... lower semiconductor chip, 2... tab, 3... adhesive for attaching pellets, 4... non-conductive adhesive for attaching pellets. , 5A. 5B...Bonding wire, 6...Lead frame, 7...Mold sealing resin.

Claims (1)

[Claims] 1. In a semiconductor device in which an electrode on a semiconductor chip and an external terminal are electrically connected by a metal wire, at least one semiconductor chip is stacked on the semiconductor chip, and each semiconductor chip is made of a non-conductive material. A semiconductor device characterized by being attached to pellets with adhesive. 2. The semiconductor device according to claim 1, wherein each of the plurality of semiconductor chips has an upper semiconductor chip smaller in size than a lower semiconductor chip. 3. The semiconductor device according to claim 1 or 2, wherein the plurality of semiconductor chips also serve as input/output circuits. 4. The semiconductor device according to any one of claims 1 to 3, wherein a coated wire is used as the metal wire.