JPH01225226A - Error correcting and decoding device - Google Patents

Abstract

PURPOSE:To decode a receiving signal at a high speed with using a low speed decoder without any limit in a transmission side by writing the reception signal from a transmission line to a memory and decoding the written signal. CONSTITUTION:Data from a transmission side 10 are received by a reception demodulator 3 in a reception side 20. These received data are stored through a switch 41 to memories 51 and 52 with being divided. The data to be stored in memories 51-53 are controlled by a control circuit 91, respectively read and decoded by decoders 61-63. The decoded data are outputted through output buffer memories 71-73 and a switch 81.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to an error correction decoding device for communication.

(Prior Art) Convolutional code decoding circuits generally operate at low speeds, and it may not be possible to obtain a decoder with a speed that is compatible with the speed of a transmission path (referred to as a bit rate).

In such a case, conventionally, as shown in FIG. 5, the codes on the transmission path are divided into several systems for each code, and encoding and decoding are performed for each system.

As shown in the figure, the input data is divided into three encoders 1), 12 and 13 by switching the switch 14 according to the clock of the control circuit 16 and inputting the input data. let The encoder 1)゜12.13 encodes the input data respectively, and switches the switch 15 to the control circuit 1.
6), the modulating transmitter 2 modulates the signal, and transmits it as a radio wave. This transmitted data is received and demodulated by the reception demodulator 3. At this time, the switch 43 is switched according to the clock of the control circuit 93, and the decoder 64,
The data transmitted after being divided by 65 and 66 is decoded as it is. The decoded data is outputted by switching the switches 83 according to the clock of the control circuit 93.

However, according to this method, each encoder 1),
12.13, it is necessary to perform special encoding, so that - film properties are lost. For example, it is impossible to receive a standard signal using a single encoder and apply a low-speed decoder.

Also, when it is necessary to receive only a signal for a certain limited period, such as in a TDM transmission line, the information rate of the signal can be decoded by one decoder if it is averaged. Regardless of the method, there is an inconvenience that multiple decoders are required.

(Problems to be Solved by the Invention) As described above, the decoding speed on the receiving side must match the transmission speed on the transmitting side. Another drawback is that it is necessary to prepare a number of decoders corresponding to the number of encoders, which complicates coordination between the transmitting side and the receiving side.

An object of the present invention is to provide an error correction device that decodes a received signal from a high-speed transmission path using a low-speed decoder and corrects errors without any restrictions on the transmitting side.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, an error correction decoding device includes a memory for writing a received signal from a transmission path, and a decoding device for reading and decoding the contents of this memory. and a control circuit for generating a write timing signal for this memory. This write timing signal is characterized in that it is continuous over a certain period of time.

(Function) For example, a high-speed signal from a transmission path is written into the memory using a write timing signal that is continuously generated over a certain period of time by a control circuit, and the signal written into the memory is , decoding is performed slowly using a slow decoder.

Therefore, regardless of whether the signal on the transmission path is low speed or high speed, the signal on the transmission path is written into the memory using the write timing signal generated from the control circuit. and,
By decoding this signal with a decoder, it is possible to demodulate a good signal sent at any speed without error.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the invention. As an example of the receiving side 20, memories 51, 52, 53 and decoders 61, 62
．． 63, and three combinations of output backup memories 71, 72, and 73 are used.

The decoding speed of the decoders 61, 62, and 63 is 1 of the transmission path speed.
/2. In this example, a method is used in which encoders on the transmission path are continuously decoded.

As shown in FIG. 1, when data is input to the transmitting side 10, the data is encoded by an encoder 1, modulated by a modulation transmitter 2, and transmitted. This transmitted data travels on a transmission path and is received by the receiving demodulator 3 in the receiving side 20. This received data is transferred to the memory 51 by switching the switch 41 with the control circuit 91 to divide the data.
, 52° and 53, respectively. Memory 51, 52.5
The data stored in 3 is read out under the control of a control circuit 91, and decoded by decoders 61, 62 and 63. The decoded data is sent to the output puffer memory 7.
1, 72, and 73 by the control circuit 91. The data written in the output buffer memories 71, 72, and 73 are outputted by switching the switch 81 to the control circuit 91. FIG. 2 shows an operation timing chart of FIG. 1. The signal on the transmission path from the reception demodulator 3 is transmitted to the chi
, ch2. Separated into 3 channels: +ch3.

At the beginning of each channel, the state of the encoder (1) is known in advance. The control circuit 91 switches the switch 41 according to the frame signal, and transfers the signal on the transmission path to the memory 51, memory 52, and memory 53 for each channel.
Divide into. The memory 51 performs writing during the chl period and performs reading during the Ca2 and Ca3 periods. The decoder 61 reads the code of chl from the memory 51 and decodes it during periods Ca2 and Ca3.

The decoding speed is 1/2 of the transmission speed. The output of the decoder 61 is slowly stored in the output buffer memory 71 over a period of Ca2.3, and is rapidly output during the next chl period. The switch 81 selects and connects the output period of the output buffer memory 71, output buffer memory 72, and output buffer memory 73 to obtain a signal output after nine consecutive error corrections. By developing the configuration shown in FIG. 1, it is possible to continuously decode codes at a speed N times the speed of a single decoder using N+1 systems of decoders. In the configuration shown in FIG. 1, memory 51, memory 52, memory 53 and output puffer memory 7
1.72.If 73 is a FIPo type memory that can be read and written at the same time, the IDLE period of each decoder is unnecessary#)
Continuous decoding can be performed at N times the speed using N decoders.

Next, a second embodiment is shown in FIG. This operation timing chart is shown in FIG. In this example, U W Fi
There is a reed at the beginning of chl, but the state of the code at the beginning of other channels is not constant. If it is necessary to decode only the Ca2 portion of this signal, the memory 5 writes the Ca2 signal including the preceding and succeeding codes (shaded portion in FIG. 4). The decoder 6 decodes the data including the hatched part, but the state of the code is not determined in the first hatched part, and maximum likelihood decoding cannot be performed. Near the beginning of Ca2, the code state converges and constant tb maximum likelihood decoding can be performed, so the output at that time is written to the output buffer memory 7 of the Fs Fog type. The output buffer memory 7 continuously outputs error-corrected signals while performing speed conversion. In this way, specific channel information can be extracted from a high-speed TDM transmission path by error correction decoding using a low-speed decoder.

In the configuration shown in FIG. 3, a plurality of combinations of memory 5, decoder 6, and output buffer memory 7 are used, and the control circuit 92 independently generates a frame signal, thereby creating a high-speed transmission path that is not framed. All of the signals can be decoded sequentially. At this time, the operations of the independent memory 5, decoder 6, and output buffer memory 7 are the same as those shown in FIG.

〔Effect of the invention〕

As described in detail above, according to the present invention, even codes from a high-speed transmission path can be error-corrected and decoded using a low-speed decoder without imposing any restrictions on the transmitter-side encoder. can. Therefore, it is possible to realize an error correction device that can decode data regardless of the transmission speed on the transmitting side.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
3 is a diagram showing another embodiment of the present invention, FIG. 4 is a diagram showing the timing chart of FIG. 2, and FIG. 5 is a diagram showing a conventional example. It is. 1.1), 12.13... encoder, 14.15...
Switch, 16... Control circuit, 2... Modulator/transmitter, 3... Receiver/demodulator, 41.42, 43.81°8
3...Switch, 5,51,52.53...Memory, 6.61,62,63,64,65.66...Decoder, 7,71,72.73...Output backup memory ,
91.92.93...Control circuit. Agent: Patent Attorney Noriyuki Chika Mitsuyuki Matsuyama, Figure 1, Figure 3, Memory Figure 4

Claims (3)

[Claims] (1) A memory for writing received signals from the transmission line,
a decoder for reading and decoding the memory contents;
An error correction decoding device comprising: a control circuit for generating a write timing signal for the memory, wherein the write timing signal is continuous over a certain period of time. (2) The error correction decoding apparatus according to claim 1, wherein the decoder performs decoding using a convolutional code. (3) The error according to claim 1, wherein the continuous period of the write timing signal is longer than the period of the code to be decoded by the decoder, which is more than twice the constraint length of the convolutional code. Correction decoding device.