JPH01211136A - Program debugging system - Google Patents

Abstract

PURPOSE:To dynamically rewrite the address of a shifting destination by making plural interruption processings generated with a debugging register exist and shifting it to a special interruption processing based on message contents from a host machine. CONSTITUTION:When the message of a real time record is issued from a host machine 2, this is sent to a target 1, the target 1 receives and decodes this, and an interruption vector value corresponding to an interruption signal generated from a debugging register 3 is sent to a ROM 13 in the target 1. The ROM 13 refers to the message written beforehand, prepares a processing address and sets an address to the debugging register 3. Thereafter, when a message concerning a prescribed position is sent from a machine 2, this is stored into a RAM 14 and the execution starting address is set to the instruction pointer of a CPU 11. Next, the debugged program obtained here is given to the register 3, the interruption processing is completed and the register of the CPU 11 is read.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a program debugging method for debugging a target operating program in an information processing device.

[Conventional technology]

FIG. 1 is a block diagram showing a conventional program monitor. In the figure, 1 is the target which is the system to be debugged, and 11 is the central processing unit of the target 1 (
12 is a communication means (hereinafter referred to as CD) that controls communication processing, receives messages related to debugging, and transmits the results; 13 is a communication means (hereinafter referred to as CD) that handles communication processing, receives messages related to debugging, and transmits results; 13 is a communication means for controlling the program to be debugged, and accesses registers of target 1, etc. 14 is a read-only memory (hereinafter referred to as OM) containing a monitor program that specifies debugging;
Random access memory (hereinafter referred to as AM) used when the program in OM13 is executed, 2
3 is a host machine that sends and receives messages to and from the CD 12, and 3 is a debug register (hereinafter referred to as D
It is called 几. This D-box 3 may exist as an external circuit of the CPU 11, but is usually built into the CPU. Here, an external circuit is used for explanation.

Next, the operation will be explained. A debug command issued by the user from the host machine 2 is sent to the CD 12 as predetermined message data. CD1
The message received at 2 is decoded by the monitor program in H1ROM 13, and the requested operation is performed.

For example, if there is a request to read the register of CPU11,
Read the corresponding register. The read value is sent to the host machine 2 via the CD 12. Host machine 2 displays this value. In addition, when controlling the execution of the program to be debugged, the CPU 1
The instruction pointer of l is written, and execution begins.

To interrupt the above execution, the address to be interrupted is set to DR.

3, and when the program to be debugged reaches the interrupt address, an interrupt signal issued from DR3 moves to interrupt processing, interrupts execution here, and returns control to the monitor program. This will be explained below according to the flowchart shown in FIG. For example, the execution control command for the debugged program from the host machine 2 is "G0F OM ADD TIL ADD".
RZ", and when this is sent to the host machine 2 (step 5T1), the target 1 receives and decodes it (step ST2), sets ADD 几1 as the execution start address written in the instruction pointer, ADDRZ is set as the execution interruption address written to DR3 (step 5T3).

After these writes are completed, the program to be debugged is executed from ADE) to ADDRZ-1 (Step 5T4). When the execution reaches ADDRZ, an interrupt signal is generated and the monitor program is executed by interrupt processing. The control is returned (step 5T5).

Here, the transition to interrupt processing is performed by referring to a table known by the CPU 11 called an interrupt vector, in which interrupt processing destinations are written. Therefore,
When an interrupt occurs, the processing destination of the corresponding interrupt is obtained from the table, the process moves to the processing destination, and the contents included in the processing destination are executed.

Next, target 1 waits to receive the next message (command) (step 8T5), and when host machine 2 sends the next message (step 5T7), target 1 receives and decodes it (step 8TJ3).
, Since the program debugging method in step ST3 and subsequent steps and in the conventional program monitor is configured as above, the usage of DR3 is fixed and Df(,3
After reaching the address set in DR3, it will always return to the monitor program, and the debugged program will not only stop running at the address set in DR3, but also write an arbitrary address to DR3. Since an interrupt is generated at the written address,
A real-time function that allows you to read a section of the program (for example, register or memory values) immediately after executing a specific address in the debugged program, or to move to a program added for debugging (such as a patch program). There were problems such as not being able to debug.

This invention was made to solve the above-mentioned problems, and it generates an interrupt at any point in time when the program to be debugged is executed, and handles the interrupt in advance by commands from the host machine. The object of the present invention is to obtain a program debugging method capable of real-time debugging in which a set debugging operation is performed and the program to be debugged is returned to after the interrupt processing is completed.

[Failure to solve the problem]

In the program debugging method according to the present invention, there are multiple interrupt processes caused by DR, and the transfer destination address of the interrupt process is set so that the process can be transferred to a specific interrupt process depending on the content of the message from the host machine. It is designed to be rewritten dynamically.

[Operation] In the program debugging method according to the present invention, after a message (command) from the host machine to set an address in the DR is issued, one of the commands for debugging in real time is issued, and the program debugging method according to the present invention When the execution command of the debugged program is issued, an interrupt vector is written so that the interrupt processing is executed according to the address of the DR where the above message is set, and at the end of this processing, the address of the above execution command is The interrupt vector is rewritten so that the processing is executed according to the interrupt vector.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is the target, 2r/i host machine,
3 is DR, and these hardware blocks are exactly the same as the conventional ones.

Next, the operation will be explained. Now, read the value of the register of the CPU 11 when the address ADD 3 set in DR3 is executed, and save it in the AM 14.
After that, return to the debugged program again and add the address AD.
At step D2, the program returns to the monitor program 9, and then considers real-time debugging in which the saved register values are sent to the host machine 2 and displayed.

The command on host machine 2 to set an address in DR3 is "SET ADDR3". As a result, address ADDR3 is set in DR3 on target 1. Also, a message for debugging in real time. For example, "REALTI"
ME 几EG几D” -1 “Read the register in real time.”, “REALTIMEAf)D” --“
Migrate to additional programs in real time. ” etc. Here, the message “REALTIME RH
GRD” will be explained.

FIG. 2 is a diagram 70 showing the series of operations, and below,
The operation will be explained with reference to this. First, on host machine 2, send the message “REALTIMEBEG 几D”
When # is issued, the next message is sent to target 1 (step 5T11). Next, in step 5T12), the target 1 receives and deciphers this, and sends the value of the interrupt vector corresponding to the interrupt generated from the DR3 to the message "REALT
IMER, EGRD” processing address (vg
c'roat) (Step 5T13
). Next, host machine 2 sends the message “SET A
DDR3''' is issued and the message is sent to target 1 (step 8T14).This is received and decoded in ROM 13 (step 5T15), and address ADDR3 is set in DR3 (step 8T16).

After this, from host machine 2, “GOPR, OMADD
When this message is sent (step 8T17), it is received and deciphered (step 5T18), and the address ADDR2 is sent to address ADDR2.
After storing it in a specific location on Mi4 (Step 5T19)
, set the execution start address ADDRI to the instruction pointer of the CPU 11 (step 5T20),
Execute the debugged program (step 5T21)
. When the debugged program reaches address ADDR3, an interrupt occurs and the CPU
The register of i1 is read and the result is saved in a specific section (herein referred to as a queue) of the RAM 14 (step 5T22). Furthermore, after this, DEL3 is set to address AD.
Rewrite to DR2 and change the value of the above interrupt vector to
The process for returning to the monitor program in fLOMi3 is rewritten to the address (VDCTO 几2), and the interrupt process ends (step 5T2).
3). After the interrupt processing is completed, the program to be debugged is executed from ADI) 3, and when address ADD 2 is reached, an interrupt is generated, and processing for returning to the monitor program is executed as interrupt processing (step 5T).
24). At this point, it becomes possible to accept messages from the host machine 2 (because the monitor program is being executed), and the host machine 2 sends a message displaying the contents of the queue (Stella 7'5T25). In addition, the issued message is received and decoded in step 5T26),
Send the queue contents to host machine 2 (step 5)
T27).

Host machine 2 receives the message, displays the contents of the queue, and completes a series of debugging operations (step 5).
T28).

Also, if you want to add processing to the depacked program at the address ADDR3, step 5T1
1, the message “BONEALT IMEADD”
” is issued, the process of adding the value of the interrupt vector is rewritten to the written address in step 5T12, the process of adding is executed in step 5T22, and then step 8T2
The process flow described above is followed except that step ST25 is performed and steps ST25 and subsequent steps are unnecessary.

[1 Message regarding real-time debugging”) I
EALTIMg f'lG 几D", 1 BON HALTIM
The only difference is that the value of the interrupt vector is dynamically changed by ``EADD'' or the like.

〔Effect of the invention〕

As described above, according to the present invention, the value of the interrupt vector is rewritten by a message issued from the host machine, and after the interrupt processing is completed, the value of the vector is rewritten to the processing destination for returning to the monitor program. This has the effect of making it possible to perform various real-time debugging regardless of execution control of bug programs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a program debugging method according to an embodiment of the present invention and a conventional example, FIG. 2 is a flow chart showing its operation, and FIG. 3 is a flow chart showing the operation of a conventional program monitor. 1 is a target, 2 is a host machine, 3 is a debug register (DR), and 11 is a CPU 0. In the figure, the same reference numerals indicate the same or complementary parts. Patent Applicant: Mitsubishi Electric Corporation 1-Hoop': 7 To 11: Knock-out raccoon device (CplJ)

Claims (1)

[Claims] The host machine recognizes the execution address of the central processing unit in the target using the debug register, generates an interrupt signal when this execution address matches the set value, and sends and receives messages to and from the target. A program debugging method that dynamically rewrites the destination address of interrupt processing according to the contents of the program.