JPH01199436A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01199436A
JPH01199436A JP2479788A JP2479788A JPH01199436A JP H01199436 A JPH01199436 A JP H01199436A JP 2479788 A JP2479788 A JP 2479788A JP 2479788 A JP2479788 A JP 2479788A JP H01199436 A JPH01199436 A JP H01199436A
Authority
JP
Japan
Prior art keywords
mounting
chip
parts
component
mount
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2479788A
Other languages
Japanese (ja)
Inventor
Sakanori Ito
栄記 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2479788A priority Critical patent/JPH01199436A/en
Publication of JPH01199436A publication Critical patent/JPH01199436A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent the flow of a brazing metal to other component mounting parts at the time of mounting of a semiconductor chip and to contrive the improvement of the reliability of a semiconductor device by a method wherein protrusion parts are respectively provided at parts, which come into contact to the other component mounting parts, of a chip mounting part. CONSTITUTION:In a semiconductor device provided with a case 3 comprising a chip mounting part 1 for mounting a semiconductor chip and other component mounting parts 2 for mounting other components other than the semiconductor chip, protrusion parts 4 are respectively provided at parts, which come into contact to the mounting parts 2, of the mounting part 1. For example, in a field-effect transistor provided with the case 3 comprising the mounting part 1 for mounting a transistor chip, which is used as the semiconductor chip, and the mounting parts 2 for mounting other components other than the transistor chip, such as a dielectric substrate provided with strip lines for an internal matching circuit and a chip capacitor, the protrusion parts 4 are respectively provided at parts, which come into contact to the mounting parts 2 and are located in the input/output direotions, of the mounting part 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置分野に利用される。[Detailed description of the invention] [Industrial application field] The present invention is utilized in the field of semiconductor devices.

本発明は、半導体装置に関し、特にケースを改良した高
出力内部整合回路付の電界効果トランジスタに関する。
The present invention relates to a semiconductor device, and more particularly to a field effect transistor with an improved case and a high output internal matching circuit.

〔概要〕〔overview〕

本発明は、半導体チップをマウントするチップマウント
部と、前記半導体チップ以外の他部品をマウントする他
部品マウント部とを含むケースを有する半導体装置にお
いて、 前記チップマウント部の前記他部品マウント部に接する
部分に突起部を設けることにより、半導体チップマウン
ト時における他部品マウント部へのロー材の流れを防止
し、信頼性の向上を図ったものである。
The present invention provides a semiconductor device having a case including a chip mount section for mounting a semiconductor chip, and an other component mount section for mounting a component other than the semiconductor chip, wherein the chip mount section is in contact with the other component mount section. By providing protrusions on the parts, it is possible to prevent brazing material from flowing to other component mounting parts when mounting a semiconductor chip, thereby improving reliability.

〔従来の技術〕[Conventional technology]

従来、内部整合回路材の電界効果トランジスタのケース
では、トランジスタチップをマウントするチップマウン
ト部は、ストリップラインを形成する誘電体基板やチッ
プコンデンサなどのトランジスタチップ以外の他の部品
をマウントする他部品マウント部と、フラットかもしく
はチップマウント部が一段高くなるような形状となって
いた。
Conventionally, in the case of field-effect transistors using internal matching circuit materials, the chip mount part that mounts the transistor chip is used as a component mount part that mounts other components other than the transistor chip, such as a dielectric substrate forming a strip line or a chip capacitor. The chip mount part was either flat or had a raised chip mount part.

第2図(a)および(社)はかかる従来例の構造を示す
図で、同図(a)は上面図、同図(社)はそのA−A’
断面図である。ケース3は、チップマウント部1と他部
品マウント部2とを含み、チップマウント部1は他部品
マウント部2よりも一段高くなっている。
FIGS. 2(a) and 2(a) are diagrams showing the structure of such a conventional example; FIG. 2(a) is a top view, and FIG.
FIG. The case 3 includes a chip mount section 1 and an other component mount section 2, and the chip mount section 1 is higher than the other component mount section 2.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前述した従来のケース形状を有する半導体装置では、チ
ップマウント部が他部品マウント部とフラットかもしく
はチップマウント部全体が一段高くなっている形状をし
ているため、トランジスタチップをマウントする際、チ
ップマウントロー材が他部品マウント部へ流れてしまい
、トランジスタチップのマウント状態を悪くし、さらに
他部品に短絡を発生させるなど、信頼性を低下させる欠
点があった。
In the semiconductor device having the conventional case shape mentioned above, the chip mount part is either flat with the other component mount parts or the entire chip mount part is raised, so when mounting the transistor chip, the chip mount The brazing material flows to the mounting area of other components, which deteriorates the mounting condition of the transistor chip and further causes short circuits to other components, resulting in a reduction in reliability.

本発明の目的は、前記の欠点を除去することにより、半
導体チップをマウントする際、ロー材が他部品マウント
部へ流れることなく、信頼性の向上を図った半導体装置
を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which the reliability is improved by eliminating the above-mentioned drawbacks so that the brazing material does not flow to other component mounting parts when mounting a semiconductor chip.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、半導体チップをマウントするチップマウント
部と、前記半導体チップ以外の他の部品をマウントする
他部品マウント部とを含むケースを有する半導体装置に
おいて、前記チップマウント部の前記他部品マウント部
に接する部分に突起部を設けたことを特徴とする。
The present invention provides a semiconductor device having a case including a chip mount section for mounting a semiconductor chip and an other component mount section for mounting a component other than the semiconductor chip, in which the other component mount section of the chip mount section has A feature is that a protrusion is provided at the contacting part.

〔作用〕[Effect]

突起部は、チップマウント部の他部品マウント部に接す
る部分に設けられるので、半導体チップマウント時にお
けるロー材の流れを防止する。
Since the protrusion is provided at the part of the chip mount part that contacts the other component mount part, it prevents the brazing material from flowing when the semiconductor chip is mounted.

従って、半導体チップはしっかりと固着され、他部品に
短絡も生じることなく、信頼性の向上が可能となる。
Therefore, the semiconductor chip is firmly fixed, and short circuits do not occur to other components, making it possible to improve reliability.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を参照して説明する
Embodiments of the present invention will be described below with reference to the drawings.

第1図(a)は本発明の一実施例の要部を示す上面図、
第1図(b)はそのA−A’断面図で、内部整合回路用
の電界効果トランジスタの場合を示す。
FIG. 1(a) is a top view showing essential parts of an embodiment of the present invention;
FIG. 1(b) is a sectional view taken along the line AA', showing the case of a field effect transistor for an internal matching circuit.

本実施例は、半導体チップとしての図外のトランジスタ
チップをマウントするチップマウント部1と、前記トラ
ンジスタチップ以外の内部整合回路用のストリップライ
ンが設けられた誘電体基板やチップコンデンサなどの他
の部品をマウントする他部品マウント部2とを含むケー
ス3を有する電界効果トランジスタにおいて、チップマ
ウント部lの他部品マウント部2に接する入出力方向部
分に、突起部4を設けである。
This embodiment includes a chip mount part 1 for mounting a transistor chip (not shown) as a semiconductor chip, and other components other than the transistor chip, such as a dielectric substrate provided with a strip line for an internal matching circuit and a chip capacitor. In a field effect transistor having a case 3 including a component mount section 2 for mounting the chip mount section 1, a protrusion 4 is provided at a portion of the chip mount section l in the input/output direction that is in contact with the component mount section 2.

本発明の特徴は、第1図(a)および(b)において、
突起部4を設けたことにある。
The feature of the present invention is that in FIGS. 1(a) and (b),
This is because the protrusion 4 is provided.

本実施例によると、チップマウント部1にトランジスタ
チップをマウントする際に生じるロー材の流れは、突起
部4により阻止されて、他部品マウント部への流出は完
全に防止される。
According to this embodiment, the flow of brazing material that occurs when a transistor chip is mounted on the chip mount portion 1 is blocked by the protrusion portion 4, and flow to other component mount portions is completely prevented.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、チップマウント部の他
部品マウント部に接する部分に、突起部を設けることに
より、半導体チップをマウントする際のロー相流れを防
止し、チップマウントを安定確実にし、かつ他部品に短
絡も生じることなく、半導体装置の信頼性を向上させる
効果がある。
As explained above, the present invention prevents low-phase flow when mounting a semiconductor chip and makes the chip mount stable and reliable by providing a protrusion on the part of the chip mount that contacts the other component mount. Moreover, short circuits do not occur in other parts, and the reliability of the semiconductor device is improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)は本発明の一実施例の要部を示す上面図、
第1図(社)はそのA−A’断面部。 第2図(a)は従来例の要部を示す上面図、第2図ら)
はそのA−A’断面図。 1・・・チップマウント部、2・・・他部品マウント部
、3・・・ケース、4・・・突起部。 特許出願人 日本電気株式会社7.− 代理人  弁理士 井 出 直 孝 ゛1:+−ノアマ
ウント耶  3 :ケース2:地部品マウントs  4
:友起部 A−Kr面図 (b) 夷廁例の構造 肩 1 図 1:+−,プマウント部  3:ケー人2:Ali部品
マウント部 (a) A−A′Fr面図 (b) 従来例の構き 肩 2 図
FIG. 1(a) is a top view showing essential parts of an embodiment of the present invention;
Figure 1 (company) is the AA' cross section. Fig. 2 (a) is a top view showing the main parts of the conventional example, Fig. 2 et al.)
is a sectional view taken along line AA'. DESCRIPTION OF SYMBOLS 1...Chip mount part, 2...Other component mount part, 3...Case, 4...Protrusion part. Patent applicant: NEC Corporation7. − Agent Patent Attorney Nao Takashi Ide ゛1: +-Noah Mount Ya 3: Case 2: Ground Parts Mount s 4
: A-Kr side view of Yuki part (b) Structural shoulder of Issei example 1 Figure 1: +-, mount part 3: Case 2: Ali parts mount part (a) A-A'Fr side view (b) Figure 2 of the conventional example

Claims (1)

【特許請求の範囲】 1、半導体チップをマウントするチップマウント部(1
)と、前記半導体チップ以外の他の部品をマウントする
他部品マウント部(2)とを含むケース(3)を有する
半導体装置において、 前記チップマウント部の前記他部品マウント部に接する
部分に突起部(4)を設けた ことを特徴とする半導体装置。
[Claims] 1. A chip mount section (1) for mounting a semiconductor chip;
) and a case (3) including an other component mount part (2) for mounting a component other than the semiconductor chip, the semiconductor device having a protrusion in a part of the chip mount part that comes into contact with the other component mount part. A semiconductor device characterized by providing (4).
JP2479788A 1988-02-03 1988-02-03 Semiconductor device Pending JPH01199436A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2479788A JPH01199436A (en) 1988-02-03 1988-02-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2479788A JPH01199436A (en) 1988-02-03 1988-02-03 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01199436A true JPH01199436A (en) 1989-08-10

Family

ID=12148182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2479788A Pending JPH01199436A (en) 1988-02-03 1988-02-03 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01199436A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278193B1 (en) * 1998-12-07 2001-08-21 International Business Machines Corporation Optical sensing method to place flip chips

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278193B1 (en) * 1998-12-07 2001-08-21 International Business Machines Corporation Optical sensing method to place flip chips

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