JPH01196873A - Silicon carbide semiconductor device - Google Patents

Silicon carbide semiconductor device

Info

Publication number
JPH01196873A
JPH01196873A JP63022492A JP2249288A JPH01196873A JP H01196873 A JPH01196873 A JP H01196873A JP 63022492 A JP63022492 A JP 63022492A JP 2249288 A JP2249288 A JP 2249288A JP H01196873 A JPH01196873 A JP H01196873A
Authority
JP
Japan
Prior art keywords
silicon carbide
electrode
substrate
silicon
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63022492A
Other languages
Japanese (ja)
Inventor
Yoshihisa Fujii
藤井 良久
Akira Suzuki
彰 鈴木
Masaki Furukawa
勝紀 古川
Mitsuhiro Shigeta
光浩 繁田
Atsuko Ogura
小倉 敦子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP63022492A priority Critical patent/JPH01196873A/en
Publication of JPH01196873A publication Critical patent/JPH01196873A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827Vertical transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H01L29/8122Vertical transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To prevent leakage currents even under severe conditions such as a high temperature, large power, etc., by forming a first electrode onto the surface of an silicon carbide semiconductor layer shaped onto one surface of a substrate, a second electrode onto the other surface of the substrate and a third electrode onto the side face of the silicon carbide semiconductor layer. CONSTITUTION:A nickel film formed onto the rear of an silicon substrate 1 is used as a drain electrode 7, and a titanium-aluminum film shaped onto the projecting end face of an silicon carbide growth layer 2 having mesa structure is employed as a source electrode 6. Currents flowing between the source electrode 6 and the drain electrode 7 are controlled by fluctuating voltage applied to gate electrodes 8 and changing the width of depletion layers 9 spreading in the silicon carbide growth layer 2. Accordingly, an silicon carbide semiconductor device, in which leakage currents are not generated even under severe conditions such as a high temperature, large power, etc., and which has excellent characteristics, can be acquired.

Description

【発明の詳細な説明】 (技術分野) 本発明は炭化珪素半導体装置に関するものである。[Detailed description of the invention] (Technical field) The present invention relates to a silicon carbide semiconductor device.

(従来の技術) 珪素(St)半導体を初めとして、砒化ガリウム(Ga
As)やリン化ガリウム(GaP)等の化合物半導体材
料を用いたダイオード、トランジスタ、IC1LSI、
発光ダイオード、半導体レーザ、CCD等の半導体装置
がエレクトロニクスの各種分野で広く実用に供せられて
いる。一方、炭化珪素半導体はこれらの半導体材料に比
べて禁制帯幅が広く(2,2〜3.3eV)、また熱的
、化学的及び機械的に極めて安定で、放射線損傷にも強
いという特徴をもっている。従って、炭化珪素を用いた
半導体装置は他の半導体材料を用いた装置では使用困難
な高温、大電力、放射線照射等の苛酷な条件でも使用す
ることができ、高い信頬性と安定性を呈する装置として
広範な分野での応用が期待されている。
(Prior art) In addition to silicon (St) semiconductors, gallium arsenide (Ga
Diodes, transistors, IC1LSI, etc. using compound semiconductor materials such as As) and gallium phosphide (GaP),
Semiconductor devices such as light emitting diodes, semiconductor lasers, and CCDs are widely used in various fields of electronics. On the other hand, silicon carbide semiconductors have a wider forbidden band width (2.2 to 3.3 eV) than these semiconductor materials, are extremely stable thermally, chemically, and mechanically, and are resistant to radiation damage. There is. Therefore, semiconductor devices using silicon carbide can be used under harsh conditions such as high temperatures, high power, and radiation exposure, which are difficult to use with devices using other semiconductor materials, and exhibit high reliability and stability. The device is expected to be applied in a wide range of fields.

このように炭化珪素半導体装置は広範な応用分野が期待
されながら未だ実用化が阻まれている原因は、生産性を
考慮した工業的規模での量産に必要となる高品質で大面
積の炭化珪素単結晶を得るための結晶成長技術の確立が
遅れていることにある。従来、研究室規模で、昇華再結
晶法(レーリー法とも称される)等により成長させた炭
化珪素単結晶を用いて、あるいはこの単結晶上に気相成
長法や液相成長法でエピタキシャル成長させた炭化珪素
単結晶膜を用いてダイオードやI−ランジスタの製作が
試みられている。
Although silicon carbide semiconductor devices are expected to have a wide range of applications, their practical application is still hindered because of the high quality and large area silicon carbide required for mass production on an industrial scale with productivity in mind. This is because the establishment of crystal growth technology for obtaining single crystals has been delayed. Conventionally, on a laboratory scale, silicon carbide single crystals grown by sublimation recrystallization method (also called Rayleigh method) are used, or epitaxial growth is performed on this single crystal by vapor phase growth method or liquid phase growth method. Attempts have been made to fabricate diodes and I-transistors using silicon carbide single crystal films.

この技術はR,B、Campbell and It、
 −C,Chang+“5ilicon Carbid
e Junction Devices”、  in”
Sem1conductors and Semime
tals”、  eds、  R,K。
This technique was developed by R.B.Campbell and It.
-C,Chang+“5ilicon Carbid
e Junction Devices”, in”
Sem1 conductors and Semime
tals”, eds, R,K.

Willardson and A、C,Beer  
(Academic Press、NewYork、 
 1971)、  vol 7 、  Pa5t B 
Chap 9.P625〜P683に記載されている。
Willardson and A.C.Beer
(Academic Press, New York,
1971), vol 7, Pa5t B
Chap 9. It is described in P625 to P683.

しかしながら、上記方法では炭化珪素単結晶は小面積の
ものしか得られず、また該炭化珪素単結晶の寸法、形状
を制御することが困難であり、炭化珪素結晶に存在する
結晶多形の制御及び不純物濃度の制御も容易でなく、従
ってこのようにして製造された炭化珪素単結晶を用い、
工業的規模で半導体装置を製造することはできない。
However, with the above method, silicon carbide single crystals can only be obtained with a small area, and it is difficult to control the size and shape of the silicon carbide single crystals. It is not easy to control the impurity concentration, so using the silicon carbide single crystal produced in this way,
Semiconductor devices cannot be manufactured on an industrial scale.

最近、本発明者らは、気相成長法(CVD法)を用いる
ことによって、珪素単結晶基板上に良質で、且つ大面積
の炭化珪素単結晶を成長させる方法を確立し、特願昭5
8−76842号にて出願している。
Recently, the present inventors have established a method for growing high-quality, large-area silicon carbide single crystals on silicon single crystal substrates by using a vapor phase growth method (CVD method).
The application has been filed under No. 8-76842.

この方法は珪素単結晶基板上に低温CVD法で炭化珪素
薄膜を形成した後、昇温しでCVD法で炭化珪素単結晶
を成長させる技術である。この方法によれば、安価で人
手の容易な珪素単結晶基板を用いて結晶多形、不純物濃
度、寸法、形状等が制御された大面積で高品質の炭化珪
素単結晶膜を供給することができるとともに、この方法
は量産形態にも適し、高い生産性が期待される製造方法
である。さらに、上記発明により可能となった珪素基板
上の炭化珪素膜を用いてダイオード、トランジスタを初
めとする各種半導体装置を製作する方法についても特許
出願がなされている(特願昭58−246511号、同
58−249981号、同58−252157号)。
This method is a technique in which a silicon carbide thin film is formed on a silicon single crystal substrate by a low-temperature CVD method, and then a silicon carbide single crystal is grown by a CVD method while raising the temperature. According to this method, it is possible to supply a large-area, high-quality silicon carbide single-crystal film with controlled crystal polymorphism, impurity concentration, size, shape, etc. using a cheap and easy-to-handle silicon single-crystal substrate. This manufacturing method is suitable for mass production, and is expected to have high productivity. Furthermore, patent applications have been filed for methods of manufacturing various semiconductor devices including diodes and transistors using silicon carbide films on silicon substrates, which has been made possible by the above invention (Japanese Patent Application No. 58-246511, No. 58-249981, No. 58-252157).

従来、炭化珪素を用いた電界効果トランジスタとしては
、第4図(a) (b)に示すように、MrS型電界効
果トランジスタやショットキーゲート型電界効果トラン
ジスタ等が作製されている。
Conventionally, as field effect transistors using silicon carbide, MrS type field effect transistors, Schottky gate type field effect transistors, etc. have been manufactured as shown in FIGS. 4(a) and 4(b).

、第4図(a)に示す旧S型電界効果トランジスタは、
p型珪素単結晶基板31の表面に形成されたn型炭化珪
素成長層32及びn型炭化珪素成長層33(チャネル層
)と、該炭化珪素成長層33の表面に形成された絶縁層
34及びゲート電極38と、該ゲート電挽38を挾んで
炭化珪素成長層33の表面に形成されたn型不純物注入
層35及びドレイン電極37と、n型不純物注入層39
及びソース電極36とを有している。
, the old S-type field effect transistor shown in FIG. 4(a) is
An n-type silicon carbide growth layer 32 and an n-type silicon carbide growth layer 33 (channel layer) formed on the surface of a p-type silicon single crystal substrate 31, an insulating layer 34 formed on the surface of the silicon carbide growth layer 33, and Gate electrode 38 , n-type impurity implantation layer 35 and drain electrode 37 formed on the surface of silicon carbide growth layer 33 with gate electrode 38 in between, and n-type impurity implantation layer 39
and a source electrode 36.

また、第4図(b)に示すショットキーゲート型電界効
果トランジスタは、n型珪素単結晶基板41の表面に形
成されたP型炭化珪素成長層42及びn型炭化珪素成長
層43(チャネル層)と、該n型炭化珪素成長N43の
表面に形成されたゲート電極48と、該ゲート電極48
を挾んでn型炭化珪素成長層43の表面に形成されたド
レイン電極47及びソース電極46とを有している。
The Schottky gate field effect transistor shown in FIG. 4(b) also includes a P-type silicon carbide growth layer 42 and an n-type silicon carbide growth layer 43 (channel layer) formed on the surface of an n-type silicon single crystal substrate 41. ), a gate electrode 48 formed on the surface of the n-type silicon carbide growth N43, and the gate electrode 48
It has a drain electrode 47 and a source electrode 46 formed on the surface of n-type silicon carbide growth layer 43 sandwiching them therebetween.

上記のような構造の電界効果トランジスタは、ともにゲ
ート電極38.48に印加する電圧を変えてチャネル層
33.43内に広がる空乏層幅を変えることにより、ソ
ース電極36.46−ドレイン電極37.47間に流れ
る電流を制御することができる。
In the field effect transistor having the above structure, the width of the depletion layer extending within the channel layer 33, 43 is changed by changing the voltage applied to both the gate electrodes 38, 48, and the width of the depletion layer extending from the source electrode 36, 46 to the drain electrode 37, . 47 can be controlled.

(発明が解決しようとする課題) ところが、このような従来構造の電界効果トランジスタ
はプレーナ構造であり、次のような問題を有していた。
(Problems to be Solved by the Invention) However, such a conventional field effect transistor has a planar structure and has the following problems.

■いずれの構造の電界効果トランジスタにおいても、チ
ャネル層33.43と、珪素基板31.41との電気的
絶縁分離は、炭化珪素成長層中に形成されたpn接合に
よってなされている。ところが、現在の結晶成長技術に
よって得られる上記炭化珪素p’n接合は、高温などの
苛酷な条件では充分な整流性を示さず、このような苛酷
な条件では珪素基板31.41あるいは下部炭化珪素成
長層32.42を流れるリーク電流が大きくなる。
(2) In field effect transistors of either structure, electrical insulation separation between channel layer 33.43 and silicon substrate 31.41 is achieved by a pn junction formed in a silicon carbide growth layer. However, the silicon carbide p'n junction obtained by current crystal growth technology does not exhibit sufficient rectification properties under harsh conditions such as high temperatures; The leakage current flowing through the growth layers 32 and 42 increases.

■トランジスタを大電流、大出力の条件で使用するには
、複数個の素子を並列に接続することが望ましい。しか
し、従来のプレーナ構造の電界効果トランジスタでは、
そのような構造にすると構造が複雑となるため、複数個
の素子を並列に接続することができない。
■In order to use transistors under conditions of large current and large output, it is desirable to connect multiple elements in parallel. However, in the conventional planar structure field effect transistor,
Such a structure would complicate the structure, making it impossible to connect multiple elements in parallel.

(課題を解決するための手段) 本発明は上述の実情に鑑みてなされたものであり、その
目的とするところは、高温、大電力等の苛酷な条件にお
いても良好な特性を示し、また構造が複雑化することな
く複数個の素子を並列に接続することが可能な炭化珪素
半導体装置を提供することにある。
(Means for Solving the Problems) The present invention has been made in view of the above-mentioned circumstances, and its purpose is to provide a structure that exhibits good characteristics even under severe conditions such as high temperature and high power. An object of the present invention is to provide a silicon carbide semiconductor device in which a plurality of elements can be connected in parallel without complication.

(課題を解決するための手段) 本発明の炭化珪素半導体装置は、基板の一方の面に設け
られた炭化珪素半導体層と、該炭化珪素半導体層の表面
に設けられた第1の電極と、該基板の他方の面に設けら
れた第2の電極と、該炭化珪素半導体層の側面上に設け
られた第3の電極とを備えており、そのごとにより上記
目的が達成される。
(Means for Solving the Problems) A silicon carbide semiconductor device of the present invention includes a silicon carbide semiconductor layer provided on one surface of a substrate, a first electrode provided on the surface of the silicon carbide semiconductor layer, The semiconductor device includes a second electrode provided on the other surface of the substrate and a third electrode provided on the side surface of the silicon carbide semiconductor layer, thereby achieving the above object.

(作用) 基板の一方の面に設けた炭化珪素半導体層の表面に第1
の電極を設けると共に、基板の他方の面に第2の電極を
設けて、電流が炭化珪素半導体層の膜厚方向を流れるよ
うに構成し、該炭化珪素半導体層の側面上に設けられた
第3の電極に印加する電圧によって、前記電流を制御す
るように構成することにより、電流はこの炭化珪素半導
体にて形成されるチャネル層だけを流れることになり、
リーク電流を生じることがない。また、複数の素子を基
板に並列に設け、該基板の片側面を共通の電極として使
用できるので、素子構造を複雑化することなく複数個の
素子を並列に接続することがで、きる。
(Function) A first layer is formed on the surface of the silicon carbide semiconductor layer provided on one side of the substrate.
A second electrode is provided on the other surface of the substrate so that a current flows in the thickness direction of the silicon carbide semiconductor layer, and a second electrode is provided on the side surface of the silicon carbide semiconductor layer. By configuring the current to be controlled by the voltage applied to the electrode No. 3, the current flows only through the channel layer formed of this silicon carbide semiconductor,
No leakage current occurs. Furthermore, since a plurality of elements can be provided in parallel on a substrate and one side of the substrate can be used as a common electrode, a plurality of elements can be connected in parallel without complicating the element structure.

(実施例) 以下に本発明の一実施例として、珪素基板上に成長させ
た炭化珪素半導体を用いた縦型電界効果トランジスタの
構成と、その製造方法を説明する。
(Example) As an example of the present invention, the structure of a vertical field effect transistor using a silicon carbide semiconductor grown on a silicon substrate and its manufacturing method will be described below.

珪素基板上に炭化珪素単結晶膜を形成する方法について
は、前述の方法のいずれかを採用することができる。ま
た、珪素基板上に部分的に炭化珪素を形成するには選択
成長技術を用いても良いし、または珪素基板全面に炭化
珪素単結晶膜を形成した後、炭化珪素単結晶膜を選択的
にエツチング除去しても良い。
As for the method of forming a silicon carbide single crystal film on a silicon substrate, any of the above-mentioned methods can be adopted. Alternatively, a selective growth technique may be used to partially form silicon carbide on a silicon substrate, or a silicon carbide single crystal film may be selectively grown after forming a silicon carbide single crystal film on the entire surface of the silicon substrate. It may be removed by etching.

上記選択成長技術は、珪素基板上にシリコン酸化膜ある
いはシリコン窒化膜を部分的に形成し、次にその表面全
面に炭化珪素を形成した後、前記シリコン酸化膜あるい
はシリコン窒化膜を剥離し、この膜の剥離と同時に膜表
面の炭化珪素も剥離させることにより、珪素基板上に炭
化珪素を部分的に形成する技術である。
The selective growth technique described above involves forming a silicon oxide film or silicon nitride film partially on a silicon substrate, then forming silicon carbide on the entire surface, and then peeling off the silicon oxide film or silicon nitride film. This is a technique for partially forming silicon carbide on a silicon substrate by peeling off the film and simultaneously peeling off the silicon carbide on the film surface.

ズ緊l飢上 縦型炭化珪素旧S型電界効果トランジスタこの縦型炭化
珪素旧S型電界効果トランジスタは以下のようにして作
製される。
Vertical silicon carbide old S-type field effect transistor This vertical silicon carbide old S-type field effect transistor is manufactured as follows.

第2図(a)に示すように、n型珪素単結晶基板lの表
面の一部に、炭化珪素単結晶からなる炭化珪素成長層2
をモノシラン(Sil14)とプロパン(C,H,)を
用いた化学的気相成長法(CVD)法を用いて厚さ約5
μm形成する。この炭化珪素成長層2は不純物を添加し
ないで形成し、形成された成長層2の導電型はn型を示
す。次いで、その炭化珪素成長層2の表面の一部にアル
ミニウム層3を円形状(直径約2μm)に真空蒸着する
(第2図(b)及び山))。
As shown in FIG. 2(a), a silicon carbide growth layer 2 made of a silicon carbide single crystal is formed on a part of the surface of an n-type silicon single crystal substrate l.
The film was made to a thickness of approximately 5 cm using chemical vapor deposition (CVD) using monosilane (Sil14) and propane (C,H,).
μm is formed. This silicon carbide growth layer 2 is formed without adding impurities, and the conductivity type of the formed growth layer 2 is n-type. Next, an aluminum layer 3 is vacuum-deposited in a circular shape (about 2 μm in diameter) on a part of the surface of the silicon carbide growth layer 2 (FIG. 2(b) and peaks).

次に、このアルミニウム層3をマスクとして、リアクテ
ィブイオンエツチングを行うことにより、第2図(C)
に示すようなメサ構造の炭化珪素成長層2を得る。次に
、該成長層2の表面に形成されたアルミニウム層3をエ
ツチング除去した後、このものを酸素雰囲気中で105
0°C16時間、熱処理することにより、炭化珪素成長
層2及び珪素基板1表面上に絶縁用熱酸化膜(SiO□
)4を形成する。
Next, using this aluminum layer 3 as a mask, reactive ion etching is performed, as shown in FIG. 2(C).
A silicon carbide growth layer 2 having a mesa structure as shown in FIG. Next, after removing the aluminum layer 3 formed on the surface of the grown layer 2, the aluminum layer 3 was etched in an oxygen atmosphere.
By heat treatment at 0°C for 16 hours, an insulating thermal oxide film (SiO□
) form 4.

炭化珪素成長層2の表面に形成された酸化膜4の膜厚は
約50nmである(第2図(d))。次いで、炭化珪素
成長層2表面に形成されている酸化膜4をフォトリソグ
ラフィを用いることによってエツチング除去すると共に
、フォトレジスト5を第2図(e)に示すように、珪素
基板1表面の酸化膜4の表面及び炭化珪素成長層2の突
出端面2aの周囲とその炭化珪素成長層2の突出端部の
角部表面に形成された酸化膜4との間に亘ってそれぞれ
形成する。
The thickness of oxide film 4 formed on the surface of silicon carbide growth layer 2 is approximately 50 nm (FIG. 2(d)). Next, the oxide film 4 formed on the surface of the silicon carbide growth layer 2 is removed by etching using photolithography, and the photoresist 5 is removed by etching the oxide film 4 formed on the surface of the silicon substrate 1 as shown in FIG. 4 and the periphery of the protruding end surface 2 a of the silicon carbide growth layer 2 and between the oxide film 4 formed on the corner surface of the protruding end of the silicon carbide growth layer 2 .

次に、このような積層体の表面全面にチタン−アルミニ
ウムaを真空蒸着しく第2図(f)) 、その後フォト
レジスト5を除去する。フォトレジスト50表面に形成
されたチタン−アルミニウム膜はフォトレジスト5の除
去と同時に除去され、炭化珪素成長層2の突出端面にソ
ース電極6及び成長層2の側面上にゲート電極8が形成
される。その後、珪素基板全面面にオーミック電極とし
てニッケルを真空蒸着してドレイン電極7を形成し、第
1図(a)及び第2図(g)に示す構成の炭化珪素半導
体装置を得る。
Next, titanium-aluminum a is vacuum-deposited on the entire surface of such a laminate (FIG. 2(f)), and then the photoresist 5 is removed. The titanium-aluminum film formed on the surface of photoresist 50 is removed at the same time as photoresist 5 is removed, and source electrode 6 is formed on the protruding end surface of silicon carbide growth layer 2 and gate electrode 8 is formed on the side surface of growth layer 2. . Thereafter, nickel is vacuum-deposited as an ohmic electrode on the entire surface of the silicon substrate to form a drain electrode 7, thereby obtaining a silicon carbide semiconductor device having the structure shown in FIGS. 1(a) and 2(g).

このようにして作製された炭化珪素半導体装置は、珪素
基板1裏面に形成されたニッケル膜をドレイン電極7と
して用い、またメサ構造の炭化珪素成長層2の突出端面
に形成されたチタン−アルミニウム膜をソース電極6と
して用い、このソース電極6及びドレイン電極7間に流
れる電流を上記ゲート電極8に印加する電圧を変えて炭
化珪素成長N2内に広がる空乏層9幅を変化させること
により制御し得る電界効果トランジスタである。
The silicon carbide semiconductor device manufactured in this way uses the nickel film formed on the back surface of silicon substrate 1 as drain electrode 7, and the titanium-aluminum film formed on the protruding end surface of silicon carbide growth layer 2 having a mesa structure. can be used as the source electrode 6, and the current flowing between the source electrode 6 and the drain electrode 7 can be controlled by changing the voltage applied to the gate electrode 8 and changing the width of the depletion layer 9 that spreads in the silicon carbide growth N2. It is a field effect transistor.

なお、上記実施例において、絶縁膜(熱酸化膜SiO□
)4は炭化珪素成長層2及び珪素基板1を熱処理するこ
とにより形成したが、この絶縁膜4はスパッタリング、
CVD法等の他の方法により、炭化珪素成長層2及び珪
素基板1表面に直接形成しても良い。
Note that in the above embodiment, an insulating film (thermal oxide film SiO□
) 4 was formed by heat treating silicon carbide growth layer 2 and silicon substrate 1, but this insulating film 4 was formed by sputtering,
It may also be formed directly on the silicon carbide growth layer 2 and the surface of the silicon substrate 1 by other methods such as the CVD method.

尖施炎又 縦型炭化珪素ショットキーゲート型電界効果トランジス
タ この縦型炭化珪素ショットキーゲート型電界効果トラン
ジスタは以下のようにして作製される。
Vertical Silicon Carbide Schottky Gate Field Effect Transistor This vertical silicon carbide Schottky gate field effect transistor is manufactured as follows.

第3図(a)に示すように、n型珪素I′n結晶基板1
1の表面に、モノシラン(S i II a )とプロ
パン(c :l II 8 )を用いた化学的気相成長
法(CVD)法により、窒素ドナーを用いたn゛型炭化
珪素成長層L2aを厚さ0.1 μm成長させる。次い
で、成長層12aの表面に不純物を添加しないでCVD
法によりn型炭化珪素成長層12bを厚さ5μm成長さ
せ、さらにその表面に窒素ドナーを用いたn°型型化化
珪素成長層12c厚さ0.1 μm成長させる。次に、
第3図(b)に示すように、上記成長層付基板表面のn
゛型型化化珪素成長層12c表面にアルミニウムを円形
状(直径3μm)に真空蒸着して複数個のアルミニウム
膜13を形成する。次に、それらのアルミニウム膜13
をマスクとして、リアクティブイオンエツチングを行う
ことにより、第3図(C)に示すようなメサ構造の炭化
珪素成長層12 (12a 、12b 、12c)を得
る。次に、この炭化珪素成長層12上のアルミニウム膜
13をエンチング除去した後、この積層体を酸素雰囲気
中で1050°C16時間の熱処理を行うことにより、
炭化珪素成長層12の表面に絶縁用熱酸化膜(SiO□
)14を形成する(第3図(d))。次いで、炭化珪素
成長層12の突出端面に形成された酸化膜14のみを除
去し、そこにオーミック電極として、ニッケルを真空蒸
着してソース電極16を形成する (第3図(e))。
As shown in FIG. 3(a), an n-type silicon I'n crystal substrate 1
An n-type silicon carbide growth layer L2a using a nitrogen donor is formed on the surface of 1 by chemical vapor deposition (CVD) using monosilane (S i II a ) and propane (c:l II 8 ). Grow to a thickness of 0.1 μm. Next, CVD is performed without adding impurities to the surface of the growth layer 12a.
An n-type silicon carbide growth layer 12b is grown to a thickness of 5 μm using the method, and an n°-type silicon carbide growth layer 12c using a nitrogen donor is grown to a thickness of 0.1 μm on the surface thereof. next,
As shown in FIG. 3(b), n on the surface of the substrate with the growth layer
A plurality of aluminum films 13 are formed by vacuum-depositing aluminum in a circular shape (diameter 3 μm) on the surface of the shaped silicon growth layer 12c. Next, those aluminum films 13
By performing reactive ion etching using as a mask, silicon carbide growth layers 12 (12a, 12b, 12c) having a mesa structure as shown in FIG. 3(C) are obtained. Next, after etching and removing the aluminum film 13 on this silicon carbide growth layer 12, this laminate is heat-treated at 1050°C for 16 hours in an oxygen atmosphere.
An insulating thermal oxide film (SiO□
) 14 (Fig. 3(d)). Next, only the oxide film 14 formed on the protruding end face of the silicon carbide growth layer 12 is removed, and nickel is vacuum-deposited thereon as an ohmic electrode to form a source electrode 16 (FIG. 3(e)).

次に、炭化珪素成長層12側面の酸化膜14を除去し、
次いでフォトレジスト15を第3図(f)に示すように
ソース電極16から炭化珪素成長層12の側面の上端部
に亘って、それらを覆うように形成する。次いで、その
積層体の表面全面に白金を真空蒸着して白金膜18を形
成した後、前記フォトレジスト15及びフォトレジスト
15表面の白金膜18を除去する。その後、珪素基板1
裏面にニッケルを真空蒸着することによりオーミック電
極としてドレイン電極17を形成し、第1図(b)及び
第3図(8)に示す構造の炭化珪素半導体装置が得られ
る。
Next, oxide film 14 on the side surface of silicon carbide growth layer 12 is removed,
Next, as shown in FIG. 3(f), photoresist 15 is formed from source electrode 16 to the upper end of the side surface of silicon carbide growth layer 12 so as to cover them. Next, platinum is vacuum-deposited over the entire surface of the laminate to form a platinum film 18, and then the photoresist 15 and the platinum film 18 on the surface of the photoresist 15 are removed. After that, silicon substrate 1
A drain electrode 17 is formed as an ohmic electrode by vacuum-depositing nickel on the back surface, and a silicon carbide semiconductor device having the structure shown in FIG. 1(b) and FIG. 3(8) is obtained.

上記のようにして得られた炭化珪素半導体装置も実施例
1と同様に、珪素基板11裏面に形成されたニッケル膜
及びメサ構造の炭化珪素成長層12上部に形成されたニ
ッケル膜をそれぞれドレイン電極17及びソース電極1
6として用い、ソース・ドレイン電極16.17間に流
れる電流を、炭化珪素成長層12とショットキー接合を
形成している白金ゲート電極18に印加する電圧を変え
ることにより、炭化珪素成長層I2内に広がる空乏層1
9幅を変化させて制御し得る縦型ショットキーゲート型
電界効果1〜ランジスタである。
In the silicon carbide semiconductor device obtained as described above, similarly to Example 1, the nickel film formed on the back surface of silicon substrate 11 and the nickel film formed on the top of mesa-structured silicon carbide growth layer 12 are used as drain electrodes, respectively. 17 and source electrode 1
By changing the voltage applied to the platinum gate electrode 18 forming a Schottky junction with the silicon carbide growth layer 12, the current flowing between the source and drain electrodes 16 and 17 is applied to the silicon carbide growth layer I2. Depletion layer 1 spreads over
9. This is a vertical Schottky gate field effect transistor whose width can be controlled by changing it.

しかも、本実施例に示した作製工程によれば、上記のよ
うに基板11に並列に配置される各複数個の素子に対し
て、珪素基板11表面に形成したニッケル膜17がドレ
イン電極として共通に使用され、また各素子に形成した
白金ゲート電極18が連続しているので、各素子のソー
ス電極16を結ぶことによって容易に複数個の素子を並
列に接続することができる。
Moreover, according to the manufacturing process shown in this embodiment, the nickel film 17 formed on the surface of the silicon substrate 11 is used as a common drain electrode for each of the plurality of elements arranged in parallel on the substrate 11 as described above. Furthermore, since the platinum gate electrodes 18 formed on each element are continuous, a plurality of elements can be easily connected in parallel by connecting the source electrodes 16 of each element.

なお、上記実施例において、ショットキーゲート用電極
材料として、白金を用いたが、該電極材料は金(Au)
等の炭化珪素とショットキー接合を形成し得る他の材料
を用いても良い。
In addition, in the above example, platinum was used as the electrode material for the Schottky gate, but the electrode material was gold (Au).
Other materials that can form a Schottky junction with silicon carbide may also be used.

以上の実施例1及び2で作製された電界効果トランジス
タは、室温においても従来のプレーナ型トランジスタに
比べて以下のような良好な特性を示した。
The field effect transistors manufactured in Examples 1 and 2 above exhibited the following favorable characteristics compared to conventional planar transistors even at room temperature.

従来のトランジスタの相互コンダクタンスの値は、プレ
ーナ構造のMIS型電界効果トランジスタ(第4図(a
)に示した)で0.8mS/mm、ショットキーゲート
型電界効果トランジスタ (第4図(b)に示した)で
1.7mS/mmであった。ところが、本発明の縦型の
場合では、相互コンダクタンスの値は、旧S型電界効果
トランジスタ (第1図(a)に示した)で2mS/m
m、ショットキーゲート型電界効果トランジスタ (第
1図(b)に示した)で2.5mS/mmであった。
The mutual conductance value of a conventional transistor is a planar MIS field effect transistor (Fig. 4(a)).
) was 0.8 mS/mm, and the Schottky gate field effect transistor (shown in FIG. 4(b)) was 1.7 mS/mm. However, in the case of the vertical type of the present invention, the value of mutual conductance is 2 mS/m in the old S-type field effect transistor (shown in Fig. 1(a)).
m, and 2.5 mS/mm for a Schottky gate field effect transistor (shown in FIG. 1(b)).

また、本発明のトランジスタは、400°Cの高温にお
いても特性劣化が少なかった。つまり、400 ’Cに
おける相互コンダクタンスの値は、従来のプレーナ構造
の旧S型電界効果トランジスタで0.05m5/nun
、ショットキーゲート型電界効果トランジスタで0.1
5m5/mmまで特性が低下する。ところが、本発明の
縦型の場合、400°Cにおける相互コンダクタンスの
値は、旧S型電界効果トランジスタで1.5ms/mm
 、ショットキーゲート型電界効果トランジスタで2.
3mS/mmであった。また、実施例2による並列接続
素子において、大電流動作が可能なことも確認された。
Further, the transistor of the present invention showed little characteristic deterioration even at a high temperature of 400°C. In other words, the value of transconductance at 400'C is 0.05m5/nun for a conventional S-type field effect transistor with a planar structure.
, 0.1 for Schottky gate field effect transistor
The characteristics deteriorate to 5m5/mm. However, in the case of the vertical type of the present invention, the value of mutual conductance at 400°C is 1.5 ms/mm for the old S-type field effect transistor.
, 2. Schottky gate field effect transistor.
It was 3mS/mm. It was also confirmed that the parallel connected element according to Example 2 was capable of large current operation.

(発明の効果) このように本発明によれば、高温、大電力等の苛酷な条
件でもリーク電流を生じることのない傍れた特性の炭化
珪素半導体装置を得ることができる。しかも、珪素基板
を共通の電極として使用することができるので、複数個
の素子を並列に接続することも可能となる。従って、従
来の半導体装置では使用不可能であった、大電力、大出
力の条件で使用することができる構造の簡単な炭化珪素
半導体装置を提供することができる。
(Effects of the Invention) As described above, according to the present invention, it is possible to obtain a silicon carbide semiconductor device with excellent characteristics that does not generate leakage current even under severe conditions such as high temperature and high power. Moreover, since the silicon substrate can be used as a common electrode, it is also possible to connect a plurality of elements in parallel. Therefore, it is possible to provide a silicon carbide semiconductor device with a simple structure that can be used under conditions of high power and high output, which have not been possible with conventional semiconductor devices.

↓−皿■匁遍厘笈疲労 第1図は本発明による縦型炭化珪素電界効果トランジス
タの一実施例を示し、第1図(a)は旧S型電界効果ト
ランジスタの断面図、第1図(b)はショットキーゲー
ト型電界効果トランジスタの断面図、第2図(a)〜(
(至)は本発明による旧S型の縦型炭化珪素電界効果ト
ランジスタの作製工程の一実施例を示す断面図、第2図
(h)は第2図(b)の平面図、第3図(a)〜((イ
)は本発明によるショットキーゲート型の縦型炭化珪素
電界効果トランジスタの作製工程の一実施例を示す断面
図、第4図(a)は従来の旧S型の電界効果トランジス
タの断面図、第4図(b)は従来のショットキーゲート
型の電界効果トランジスタの断面図である。
↓-Plate■MomehenkuRikofatigue Figure 1 shows an embodiment of the vertical silicon carbide field effect transistor according to the present invention, and Figure 1 (a) is a cross-sectional view of the old S-type field effect transistor. (b) is a cross-sectional view of a Schottky gate field effect transistor;
(to) is a cross-sectional view showing an example of the manufacturing process of the old S-type vertical silicon carbide field effect transistor according to the present invention, FIG. 2(h) is a plan view of FIG. 2(b), and FIG. (a) to ((a) are cross-sectional views showing an example of the manufacturing process of a Schottky gate type vertical silicon carbide field effect transistor according to the present invention, and FIG. 4(a) is a conventional S-type electric field effect transistor. A cross-sectional view of an effect transistor, FIG. 4(b) is a cross-sectional view of a conventional Schottky gate type field effect transistor.

1、11・・・珪素基板、2.12・・・炭化珪素成長
層、6.16・・・ソース電極(第1の電極)、7.1
7・・・ドレイン電極(第2の電極)、8.18・・・
ゲート電極(第3の電極)。
1, 11...Silicon substrate, 2.12...Silicon carbide growth layer, 6.16...Source electrode (first electrode), 7.1
7... Drain electrode (second electrode), 8.18...
Gate electrode (third electrode).

以上that's all

Claims (1)

【特許請求の範囲】[Claims] 1、基板の一方の面に設けられた炭化珪素半導体層と、
該炭化珪素半導体層の表面に設けられた第1の電極と、
該基板の他方の面に設けられた第2の電極と、該炭化珪
素半導体層の側面上に設けられた第3の電極とを備えた
炭化珪素半導体装置。
1. A silicon carbide semiconductor layer provided on one surface of the substrate;
a first electrode provided on the surface of the silicon carbide semiconductor layer;
A silicon carbide semiconductor device comprising a second electrode provided on the other surface of the substrate and a third electrode provided on the side surface of the silicon carbide semiconductor layer.
JP63022492A 1988-02-02 1988-02-02 Silicon carbide semiconductor device Pending JPH01196873A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63022492A JPH01196873A (en) 1988-02-02 1988-02-02 Silicon carbide semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63022492A JPH01196873A (en) 1988-02-02 1988-02-02 Silicon carbide semiconductor device

Publications (1)

Publication Number Publication Date
JPH01196873A true JPH01196873A (en) 1989-08-08

Family

ID=12084229

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63022492A Pending JPH01196873A (en) 1988-02-02 1988-02-02 Silicon carbide semiconductor device

Country Status (1)

Country Link
JP (1) JPH01196873A (en)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5170231A (en) * 1990-05-24 1992-12-08 Sharp Kabushiki Kaisha Silicon carbide field-effect transistor with improved breakdown voltage and low leakage current
US5349207A (en) * 1993-02-22 1994-09-20 Texas Instruments Incorporated Silicon carbide wafer bonded to a silicon wafer
EP0726604A2 (en) * 1995-02-08 1996-08-14 Ngk Insulators, Ltd. MIS device and method of manufacturing the same
WO1997033322A1 (en) * 1996-03-04 1997-09-12 Daimler-Benz Aktiengesellschaft Power field effect transistor
US5747831A (en) * 1994-07-01 1998-05-05 Daimler-Benz Aktiengesellschaft SIC field-effect transistor array with ring type trenches and method of producing them
JPH11214405A (en) * 1998-01-28 1999-08-06 Sanyo Electric Co Ltd Sic semiconductor device and its manufacture
US6133587A (en) * 1996-01-23 2000-10-17 Denso Corporation Silicon carbide semiconductor device and process for manufacturing same
US6686616B1 (en) * 2000-05-10 2004-02-03 Cree, Inc. Silicon carbide metal-semiconductor field effect transistors
US6902964B2 (en) 2001-10-24 2005-06-07 Cree, Inc. Methods of fabricating delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure
US6956239B2 (en) 2002-11-26 2005-10-18 Cree, Inc. Transistors having buried p-type layers beneath the source region
US7265399B2 (en) 2004-10-29 2007-09-04 Cree, Inc. Asymetric layout structures for transistors and methods of fabricating the same
US7326962B2 (en) 2004-12-15 2008-02-05 Cree, Inc. Transistors having buried N-type and P-type regions beneath the source region and methods of fabricating the same
US7348612B2 (en) 2004-10-29 2008-03-25 Cree, Inc. Metal-semiconductor field effect transistors (MESFETs) having drains coupled to the substrate and methods of fabricating the same
US7402844B2 (en) 2005-11-29 2008-07-22 Cree, Inc. Metal semiconductor field effect transistors (MESFETS) having channels of varying thicknesses and related methods
US7646043B2 (en) 2006-09-28 2010-01-12 Cree, Inc. Transistors having buried p-type layers coupled to the gate
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
US8203185B2 (en) 2005-06-21 2012-06-19 Cree, Inc. Semiconductor devices having varying electrode widths to provide non-uniform gate pitches and related methods

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5170231A (en) * 1990-05-24 1992-12-08 Sharp Kabushiki Kaisha Silicon carbide field-effect transistor with improved breakdown voltage and low leakage current
US5349207A (en) * 1993-02-22 1994-09-20 Texas Instruments Incorporated Silicon carbide wafer bonded to a silicon wafer
US5441911A (en) * 1993-02-22 1995-08-15 Texas Instruments Incorporated Silicon carbide wafer bonded to a silicon wafer
US5747831A (en) * 1994-07-01 1998-05-05 Daimler-Benz Aktiengesellschaft SIC field-effect transistor array with ring type trenches and method of producing them
EP0726604A2 (en) * 1995-02-08 1996-08-14 Ngk Insulators, Ltd. MIS device and method of manufacturing the same
EP0726604A3 (en) * 1995-02-08 1997-09-24 Ngk Insulators Ltd MIS device and method of manufacturing the same
US6002143A (en) * 1995-02-08 1999-12-14 Ngk Insulators, Ltd. Hybrid vertical type power semiconductor device
US6025233A (en) * 1995-02-08 2000-02-15 Ngk Insulators, Ltd. Method of manufacturing a semiconductor device
US6133587A (en) * 1996-01-23 2000-10-17 Denso Corporation Silicon carbide semiconductor device and process for manufacturing same
WO1997033322A1 (en) * 1996-03-04 1997-09-12 Daimler-Benz Aktiengesellschaft Power field effect transistor
JPH11214405A (en) * 1998-01-28 1999-08-06 Sanyo Electric Co Ltd Sic semiconductor device and its manufacture
US6686616B1 (en) * 2000-05-10 2004-02-03 Cree, Inc. Silicon carbide metal-semiconductor field effect transistors
US7067361B2 (en) 2000-05-10 2006-06-27 Cree, Inc. Methods of fabricating silicon carbide metal-semiconductor field effect transistors
US6902964B2 (en) 2001-10-24 2005-06-07 Cree, Inc. Methods of fabricating delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure
US6906350B2 (en) 2001-10-24 2005-06-14 Cree, Inc. Delta doped silicon carbide metal-semiconductor field effect transistors having a gate disposed in a double recess structure
US6956239B2 (en) 2002-11-26 2005-10-18 Cree, Inc. Transistors having buried p-type layers beneath the source region
US7297580B2 (en) 2002-11-26 2007-11-20 Cree, Inc. Methods of fabricating transistors having buried p-type layers beneath the source region
US7265399B2 (en) 2004-10-29 2007-09-04 Cree, Inc. Asymetric layout structures for transistors and methods of fabricating the same
US7348612B2 (en) 2004-10-29 2008-03-25 Cree, Inc. Metal-semiconductor field effect transistors (MESFETs) having drains coupled to the substrate and methods of fabricating the same
US7326962B2 (en) 2004-12-15 2008-02-05 Cree, Inc. Transistors having buried N-type and P-type regions beneath the source region and methods of fabricating the same
US8203185B2 (en) 2005-06-21 2012-06-19 Cree, Inc. Semiconductor devices having varying electrode widths to provide non-uniform gate pitches and related methods
US7402844B2 (en) 2005-11-29 2008-07-22 Cree, Inc. Metal semiconductor field effect transistors (MESFETS) having channels of varying thicknesses and related methods
US7646043B2 (en) 2006-09-28 2010-01-12 Cree, Inc. Transistors having buried p-type layers coupled to the gate
US7943972B2 (en) 2006-09-28 2011-05-17 Cree, Inc. Methods of fabricating transistors having buried P-type layers coupled to the gate
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
US8389385B2 (en) 2009-02-04 2013-03-05 Micron Technology, Inc. Semiconductor material manufacture

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