JPH01195549A - History information memory - Google Patents

Abstract

PURPOSE:To easily and effectively check the faults, etc., by using a software instruction in a program to instruct a part of a processing action of an information processing system which stores the history information. CONSTITUTION:When an information processing system detects a wrong processing result during the successive execution of a program, the control is shifted with execution of a BRANCH instruction and the TRACER and LOGOUT instructions are carried out. Then a log-out signal 118 is transmitted from an instruction control part 2 and a log-out instruction signal 119 is supplied to a diagnosis control part 3. Thus a reading signal 113 is delivered and the history information are successively read out of a memory part 4 and sent to the part 3 as the history read data 52.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a history information storage device, and more particularly to a history information storage device with an improved method for storing history information of processing operations of an information processing system.

[Conventional technology]

Information processing systems including computers are commonly used in fields such as data processing and data communications. In recent years, such information processing systems have become increasingly complex and include increasingly sophisticated functions. However, it is often extremely difficult to investigate and analyze failures that occur during the operation of an information processing system and to determine the cause.

As a method of understanding the specific occurrence of such a failure, there is a method of using a history information storage device that sequentially stores processing operations of an information processing system. This history information storage device can capture specific data on processing operations of an information processing system, and is therefore extremely useful in investigating the cause of the above-mentioned failures.

[Problem to be solved by the invention]

The conventional history information storage device described above has a limited storage capacity, and it is actually impossible to have enough storage capacity to store all the processing operations in various cases, so it is prone to failure. The disadvantage is that data necessary to clarify the cause of occurrence is often not stored.

In addition, the functional configuration of recent information processing systems has become increasingly complex, and the hardware (HW).

Since firmware (FW) and software (SW) are interrelated to perform system functions, failures are wide-ranging, making it even more difficult to capture the necessary and sufficient data once a failure occurs. There is also the problem that it is becoming more common.

In view of the above-mentioned points, an object of the present invention is to store historical information in a storage unit with a limited capacity, in which only a portion of the historical information of the processing operations of an information processing system necessary for investigating a failure or the like is stored. The goal is to provide equipment.

[Means to solve the problem]

The history information storage device of the present invention performs a history information storage operation for storing history information of processing operations of an information processing system, and the history information storage device performs the history information storage operation by specifying an instruction address and the number of instruction steps. a first register that holds an instruction address designated by the startup means; and a first comparison that sequentially compares the address of the instruction performing the processing operation with the contents of the first register. an instruction at/res comparison means comprising a circuit and an indicator for holding an indication when the first comparison circuit detects a match; and a second register for holding the number of instruction steps specified by the starting means. a counter that decrements the contents of the second register by one each time one instruction is executed when the indicator holds a match determined by the first comparison circuit; instruction step number comparison means comprising a second comparison circuit for comparison; stop means for stopping the history information storage operation when the second comparison circuit detects a match with zero; and the history information storage. and reading means for reading history information stored in the device, and the starting means and the reading means are executed as software instructions.

[Effect]

In the history information storage device of the present invention, the activation means specifies an instruction address and the number of instruction steps to start a history information storage operation, and the instruction address comparison means stores the first register that holds the instruction address specified by the activation means. and a first comparison circuit that sequentially compares the address of the instruction that is processing the instruction with the contents of the first register, and an indicator that holds that fact when the first comparison circuit detects a match. The step number comparing means compares the contents of the second register with the second register holding the number of instruction steps specified by the starting means each time one instruction is executed when the indicator holds a match determined by the first comparing circuit. 1
It consists of a counter that decrements the contents of the second register and a second comparator circuit that sequentially compares the contents of the second register with zero.
When the comparison circuit detects a match with zero, the history information storage operation is stopped, the reading means reads out the history information stored in the history information storage device, and the starting means and the reading means are executed as software instructions. It is characterized by

(Example〕 Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the history information storage device of the present invention.
Together with the command control section 2 and the diagnosis control section 3, it forms part of an information processing system (the entire information processing system is not shown).

The history information storage device 1 includes a storage unit 4 that stores history information, an address register 5 that specifies the address of the storage unit 4, an address counter 6 that updates the contents of the address register 5, and activates a history information storage operation. A comparison address register 14 that holds an instruction address specified by a startup instruction (TRACER5TART instruction described later), an instruction address comparison circuit 15 that compares the contents of the comparison address register 14 with the instruction address of the instruction being executed, and history information. A remaining instruction step number register 16 that holds the number of instruction steps specified by a startup instruction that starts a storage operation and its countdown value, and a counter 1 that updates (decreases by 1) the contents of the remaining instruction step number register 16.
7, the contents of the remaining instruction step number register 16 and “O”
and a plurality of flip-flops 7 to 13 that set various operating conditions for the dawn history information storage device 1 according to various instruction signals from the instruction control section 2 and the diagnostic control section 3. , a plurality of AND gates 21 to 28, and a plurality of OR gates 31 to 28.
It consists of 35.

Anime game) 21 causes the flip-flop 7 to hold stop condition data 101 (hereinafter, "stop" refers to the stop of the history information storage operation) in accordance with the stop condition setting signal 104.

The AND gate 24 outputs a logical product of the signal held in the flip-flop 7 and the stop-condition report signal 106 from the instruction control unit 2 to the OR gate 31 .

Similarly, flip-flop 8 and AND gates 22 and 25 send a signal made up of stop condition data 102 and stop condition report signal 107 to OR gate 31; sends a signal composed of the stop condition data 103 and the stop condition report signal 108 to the OR gate 31.

Here, the stop condition data 101 to 103 and the stop condition setting signal 104 are sent out from the diagnostic control section 3, and the stop condition report signals 106 to 108 are sent out from the command control section 2. Note that the flip-flops 7 to 9 are connected to the diagnostic control unit 3.
It is reset by the stop condition initialization signal 105 sent by.

In addition to the stop condition data 101 to 103 supplied via the AND gates 24 to 26, the OR gate 31 also receives a stop signal 109 from firmware (hereinafter abbreviated as FW) included in the command control unit 2. Stop signal 110
Send out.

The flip-flop 10 stores the history write data 51 sent from the instruction control unit 2 in a set state of “1” to the storage unit 4.
It has a function of instructing writing to the memory, and is set to an initial state of ``1'' by a storage start signal 111 sent by the diagnostic control unit 3, and reset to 0'' by a stop signal 110.

The flip-flop 11 stores history write data 51 sent from the instruction control unit 2 in a set state of “1” to the storage unit 4.
The storage start signal 111 sent by the diagnostic control unit 3 or the start signal 117 by the FW sent by the instruction control unit 2 (TRACER5T described later)
TRAC in the instruction control unit 2 based on the execution of the ART instruction.
(Output by the FW that executes the ER5TART instruction)
is reset to the initial state "0" via the OR gate 33, and set to "1" by the storage operation completion signal 123 which is the output of the AND gate 28.

In the AND gate 27, the flip-flop 10 is “1”,
The write signal 112 is sent out when each of the flip-flops 11 holds 10'' (ie, indicates that a history information storage operation should be performed).

The AND gate 28 is the output of the flip-flop 13.
21 and a coincidence signal 122 output from the instruction step number comparison circuit 18, and outputs a storage operation completion signal 123.

The OR gate 34 inputs the write signal 112 and the continuation signal 113 sent out by the diagnostic control unit 3, and sends out an address register update signal 114.

Address register 5 receives address register update signal 11
4, the count data 54 is input, and the address data 53 is sent out.

Address counter 6 inputs address data 53,
The count data 54 is sent out in accordance with the counter switching signal 115 sent out from the diagnostic control section 3.

This counter switching signal 115 causes the address counter to either send out count data 54 obtained by adding +1 to address data 53, or ignore address data 53 and send out count data 54 of all "O"s. Let 6 choose.

The storage section 4 writes the history write data 51 sent from the instruction control section 2 to the address indicated by the address data 53 in accordance with the write signal 112 as history information. The history information, which is the content thereof, is read out as history read data 52 and sent to the diagnosis and omission control section 3.

The flip-flop 12 receives a logout signal 118 sent from the instruction control unit 2 via the OR gate 32 (outputted by a FW that executes a TRACERLOGOUT instruction in the instruction control unit 2 based on execution of a TRACERLOGOUT instruction, which will be described later) or a stop signal. Input one or both of the signals 110 and logout instruction signal 119
is sent to the diagnostic control unit 3.

The frisible flop 13 receives a storage start signal 111 , a count stop signal 116 outputted from the instruction control unit 2 by the FW that executes the startup instruction to start the history information storage operation, or a storage operation completion signal outputted from the AND gate 28 . 0” via the OR gate 35 by the signal 123.
is reset to "l" by the match signal 120 that is output when the instruction address comparison circuit 15 detects a match.
is set to

The comparison address register 14 is set with the instruction address specified by the activation instruction from the instruction control unit 2 via the data bus 55.

The instruction address comparison circuit 15 compares the comparison address register 1
Compare the comparison address output from 4 via the data bus 56 with the instruction counter data (instruction address being executed) sent from the instruction control unit 2 via the data bus 57, and when the comparison address is failed, a match signal 120 is generated. Output.

The remaining instruction step number register 16 is set with the number of instruction steps specified by the activation instruction from the instruction control unit 2 via the data bus 55, and is subtracted by -1 by the counter 17.

Counter 17 is 1 at the cent of frisib flop 13.
The number of remaining instruction steps output from the remaining instruction step number register 16 via the data bus 58 each time an instruction is executed is one! The remaining instruction step number register 16 is re-sent via the data bus 59.

The instruction step number comparison circuit 18 compares the remaining instruction step number output from the remaining instruction step number register 16 via the data bus 5B with °0'', and generates a match signal 1 when they match.
Outputs 22.

FIG. 2 (al is a flowchart showing an example of a program executed in an information processing system. In the same figure,
Processing 6L A loop consisting of 62 and 64 indicates normal processing operations as an information processing system, and in particular, in the instruction 1N5T□, the normality of the processing result after the instruction 1N5Ta&- is checked. Then, processing 62
If an incorrect processing result due to a failure or the like is detected while executing the instruction IN5T1, control is immediately transferred from that step to process 63 for post-processing the incorrect processing.

FIG. 2(b) shows the instruction l using the history information storage device 1.
This is a flowchart of a program that has been modified from the program shown in FIG.
A loop consisting of 3 and 76 indicates normal processing operation as an information processing system.

The process 72 that includes the TRACER5TART command is a mechanism for storing necessary portions of the history information of such processing operations. Furthermore, a process 75 that includes a TRACERLOGOUT command is a mechanism for logging out detailed information on the illegal process from the process 74 that performs post-processing of the illegal process.

Next, the operation of the history information storage device 1 of this embodiment configured as described above will be explained together with the processing of the program shown in FIG. 2 (bl).

In the information processing system, when the BRANCH instruction is executed in the program process 71 shown in FIG.
5F from the instruction control unit 2 by the execution FW of the TART instruction.
A count stop signal 116 by W is output, the flip-flop 13 is reset, and updating of the value of the remaining instruction step number register 16 by the counter 17 is stopped.

Next, the instruction address and instruction step number specified by the TRACER5TART instruction are output from the instruction control unit 2 via the data bus 55, and set in the comparison address register 14 and the remaining instruction step number register 16, respectively. Subsequently, the instruction control unit 2 outputs a start signal 117 by the FW, the flip-flop 11 is reset via the OR gate 33, and the write signal 112 is output from the AND gate 27. As a result, the writing operation of the history write data 51 sent from the command control unit 2 to the storage unit 4 is started. That is, the history information storage operation of the history information storage device 1 is activated.

After the TRACER5TART instruction is executed, control is returned to the process 71 by executing the BRANCH instruction in the process 72.

Every time the information processing system performs a processing operation of the program instruction shown in FIG. The value of the register 5 is updated, and the history write data 51 is sequentially written into the next address word of the storage section 4.

In this way, the history information storage device 1 performs T in process 72.
After the RACER5TART command (instruction lN5TAI
-! The history information of the processing operations (after) continues to be stored.

Comparison address register 14 in instruction address comparison circuit 15
When a match is detected between the instruction address output from the instruction control unit 2 via the data bus 56 and the instruction counter data (instruction address being executed) output from the instruction control unit 2 via the data bus 57, the instruction address comparison circuit 15 is match signal 1
20 and sets the flip-flop 13 to "1".As a result, the output signal 12 of the flip-flop 13
1, the counter 17 starts operating and the updating of the remaining instruction step number register 16 is started. That is, the number of remaining instruction steps outputted from the remaining instruction step number register 16 via the data bus 58 is decremented by 1 by the counter 17 for each execution of one instruction, and then output again via the data bus 59 to the remaining instruction step number register 16. is set to

Thereafter, one instruction is executed until the instruction step number comparison circuit 18 detects that the remaining instruction step number outputted from the remaining instruction step number register 16 via the data bus 58 becomes "0". The value of the remaining instruction step number register 16 is subtracted each time.

When the instruction step number comparison circuit 18 detects that the remaining instruction step number output from the remaining instruction step number register 16 via the data bus 58 is "0", a match signal 122 is output, and the AND gate A storage operation completion signal 123 is output from 28. As a result, the flip-flop 13 is reset to aO'', the operation of the counter 17 is stopped, and the remaining instruction step number register 16 is no longer updated, and the flip-flop 11 is set to "■". As a result, the write signal 112 is no longer output from the AND gate 27, and the writing operation of the history write data 51 to the storage unit 4 is stopped.That is, the history information storage operation of the history information storage device 1 is stopped.

As described above, after executing the instruction at the instruction address specified by the TRACER5TART instruction, the same <TRA
It is possible to cause the storage unit 4 to store history information during execution of instructions for the number of instruction steps specified by the CER5TART command, and to stop the history information storage operation.

After this, the history information storage device 1 again stores TRACER5T.
It is in a standby state until the ART command is executed or an incorrect processing result is detected and the TRACERLOGOUT command is executed.

If the information processing system continues the processing operation of the program shown in FIG. 2 (bl) and detects an incorrect processing result due to a failure while executing the instruction 1N5Taj in process 73, control immediately shifts from that step to process 74. .Processing 74
In the post-processing of the above-mentioned illegal process, control is passed to process 75 by executing the BRANCH instruction. In process 75, T
A RACERLOGOUT instruction is executed.

When the TRACERLOGOUT instruction is executed, the TRA
The instruction control unit 2 is activated by the execution FW of the CERLOGOUT instruction.
A logout signal 118 is output from the OR gate 32.
A logout instruction signal 119 is outputted via the flip-flop 12 and inputted to the diagnostic control section 3. Therefore, the diagnostic control section 3 outputs a read signal 113, and the history information is sequentially read out from the storage section 4 as history read data 52 to the diagnosis control section 3.

Thereafter, in process 75, control is returned to process 74 by executing the BRANCH instruction.

In this way, in the history information storage device l of this embodiment, by specifying the part of the program of the information processing system in which the history information of the processing operation is to be stored, the history information of the designated part is stored. The history information can be stored, and the stored history information can be read out.

In addition, in the above embodiment, the stop condition data 101 to 103
Although the explanation has been given by illustrating up to three, the number may be four or more or two or less. That is, the present invention is not limited by the number of stop condition data.

〔Effect of the invention〕

As explained above, the present invention enables a portion of the processing operations of an information processing system that stores history information to be instructed by software instructions in the program, thereby detecting the occurrence point of unauthorized processing. It is possible to directly instruct the start and stop of storing historical information even if the points are far apart in time or within a processing loop. Since sufficient historical information can be obtained, it is possible to easily and efficiently investigate failures.

In addition, as detailed history information can be recorded as described above, it is possible to obtain the necessary data while narrowing down the target when investigating a problem.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the history information storage device of the present invention, and FIG. 2 is a flowchart showing an example of a program for explaining the operation of the history information storage device of this embodiment. In the figure, 1...history information storage device, 2...command control unit, 3...diagnosis control unit, 4...storage unit, 5...・Address register, 6...Address counter, 7-13...Flip-flop, 14...Comparison address register, 15...
Instruction address comparison circuit, 16... Remaining instruction step number register, 17... Counter, 18... Instruction step number comparison circuit, 21-28.
...AND gate, 31-35...OR gate, 51...History write data, 52...History read data, 53...Address data, 54...Count data , 55-59...Data bus, 101-103 - Stop condition data, 104...
... Stop condition setting signal, 105 ... Stop condition initialization signal, 106 to 108 - Stop condition report signal, 10
9...Stop signal by FW, 110...Stop signal, 111...Storage start signal, 112...Write signal, 113...Read signal, 114...Address register Update signal, 115
...Counter switching signal, 116 ...F
Count stop signal by W, 117...Start signal by FW, 11B...Logout signal, 119...Logout instruction signal, 120, 1
22 - Match signal, 123 . . . Storage operation completion signal.

Claims (1)

[Scope of Claims] In a history information storage device that performs a history information storage operation for storing history information of processing operations of an information processing system, the history information storage operation is started by specifying an instruction address and the number of instruction steps. a first register for holding an instruction address specified by the starting means; and a first register for holding an instruction address designated by the starting means;
an instruction address comparison means comprising a first comparison circuit that sequentially compares the content of the register with the contents of the register; and an indicator that holds the fact when the first comparison circuit detects a match;
When a second register holding the number of instruction steps specified by the starting means and the indicator match each other by the first comparison circuit, the contents of the second register are read every time one instruction is executed. instruction step number comparison means comprising a counter that is decremented by 1 and a second comparison circuit that sequentially compares the contents of the second register with zero; and the second comparison circuit detects a match with zero. and a reading means for reading out the history information stored in the history information storage device, wherein the starting means and the reading means are executed as software instructions. A history information storage device characterized by: