JPH01194055A - Parallel computer - Google Patents

Abstract

PURPOSE:To reduce overhead generated at the time of transferring data between processor elements by inspecting the contents of a tag added to a word and repeating the inspection of the word until the tag express validity. CONSTITUTION:When processor elements 1-1-1-n write data in a word of a local memory 6 of another processor element, the contents of a tag added to the word are processed by a validating means so as to express 'data are valid'. On the other hand, the processor element for reading out the data waits until the contents of the tag added to the word express 'data are valid' by a tag access means prior to reading of the word and reads out the data stored in the word so that the contents of the tag express 'data are invalid' by an invalidating means 33. Consequently, overhead generated at the time of transferring data between the processors can be reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for configuring a parallel computer.

[Conventional technology]

Conventionally, in a parallel computer that has local memory, is composed of multiple processor elements, and can access the local memory of other processor elements, one processor element receives and passes data via the local memory of another processor element. Sometimes, in order to guarantee the order in which data is referenced, the passing processor element writes the data to local memory and then interrupts the processor element reading the data. Related devices of this type include, for example, I.E.E., 19
Proceedings of the 85th International Conference on Parallel Processing, pp. 782-788 (
IEEE, PROCEEDINGS OF THE
1985 INTERNATIONAL CONFER
ENCE ON PARALLEL PROCESS
ING pp, 782-788).

On the other hand, in a parallel computer consisting of multiple processor elements connected by a shared memory, when one processor element receives or passes data to another processor element via the shared memory, a tag is set in the colloquy of the shared memory. There is a device that uses this tag to indicate whether the content of the word has been written (data is valid) or not written (data is invalid). For example, real-time
Signal Processing IV, Vol, 298(1)
August 981) pages 241 to 248 (REAL-
TI ME SI GNAL PROCESSIN
G IV, Vol. 298 (Aug 1981),
This is the device discussed in pp. 241-248.

[Problem to be solved by the invention]

The former of the above conventional technologies uses local memory to execute calculations, so even if the number of processor elements that make up a parallel computer increases, the ability to supply data from local memory to arithmetic units is limited. High performance can be obtained because the number increases in proportion to the number of processor elements, but when receiving and passing data from one processor element to another through local memory, interrupt processing is involved, and the The overhead may significantly reduce the performance of parallel computers.

On the other hand, in the latter of the above conventional technologies, although there is no interrupt processing overhead, multiple processor elements are connected using shared memory, so it is necessary to install many processor elements in order to improve the performance of a parallel computer. Therefore, it is extremely difficult to realize a high-performance parallel computer.

An object of the present invention is to reduce the overhead that occurs when receiving and passing data between processor elements in a parallel computer that is composed of a plurality of processor elements each having a local memory and in which data can be written to the local memory from other processor elements. It is in.

[Means to solve the problem]

The above purpose is to consist of a plurality of processor elements that have local memories and can operate independently, and a network that connects them, and that each of the plurality of processor elements writes data into the local memory of other processor elements. In a parallel computer that is capable of an enabling means for setting the content of a tag attached to a word to indicate "data valid" when writing a word; a tag access means for continuing checking until the content of the tag indicates "data is valid"; This is achieved by providing invalidation means that sets the content of the tag attached to the word to indicate "data is invalid" when the word is read from the processor element holding the word.

Further embodiments may also achieve the above objectives. The above purpose is to configure a receiving memory by providing a receiving memory in each processor element that can be written to by any processor element in a parallel computer consisting of a plurality of processor elements that have local memory and can operate independently. This can also be achieved by providing a tag for the word, giving this tag the same meaning as the tag in the embodiment described above, and providing the receiving memory with the enabling means, the tag access means, and the disabling means in the embodiment described above. Ru.

[Effect]

In a first embodiment, when a processor element writes data to a word in the local memory of another processor element, in a second embodiment, a processor element writes data to a word in the receive memory of another processor element. When writing data, the content of the tag attached to the word by the validation means is made to indicate "data is valid." On the other hand, the processor element that reads this data waits until the content of the tag attached to the word by the tag access means indicates "data is valid" before reading the word, and then reads the data stored in the word. , the content of the tag is made to represent "data is invalid" by the above-mentioned invalidation means.

By doing as described above, data transfer between processor elements can be performed correctly and efficiently.

〔Example〕

The present invention will be explained in detail below.

<First Example> The first example will be described with reference to the drawings. First, an overview of the parallel computer according to this embodiment will be explained with reference to FIG. In FIG. 1, 1-1 to 1-n are n independently operable processor elements.

A network 2 receives a data transmission request issued from any processor element 1-1 to 1-n and transfers the data to a specified processor element.

Next, the configuration of processor elements 1-1 to 1-n will be explained. Processor element 1-1 to 1-n
have the same configuration, but in Figure 1, 1 is used for simplicity.
Only the inside of -1 is shown. Processor element 1
-1 is composed of a processor 3, a receiver 4, a transmitter 5, and a local memory 6. Details of the processor 3 are shown in FIG. In FIG. 2, 30 is an instruction fetch circuit, 32 is an ALU, 33 is an invalidation circuit, 34 is a general-purpose register group, and 35 is a program counter.

Reference numeral 36 denotes an instruction register, which is divided into a field 36-1 for storing an instruction code and a field 36-2, 36-3, and 36-4 for storing operands. Reference numeral 37 denotes an instruction decoding control, which decodes instructions and controls their execution. 38 is a memory access circuit, which is used when executing a RECEIVE instruction, which will be described later. Also, 3
1 is an OR circuit, and 300 is an AND circuit. The processor 3 is a so-called Neumann type computer, and for this embodiment, it is designed to be able to execute two new instructions in addition to the normal von Neumann type computer instruction set (memory read, memory write, arithmetic instructions, etc.). There is. The new order will be discussed later.

Addresses are assigned to the guest words in the local memory 6 in FIG. 1 in units of words. Furthermore, in addition to the data part that stores data, the customary language has a tag part that stores one-bit tags. How to use it will be explained later. The data section of the local memory 6 stores programs executed by the processor 3 and data used by the programs. Local memory 6 has a first port, line L6, which uses line L3 as address input, line L4 as data input and data write request signal, and line L5 as tag input and tag write request signal.
to address input, line L7 to tag input and tag write request signal, line L8 to address input and tag and data read request signal, line L9 to tag output, line LIO to data input/output. There is a third port that uses the line L12 as a data write request signal, a fourth port that uses line L12 as an address input and data read request signal, and line L13 as a data output signal. When two or more requests from the first port, second port, and third port arrive at the same time, the local memory 6 arbitrates appropriately and responds to the requests.

The transmitter 5 is a device used to write data from the processor element 1-1 to the local memories of the other processor elements 1-1 to l-n, and has a register 50 therein. Register 50 has field 5
It is divided into 0-1.50-2.50-3, each storing a destination, address, and data.

The receiver 4 includes processor elements 1-1 to 1-
n is a device used when writing data to the local memory 6 of the processor element 11, and has a register 40 therein. Register 40 has field 40
-1, 40-2, each of which stores addresses and data. 41 is a write control, and when data is written into the register 40 from line L1, a tag value of 1 and a tag write request signal are output to line L5.

FIG. 1 shows the operation of the processor element 1-1.

This will be explained using FIG. First, the instruction fetch circuit 30 in the processor 3 connects the program counter 3 to the line L12.
5 and the data read request signal to the local memory 6.
output to the fourth port of.

Then, the local memory 6 is read out and its contents are shown on line L.
13, this is set in the instruction register 36. The instruction decoding control 37 decodes the value of the instruction code stored in the field 36-1 of the instruction set in the instruction register 36.

A signal for realizing the operation specified by the instruction is distributed inside the processor 3, and the ALU 32. General-purpose register group 3
4 etc. When the operation specified by the instruction is completed, the instruction decoding control 37 updates the value of the program counter 35 from line L302 and repeats the above operation.

The operation of network 2 will be explained. Network 2 is
When a value is set in the register 50 in the transmitter 5, the processor element 1 indicated by the field 50-1
register 400 field 40-1.40-2 in receiver 4 in
The values of fields 50-2 and 50-3 are transferred to each of the fields 50-2 and 50-3.

Next, I will explain the newly established commands. First, 5END
Explain the command. The 5END instruction is an instruction for writing data possessed by the processor element that executed this instruction into a local memory in another processor element. FIG. 4 shows the format of the 5END instruction. The 5END instruction has three operands.

1, destination 2, address 3, data operands are R1 and R of the instruction format, respectively.
2, stored in the general-purpose register specified by the R3 field. This instruction means writing data specified by the third operand to the address specified by the second operand in the local memory of the processor element specified by the first operand. When executing this instruction, the parallel computer of this embodiment operates as follows.

First, the instruction decoding control 37 of the processor 3 inputs the values (register numbers) stored in the fields 36-2, 36-3, and 36-4 of the instruction register 36 to the lines L305 and 36-4, respectively.
．． Line L306. It is transmitted to the general-purpose register group 34 via line L307. As a result, 1st degree, 2nd degree. The third operand is line L3
15, the instruction decoding control 37 is generated and output to the line Lll together with the write request signal transmitted from the line L309, and the fields 50-1 and 5 of the register 50 are respectively output.
Set to 0-2.50-3. This completes the 5END command, but the following operations are subsequently performed.

When a value is set in the register 50, the register 40-1, 40-2 of the processor element specified by the field 50-1 is
The contents of registers 50-2 and 50-3 are set respectively. Then, the receiver 4 of the processor element to which the data has been set transfers the contents of 40-2 from the first port of the local memory 6 to the data field of the word specified by 40-1, and sets the value 1 to the tag field of that word. (a value indicating that the content of the word is valid) is written.

Next, the RECEIVE command, which is a newly installed command, will be explained. The RECEIVE instruction is an instruction to read data from the local memory of the processor element that executed this instruction. FIG. 3 shows the format of the RECE IVE command.

The RECE IVE instruction has two operands.

(2) Address 2, Register Number Each operand is stored in the general-purpose register and R2 field specified by the R1 field of the instruction format, respectively. This instruction reads valid data from the local memory address specified by the first operand and stores the data in the general-purpose register specified by the second operand. When executing this instruction, the parallel computer of this embodiment operates as follows.

First, the instruction decoding control 37 of the processor 3 outputs the contents (register numbers) of fields 36-2 and 36-3 of the instruction register 36 to the general-purpose register group 34 on lines L305 and L306, respectively, and
A signal indicating execution of the command is output to the line L303, and the memory access circuit 38 is activated. As a result, along with the first operand as a memory address, a memory read request signal generated by the memory access circuit 38 and passed through the line L301 and the OR circuit 31 is transmitted to the third port of the local memory 6 on the line L8.

Then, the local memory 6 stores the tag value on the line L9 and the tag value on the line LI.
Output data to O. The data output to line LIO is set in the general-purpose register specified by the second operand. The tag value output on line L9 is input to the memory access circuit 38, and when this value is O, the memory access circuit 38 again generates a memory read request signal on line L301 and repeats the above memory access. Line L
When the value output to 9 is 1, the output of the AND circuit 300 in the invalidation circuit 33 becomes 1. As a result, line L6
Using the first operand output to the line L7 as an address, the value O and the output of the AND circuit 300 are output to the second port of the local memory 6 as tag write data and a write request, respectively. , the tag of the word specified by the first operand becomes O (a value indicating that the data is invalid). When the line L9 is 1, the memory access circuit 38 applies a signal to the program counter 35 from the line L302 in parallel to this, and updates the contents of the program counter. This completes the RECE IVE command.

Next, the operation of the parallel computer according to this embodiment will be explained.

Each processor element constituting the parallel computer according to this embodiment operates in the same way as a normal computer when it is not necessary to receive or pass data to or from other processor elements. When data needs to be passed to and from other processor elements, the word used for the data passing (this word is specified by the programmer or compiler in advance) is stored in the local memory of the receiving processor element. Program the processor element on the side that sends data to write data using the 5END instruction mentioned above, and the processor element on the side that receives data to read data using the RECE IVE instruction. . By doing so, the processor element on the data receiving side will not read the data before the data transmitting processor element writes the data, and the reference order of the data is guaranteed. The above is the first embodiment of the present invention.

In the above, when the RECE IVE instruction is executed and the tag value is 0, the memory access circuit repeatedly accesses the memory and checks the tag value. When executing the command, the tag value is read only once to complete instruction execution, and this value is set in a flag register or condition code register that reflects the execution result of this instruction.
E If the tag is set to 1 due to a conditional branch instruction following the IVE instruction, etc.
It may also be implemented by repeatedly executing the RECE IVE command until the RECE IVE command is reached.

Second Example> A second example will be described with reference to the drawings. This embodiment is a modification of the first embodiment. The configuration of the parallel computer of this embodiment will be explained with reference to FIG. Components labeled with the same reference numerals in FIG. 5 and FIG. 1 are the same.

In FIG. 5, 8 is a receiving memory, and like the local memory 6 in FIG. 1, addresses are assigned in units of words. In addition to the data part that stores data, the guest word also has one part.
There is a tag section that stores bit tags. The receiving memory 8 has a first port that uses line L3 as an address input, line L4 as a data input and data write request signal, line L5 as a tag input and tag write request signal, line L6 as an address input, and line L6 as an address input. Second port with L7 as tag input and tag write request signal, line L8 as address input and tag and data read request signal, line L9 as tag output, line L1
There is a third port that makes 0 the data output signal. When two or more requests from each boat arrive at the same time, the receiving memory 8 arbitrates appropriately and responds to the requests.

Reference numeral 9 denotes a local memory, to which addresses are assigned in units of words. A guest word has a data part that stores data. The local memory 9 has a first port, line L1, which uses line L15 as an address input and data read request signal, and line L14 as a data input/output and data write request signal.
2 as address input and data read request signal, line L1
There is a second port that makes 3 a data output. When two or more inputs from each port arrive at the same time, the local memory 9 arbitrates appropriately and responds to the requests.

In contrast to the local memory 6 in the receiver 4, the operation in FIG. 5 is similar to that of the first embodiment except that writing is performed in the reception memory 8.

The transmitter 5 operates in the same way as the transmitter 5 of the first embodiment.

FIG. 5 shows the operation of the processor element 1-1.

This will be explained using FIG. First, the instruction fetch circuit 30 in the processor 7 inputs the program counter 35 from the line LL2.
and the data read request signal are output to the second port of the local memory 9. Then, the local memory 9 is read out and its contents are output to the line L13, which is then set in the instruction register 36. The instruction decoding control 37 decodes the value of the instruction code stored in the field 36-1 of the instruction set in the instruction register 36, and sends a signal to the processor 7 for implementing the operation specified by the instruction. distributed to ALU32. The general-purpose register group 34 and the like are operated. When the action specified by the command is completed,
The instruction decoding control 37 updates the value of the program counter 35 from the ML 302 and repeats the above operation.

The operation of network 2 is the same as in the first embodiment.

Next, I will explain the newly established commands. First, 5END
Explain the command. The 5END instruction is the 5EN of the first embodiment.
It has the same format as the D instruction. The meanings of the operands are also the same. When executing this instruction, the parallel computer of this embodiment operates as follows.

First, the instruction decoding control 37 of the processor 7 inputs the values (register numbers) stored in the fields 36-2, 36-3, and 36-4 of the instruction register 36 to the lines L305 and 36-4, respectively.
．． Line L306. It is transmitted to the general-purpose register group 34 via line L307. As a result, 1st degree, 2nd degree. The third operand is line L3
15, an instruction decoding control 37 is generated and output on line Lll together with a write request signal transmitted from line L309, respectively, to fields 5o-i of register 50.

Set to 5o-2, 50-3. This completes the 5END command, but the following operations are subsequently performed.

When a value is set in the register 50, the register 40-1.
The contents of registers 50-2 and 50-3 are respectively sent to the registers 50-2 and 50-3. Then, the receiver 4 of the processor element to which the data has been set receives the data from the first port of the reception memory 8.
The contents of 40-2 are written in the data section of the word specified by -1, and the value 1 (a value indicating that the contents of the word are valid) is written in the tag section of that word.

Next, the RECEIVE command, which is a newly installed command, will be explained. The RECEIVE instruction is RECEIV in the first embodiment.
It has the same format as the E command.

The same applies to operands. When executing this instruction, the parallel computer of this embodiment operates as follows.

First, the instruction decoding control 37 of the processor 7 reads the contents (register numbers) of fields 36-2 and 36-3 of the instruction register 36 through a line L305° and outputs them to the general-purpose register group 34 at 306, and RECEIVE
A signal indicating execution of the command is output to the line L303, and the memory access circuit 38 is activated. As a result, along with the first operand as a memory address, a memory read request signal generated by the memory access circuit 38 and passed through the line L301 is outputted to the third port of the receiving memory 8 from the line L8. Then, the reception memory 8 outputs the tag value to the line L9 and the data to the line LIO. The data output to line LIO is set in the general-purpose register specified by the second operand.

The tag value output to line L9 is sent to memory access circuit 38.
However, when this value is O, the memory access circuit 38 again generates a memory read request signal on the line L301, and repeats the above memory access. When the value output to the line L9 is 1, the AND in the invalidation circuit 33
The output of circuit 300 becomes 1. As a result, the first operand output on the line L6 is used as an address, and the value 0 and the output of the AND circuit 300 are output on the line L7 as tag write data and a write request signal, respectively, to the second port of the receiving memory 8. Therefore, the tag of the word specified by the first operand is 0 (a value indicating that the data is invalid).

When the line L9 is 1, the memory access circuit 38 applies a signal to the program counter 35 from the line L302 in parallel to this, and updates the contents of the program counter 35. This completes the RECETVE command.

The parallel computer of this embodiment operates in the same way as the parallel computer of the first embodiment, except that the storage location used for receiving and passing data between processor elements is the reception memory 8. The same effect as the first embodiment can be obtained.

Furthermore, the following effects are unique to this embodiment.

In this embodiment, the memory for receiving and passing data (reception memory 8) is separated from the memory for storing programs and data (local memory 9), so from the standpoint of creating a program, the memory shown in FIG. As shown above, there appear to be two memory spaces: a receiving memory space 80 and a local memory space 90. Therefore, when combining and editing programs to be executed on this parallel computer and resolving unresolved external references, 1) resolving unresolved external references between the receiving memories of each processor element, and 2) resolving the unresolved external references within each processor element. Both resolutions of unresolved external references can be performed independently.

Then, if you create a program as a subroutine that performs calculations while passing data between processor elements, and resolve the unresolved external references in 1), you can reuse this subroutine in another program. When incorporating, all that is required is to resolve unresolved external references in 2) as before. In other words, programs can be easily reused.

<Third Example> A third example will be described with reference to the drawings. This embodiment is a modification of the first embodiment. The configuration of the parallel computer of this embodiment will be explained with reference to FIG. Components labeled with the same reference numerals in FIG. 9 and FIG. 1 are the same.

In this embodiment, the effects obtained in the second embodiment are achieved by making some changes to the first embodiment. i-th
The unique effect of this embodiment is due to the fact that the memory space 80 created by the reception memory and the memory space 90 created by the local memory are separated, as shown in FIG. Dividing the space can also be achieved by dividing the memory entity as in the second embodiment, but in this embodiment it is achieved by a different method. That is, by mapping the reception memory space 81 into the local memory space 91 as shown in FIG. 8, architecturally separate spaces are realized on the same hardware memory. The mapping method is as shown in FIG. 8, in which a fixed value "x" is added to the address in the reception memory space to make it an address in the local memory.

In FIG. 9, 100 is address translation, the details of which are shown in FIG. 11. In FIG. 11, 101 is a register, which stores the above-mentioned constant value "x".

The value may be set in the register 101 by, for example, the processor 11 in FIG. 9 (lines necessary for this are omitted from the figure).

In FIG. 11, 102 is an adder. Address conversion 100 is a constant value +1 x++ to the contents of register 40-1.
The added value is output to line L3.

In FIG. 9, 110 is address translation, the details of which are shown in FIG. 12. In FIG. 12, 113 is a register, which stores the above-mentioned constant value "x".

Values can be set in register 113 in the same manner as in register 101.

114 is an adder. Address translation 110 is performed on line L3
A value obtained by adding a constant value "x" to the value input from 13 is output to line L6.

FIG. 10 shows the configuration of the processor 11.

In FIG. 11 and FIG. 2, components denoted by the same reference numerals are the same. In FIG. 11, 110 is address translation, which has already been explained.

111 is an instruction decoding control. 112 is a selector, which is controlled by line L312.

FIG. 9 shows the operation of the processor element 1-1.

This will be explained using FIG. The operation of the processor 11 is as follows:
The operation is almost the same as that of the processor 3 of the first embodiment, except for the commands (RECEIVE commands) mentioned below.
The difference is that the instruction decoding control 111 always transmits the line L313 to the line L314.

The operation of network 2 is the same as in the first embodiment.

Next, I will explain the newly established commands. First, 5END
Explain the command. The 5END instruction is the 5EN of the first embodiment.
It has the same format as the D instruction. The meanings of the operands are also the same. When executing this instruction, the parallel computer of this embodiment operates as follows.

The operation of the processor element that executed the 5END instruction is the same as that of the processor element of the first embodiment. The processor element whose data is set in the register 40 via the network operates as follows. The receiver 10 of this processor element converts the contents of 40-1 from the first port of the local memory 6 into the data portion of the word 40-2 specified by the value obtained by converting the contents of 40-1 by the address conversion 100. The content is set to the value 1 in the tag section of the word.
Write.

Next, we will explain the RECE IVE command, which is a newly created command.
It has the same format as the IVE instruction.

The same applies to operands. When executing this instruction, the parallel computer of this embodiment operates as follows.

First, the instruction decoding control 37 of the processor 11 transfers the contents of fields 36-2 and 36-3 of the instruction register 36 to the general-purpose register group 34 on lines L305 and L306, respectively.
At the same time, a signal indicating execution of the RECEIVE instruction is output to the line L303, and the memory access circuit 38 is activated. As a result, the first operand as a memory address is on line L313. Address conversion 110
, are output to line L314 via selector 112.

In addition to this, the memory access circuit 38 occurs, and the line L301
．． Together with the memory read request signal via the OR circuit 31, the signal is transmitted to the third port of the local memory 6 as a line L8. Then, the local memory 6 outputs the tag value to the line L9 and the data to the line LIO. The data output to line L10 is set in the general-purpose register specified by the second operand. The tag value output to line L9 is input to the memory access circuit 38, but if this value is 0
At this time, the memory access circuit 38 again generates a memory read request signal on the line L301 and repeats the above memory access. When the value output to line L9 is 1, the output of AND circuit 300 in invalidation circuit 33 becomes 1.

Thereby, the first operand is set to line L313. Via the address conversion 110, the value output to the line L6 is used as an address, and the value 0 and the output of the AND circuit 300 are combined to the line L7 and sent to the second port of the local memory 6 as tag write data and a write request signal. Since it is to be output, the tag of the word in the reception memory space specified by the first operand becomes 0. When the line L9 is 1, the memory access circuit 38 applies a signal to the program counter 35 from the line L302 in parallel to this, and updates the contents of the program counter 35. This completes the RECEIVE command.

In the above, the address conversion accompanying the execution of the 5END instruction is executed by the address conversion 100 in the receiver 10 in FIG. It should be executed before the value is written. Therefore, for example, as shown in FIG. 13, an address translation 120 may be placed in the transmitter 12 and configured to perform the same translation as the address translation 110 here.

In addition, in the above mapping method, a constant value "x"'
Although we have explained the method of adding , mapping itself does not need to be limited to this method. It is sufficient that the address of the local memory space is uniquely determined from the address of the reception memory space, and the mapping does not overlap.

In addition, when writing data to the local memory of another processor element using the 5END command in the above, writing to a portion of the local memory space 91 in FIG. 8 other than the portion mapped to the receiving memory space 81 is prohibited. By preventing execution, data local to the processor element can be prevented from being destroyed by other processor elements due to a program error or the like.

For example, if the capacity of the local memory space used as the reception memory space is n words, when executing the 5END instruction, the comparator determines that the address of the reception memory space, which is the second operand of the instruction, is less than address n. For example, if the address is n or more, writing may be inhibited. Alternatively, after executing the address conversion performed in conjunction with the 5END instruction, it may be confirmed that the address obtained by the conversion is greater than or equal to address X and less than address x+n.

According to this embodiment, not only the effects shown in the second embodiment can be obtained, but also the following effects.

That is, in the second embodiment, since the receiving memory 8 and the local memory 9 are separated in terms of hardware, if the capacity of the local memory 9 becomes insufficient even when attempting to perform large-scale calculations, even if the receiving memory 8 Even if there is a margin, this cannot be used to perform calculations. The opposite is also true. However, according to this embodiment, if there is sufficient reception memory space, this portion can be used as a local memory. In other words, if the sum of the capacity of the receiving memory 8 and the capacity of the local memory in the second embodiment is equal to the capacity of the local memory 6 in the present embodiment, the parallel computer of the present embodiment can perform larger-scale calculations. This means that it is possible to do this.

<Fourth Example> This example is a modification of the third example. In the third embodiment, the local memory of the processor element is word-addressed memory.

Since actual computers need to process data such as character data in units of 1 byte, addresses are often assigned in units of bytes (8 bits). On the other hand, in normal numerical data processing, calculations are often performed in units of 4 or 8 bytes. Therefore, if a word is one byte,
If you add a tag to each byte, for example, 8
5END instruction of the third embodiment to guarantee reference order of byte data.

Executing the RECE IVE instruction eight times at a time not only increases the execution time but also increases the amount of hardware that must be prepared to implement the tag. The data can be processed in 1-byte units, and tags are attached to each 8-byte unit, and 5EN is added to the 8-byte m position.
D command.

Enables execution of RECE IVE command.

The mapping method in this embodiment will be explained with reference to FIG.

In FIG. 14, 82 is the reception memory space;
Each byte is assigned an address. 92 is a local memory space, and each byte is assigned an address. Here, the address of the reception memory space is a
, the address of the local memory space corresponding to this is b
When , perform as b=a*8+x. Here, the value X has the same meaning as the constant value 'lX, , in the third embodiment.

The parallel computer of this embodiment has address conversion 1 in FIGS. 9 and 10 showing the configuration of the parallel computer of the third embodiment.
This can be realized by replacing 00 with address translation 104 in FIG. 15 and address translation 110 with address translation 114 in FIG. 16.

In FIG. 15, 103 is a left 3-bit shifter.

In FIG. 16, 113 is a left 3-bit shifter. If a 3-bit shifter is provided on the left in this manner, the above-mentioned mapping becomes possible because a 3-bit shift on the left is equivalent to multiplying integer data such as an address by 8.

Fifth Embodiment> The fifth embodiment will be explained using figures.1 This embodiment is a modification of the first embodiment.The same reference numerals are used in this embodiment and the first embodiment. The components shown have the same configuration. First, an overview of the parallel computer according to this embodiment will be explained with reference to FIG. In FIG. 19, 1-1 to 1-n are n processor elements that can operate independently. 2 is a network, 1-1 or 1-
It receives a data transmission request issued from any n arbitrary processor element and transfers the data to the designated arbitrary processor element.

Next, the configuration of processor elements 1-1 to 1-n will be explained. Processor elements 1-1 to 1-n have the same configuration, but for simplicity in FIG.
Only the inside of -1 is shown. Processor element 1
-1 is processor 13. Receiver 4. Transmitter 5. It is composed of a local memory 6. Details of the processor 13 are shown in FIG. In FIG. 20, 30 is an instruction fetch circuit, and 35 is a program counter.

Reference numeral 36 denotes an instruction register, which is divided into a field 36-1 for storing an instruction code and a field 36-2, 36-3, and 36-4 for storing operands. Reference numeral 1301 denotes an instruction decoding control, which decodes instructions and controls their execution.

A transmission control circuit 1307 is used when executing a vSEND command, which will be described later. A memory access circuit 1302 is used when executing a VRECE IVE instruction, which will be described later. 1308 is a selector, 31 is an OR circuit, 33 is an invalidation circuit, 300 is an AND circuit, 1309.1317
is a selector. 1306 is an address generation circuit. 34 is a general-purpose register group, 1303 is a vector register group, and 1304 and 1305 are arithmetic units. The vector register group 1303 is composed of a plurality of vector registers, and each vector register can be read.

In writing, the elements are accessed in order starting from the first element. 1306 is an address generation circuit, the inside of which is shown in FIG. In Figure 21, 131
0 is a register, 1311 is an increment circuit, 131
2 is a register, 1313 is a decrement circuit, 131
4 is an O detection circuit, and 1315 and 1316 are selectors.

The processor 13 is a so-called vector computer, but for the purpose of this embodiment, it uses a normal vector computer instruction set (memory read, memory write, arithmetic instructions for scalar data, memory read, memory write, arithmetic instructions for vector data, etc.). ), it is now possible to execute some newly established commands. The new order will be discussed later.

The function and configuration of the local memory 6 in FIG. 19 are the same as the local memory 6 in the first embodiment.

Transmitter 5. Receiver 4. Regarding the network 2, transmitters 5 and 5 of the first embodiment are respectively used. Receiver 4° is the same as network 2.

FIG. 19 shows the operation of the processor element 1-1.

This will be explained using FIGS. 20 and 21. First, the instruction fetch circuit 30 in the processor 13 outputs the contents of the program counter 35 and a data read request signal to the fourth port of the local memory 6 via the line L12. Then, the local memory 6 is read out and its contents are output to the line L13, so this is set in the instruction register 36.

The instruction decoding control 1301 decodes the value of the instruction code stored in the field 36-1 of the instruction set in the instruction register 36, and sends a signal to the internal processor 13 to implement the operation specified by the instruction. Distribute to the calculator 1
304. Arithmetic unit 1305. General-purpose register group 34. The vector register group 1303 and the like are operated. When the operation specified by the command is completed, the command decoding control 1301 outputs the line L1.
From step 308, the value of the program counter 35 is updated and the above operations are repeated.

Next, I will explain the newly established commands. First, VSEN
Explain the D command. The VSEND instruction is an instruction for writing vector data possessed by the processor element that executed this instruction into a local memory in another processor element. FIG. 18 shows the format of the VSEND command. The VSEND instruction has three operands.

The operands 1, destination 2, base address 3, and vector data are respectively stored in a general-purpose register specified by R1, a general-purpose register specified by R2, and a vector register specified by the VR3 field of the instruction format. This instruction stores a third contiguous area in the local memory of the processor element specified by the first operand, starting from the address specified by the second operand.
This means writing the vector data specified by the operand. It is assumed that the number of elements of the vector data is stored in advance in a specific register in the general-purpose register group 34 by another instruction. When executing this command,
The parallel computer of this embodiment operates as follows.

First, the instruction decoding control 1301 of the processor 13 reads the values (register numbers) stored in fields 36-2, 36-3 of the instruction register 36 on lines L1302, .
At line L1303, field 3 is added to general register group 34.
The value (vector register number) stored in 6-4 is transmitted to the vector register group 1303 via line L1304. Further, a signal indicating execution of the VSEND command is transmitted to the transmission control circuit 1307 through the aL 1310, and this is activated. Then, the first operand is transmitted via line L1311, and the transmission control circuit 1307 generates a signal on line Lt312. It is output as a line L20 together with the register write request signal that has passed through the selector 1308, and is set to field 50-1 of the register 50 of the transmitter 5. The second operand is 1%LL301. Selector 131
The number of elements of the vector data is stored in the register 1310 via line Ll 301.5. It is stored in the register 1312 via the selector 1316.

Then repeat the following actions.

First, the register 1310 in the address generation circuit 1306
The contents of line L1315. The write request signal generated by the transmission control circuit 1307 is outputted to the line L1320 via the selector 1309, and the write request signal generated by the transmission control circuit 1307 is outputted to the line L1319.
It is set to 〇-2. In parallel with this, one element of the vector register specified by the third operand is read out to line L1311, the transmission control circuit 1307 is activated, and
It is transmitted to the transmitter 5 as a line L20 together with the write signal output to the selector 1308 via the line L20,
It is set in field 50-3. Subsequently, the transmission control circuit 1307 connects the line L1313. Increment circuit 13 in address generation circuit 1306 via line L1306
11. A signal is sent to a decrement circuit 1313 to increase and decrease the contents of registers 1310 and 1312 by 1, respectively. At this time, if the decrement circuit 1313 decreases the contents of the register 1312 by 1 and the result becomes O, the 0 detection circuit 1314 sends a signal to the transmission control circuit 1307 via the line L1307.

The transmitter 5 transmits the contents via the network to the processor element specified by the contents of 50-1 each time a value is set in the register 50. The operations after transmission are the same as in the first embodiment.

Since the number of vector data elements is set in the register 1312 at the beginning of the instruction execution process, the above operation is repeated the same number of times as the number of elements, and then a signal is sent to the transmission control circuit 1307 via line L1307. It turns out.

When this signal arrives, the transmission control circuit 1307 transmits the signal to the line L13.
At step 08, the contents of the program counter are updated. The above is the operation of the VSEND instruction.

Next, the VRECEIVE command will be explained.

The VRECE IVE instruction is an instruction that reads valid data from the local memory of the processor element that executed this instruction and stores it in a vector register. 1st
Figure 7 shows the format of the VRECEIVE command. V
The RECE IVE instruction has two operands.

1, base address 2, vector register number The first operand is stored in the general-purpose register specified by the R1 field of the instruction format, and the second operand is stored in the VR2 field. This instruction means to sequentially read valid data in a continuous area starting from the address specified by the first operand and store it in the vector register specified by the second operand. It is assumed that the number of elements of the vector data is stored in advance in a specific register in the general-purpose register group 34 by another instruction. When executing this instruction, the parallel computer of this embodiment operates as follows.

First, the instruction decoding control 1301 of the processor 13 transfers the value (register number) stored in the field 36-2 of the instruction register 36 to the general-purpose register group 34 via line L1302, and transfers the value (vector register number) on line L1303 to vector register group 1.
Tell 303. Further, a signal indicating execution of the VRECEIVE instruction is transmitted to the memory access circuit 1302 via line L1 309 to activate it. Then the first
The operand is stored in the register 1310 via the ML13ot and selector 1315, and the number of vector data elements is stored in the line L.
1301. Register 131 via selector 1316
2.

Then repeat the following actions.

First, register 131O in address generation circuit 1306
The content of is outputted from the selector 1309 via the line L1315, the data read request signal generated by the memory access circuit 1302 is outputted from the OR circuit 31 via the line L1305, and the data read request signal generated by the memory access circuit 1302 is outputted from the OR circuit 31 via the line L1305. Transferred to third boat. Then, the local memory 6 outputs the tag value on the line L9 and the data on the line LIO.

The tag value output to line L9 is the memory access circuit 13.
02, but when this value is O, the memory access circuit 1302 again generates a memory read request signal on the line L1305 and reads the local memory 6. Line L
9 is 1, the memory access circuit 1302 connects the vector register group 130 to the line L1321.
3, instructs to write the data output on line LIO to the vector register specified by the second operand, and writes the contents of registers 1310 and 1312 in address generation circuit 1306 by increment circuit 1311 on line L1306. It is increased by 1 and decreased by 1 by the degreement circuit 1313. Decrement circuit 1
As a result of decrementing by 1 by 313, the contents of register 1312 are O.
If so, the 0 detection circuit 1314 notifies the memory access circuit 1302 on line L1307. When the value output to line L9 is 1, the output of AND circuit 300 in invalidation circuit 33 becomes 1, so in parallel with the operation of memory access circuit 1302 shown here, line L1315.
Using the value output to the line L6 via the selector 1317 as an address, the value 0 and the output of the AND circuit 300 are transmitted to the second port of the local memory 6 on the line L7 as tag write data and a write request signal, respectively.

As a result, the tag of the word whose address is the value output on line L6 becomes O. Note that this operation is controlled to be performed prior to incrementing the contents of register 1312 described above.

Since the number of vector data elements is set in the register 1312 at the beginning of the instruction execution process, the above operation is repeated the same number of times as the number of elements, and then a signal is sent to the memory access circuit 1302 via line L1307. It turns out. When this signal arrives, memory access circuit 1302 updates the contents of the program counter on line L1308. The above is the operation of the VRECE IVE command.

Next, the operation of the parallel computer according to this embodiment will be explained.

Each processor element constituting the parallel computer according to this embodiment operates in the same manner as a normal vector computer when it does not receive or exchange data with other processor elements. When it is necessary to pass data to and from other processor elements, the area used for data passing in the local memory of the processor element receiving the data (this area is created in advance by the programmer or compiler). (predetermined), the processor element on the data transfer side writes data using the above-mentioned VSEND instruction, and the processor element on the data receiving side reads data using the VRECEIVE instruction. By doing so, the same effects as in the first embodiment can be obtained, and data can be received and delivered at a higher speed than in the first embodiment.

In the above, the area of the local memory 6 accessed by the VSEND instruction and the VRECE IVE instruction is a continuous area, but if the increment circuit 1311 in the address generation circuit 1306 is made programmable, the increment value can be programmed. Be able to handle data groups arranged at equal intervals.

For further flexibility, the following V S E N D L command and VRECE IVEL command may be introduced.

The format of the VSENDL command is shown in FIG. V
The SENDL instruction has three operands.

(2) Destination 2, Address Vector 3, Vector Data Each operand is stored in a general-purpose register designated by R1 of the instruction format, and a vector register designated by VR2 and VR3, respectively.

This instruction writes the j-th element (j=1 r 2+ . . . ) of the vector of the second operand in the local memory of the processor element specified by the first operand.

The third address is specified by the number of elements of vector data.
This means writing the Jth element of the operand vector. It is assumed that the number of elements of the vector data is stored in advance in a specific register in the general-purpose register group by another instruction.

This instruction can be executed in substantially the same way as the VSEND instruction described above, but differs in the following points.

In the VSEND command, the value generated by the address generation circuit 1306 is used as the value set in the field 50-2 of the register 50 of the transmitter 5, and this is set on the line L1315. Selector 1309. 5 via line L1320 and line L21
It was supposed to be set to 0-2, but VSENDL
In the instruction, field 3 of the instruction register 36 is set in advance.
Vector register group 1303 specified by the contents of 6-3
The vector register within is selected via line L1303, and the contents of this vector register are displayed on line L1314. Selector 1309. 5 via line L1320 and line L21
It may be set to 0-2.

Next, the format of the VRECE I VEL command is shown in FIG. The VRECEIVEL instruction has two operands.

(2) Address vector 2, Vector register number Each operand is located in the vector register and VR2 field specified by (1) R1 field of the instruction format, respectively. This instruction returns the jth element of the vector of the first operand! '(J = 1 + 2+...

This means reading valid data from the address specified by (number of elements of vector data) and writing it to the j-th element of the vector register of the second operand. It is assumed that the number of elements of the vector data is stored in advance in a specific register in the general-purpose register group by another instruction.

This instruction can be executed in much the same way as the V RE CE I VE instruction described above, but differs in the following points.

In the VRECE IVE instruction, the value generated by the address generation circuit 1306 is used as the address for reading from the local memory 6, and this is sent to the line L1315 and the selector 130.
9. via line L8 or via line L1315. Selector 1317. The address was to be transmitted to local memory 6 via line L6, but VRECEIVEL
In the instruction, field 3 of the instruction register 36 is set in advance.
Vector register group 1303 specified by the contents of 6-2
The vector register in line L1302 is selected, and the contents of this vector register are written in line L1314. Selector 1309. via line L8 or line L131
5. The information may be transmitted to the local memory 6 via the selector 1317 and the line L6.

According to the above, the address column of the local memory 6 is set in advance in the vector register in the vector register group 1303, and this is set in the second register of the VSENDL instruction.
By specifying the operand or the first operand of the VRECEIVEL instruction and executing each instruction, any data group arranged in the local memory 6 can be efficiently received between processor elements while guaranteeing the reference order. will be able to be passed.

〔Effect of the invention〕

According to the present invention, it is possible to significantly reduce the overhead that occurs when receiving and passing data between processors in a parallel computer that is composed of a plurality of processor elements each having a local memory and in which data can be written to the local memory from other processor elements. becomes possible,
Parallel computers will be able to demonstrate high performance.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a parallel computer according to a first embodiment of the present invention, FIG. 2 is a detailed diagram of a processor constituting the first embodiment, and FIG. 3 is a diagram showing the format of a RECE IVE instruction. FIG. 4 is a diagram showing the format of the 5END instruction,
FIG. 5 is an overall configuration diagram of a parallel computer according to a second embodiment of the present invention, FIG. 6 is a detailed diagram of a processor constituting the second embodiment, and FIG. 7 is a diagram of a parallel computer according to a second embodiment. FIG. 8 is a diagram showing the memory space seen from the architecture.
FIG. 9 is a diagram showing the relationship between two memory spaces.
10 is a detailed diagram of the processor configuring the third embodiment, and FIG. 11 is a detailed diagram of the processor configuring the third embodiment.
12 is a diagram showing another address translation circuit used in the third embodiment, and FIG. 13 is another implementation of the third embodiment. FIG. 14 is a diagram showing the relationship between two memory spaces seen from the architecture of a parallel computer according to the fourth embodiment of the present invention, and FIG. 15 is a diagram showing the relationship between two memory spaces in the fourth embodiment. A diagram showing one of the address conversion circuits used, FIG. 16 is a diagram showing another address conversion circuit used in the fourth embodiment, and FIG. 17 is a diagram showing VRECEIVE.
18 is a diagram showing the format of the VSEND instruction, FIG. 19 is an overall configuration diagram of a parallel computer according to the fifth embodiment of the present invention, and FIG. 20 is a diagram showing the configuration of the fifth embodiment. 21 is a diagram showing the address generation circuit used in the fifth embodiment. FIG. 22 is a diagram showing the format of the VRECEIVEL instruction.
FIG. 3 is a diagram showing the format of the VSENDL instruction. 5. Explanation of symbols 1... Processor element, 2 ・Network,
3...processor, 4...receiver, 5...transmitter,
6... Local memory, 30... Instruction fetch circuit,
31...OR circuit, 32-4LU, 33...invalidation circuit, 34...general-purpose register group, 35...program counter, 36...instruction register, 37...instruction decoding control, 38...memory Access circuit, 300...AND
circuit, 40... register, 50... register, 41
...Write control.

Claims (1)

[Claims] 1. Consisting of a plurality of processor elements having local memory and capable of operating independently, and a network connecting the plurality of processor elements, each of the plurality of processor elements is connected to the other processor elements. In a parallel computer capable of writing data into the local memory via the network, a tag is provided to a part or all of the words in the local memory of the plurality of processor elements, and the tag attached to the word is an enabling means for indicating whether data held by a word is valid or invalid and setting the content of a tag attached to the word to indicate the validity when data is written to the word from an arbitrary processor element; 1. A parallel computer comprising tag access means for inspecting the content of a tag attached to a word and repeating the inspection for the word until the tag indicates the validity. 2. In a parallel computer consisting of a plurality of processor elements that have local memory and can operate independently and a network that connects the plurality of processor elements,
Each of the plurality of processor elements is provided with a reception memory that can be written to from any processor element via the network, a tag is provided to some or all of the words constituting the reception memory, and a tag is attached to the word. The tag indicates whether the data held by the word is valid or invalid,
an enabling means for setting the content of a tag attached to the word to indicate the validity when data is written to the word from an arbitrary processor element; and an enabling means for inspecting the content of the tag attached to the word to confirm that the tag is A parallel computer comprising: tag access means for repeating checking of the word until the word is determined to be valid. 3. The logical address specified when writing data to the local memory in another processor element and the real address assigned to the local memory are different, and the logical address specified when writing data to the local memory in another processor element is different. A writing address conversion circuit that converts an address into a real address, and a read address conversion circuit that converts a logical address into a real address when reading data written using the address conversion circuit. A parallel computer according to claim 1. 4. The scope of the claim is characterized in that an address generation means is provided for sequentially generating an address specified when writing data to a local memory in another processor element and an address specified when reading data from the local memory. Parallel computer according to item 1.