JPH01191460A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH01191460A
JPH01191460A JP1473888A JP1473888A JPH01191460A JP H01191460 A JPH01191460 A JP H01191460A JP 1473888 A JP1473888 A JP 1473888A JP 1473888 A JP1473888 A JP 1473888A JP H01191460 A JPH01191460 A JP H01191460A
Authority
JP
Japan
Prior art keywords
lsi
board
rear surface
chip
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1473888A
Other languages
Japanese (ja)
Other versions
JPH0650760B2 (en
Inventor
Yukio Kamiya
幸男 神谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1473888A priority Critical patent/JPH0650760B2/en
Publication of JPH01191460A publication Critical patent/JPH01191460A/en
Publication of JPH0650760B2 publication Critical patent/JPH0650760B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To make it possible to simplify the manufacturing process and to decrease the number of parts to be used, by fixing an LSI chip to hole parts of a ceramic board, electrically connecting the wiring in a chip that is exposed out of the rear surface of the LSI chip at the rear surface of the board, and forming a circuit. CONSTITUTION:An aluminum wiring 14 is formed in each V groove 16 in an LSI chip. The LSI chip is temporarily attached to a hole part 2 which is provided in a ceramic board 1. The rear surface of each chip 11 is protruding from the rear surface of the board 1. Then, a surface cover layer 5 is formed on the surface of the board 1. The chip 11 is fixed. The rear surface of the board 1 is scraped so that the surface is made to agree with the height of the rear surface of the board 1. An insulating film 3 is formed on the rear surface of the board 1 by using PSG and the like. The exposed part of the aluminum wring 14 is selectively etched, and holes are provided. A film is formed by sputtering aluminum, copper and the like, and a pattern is formed. Thus, a rear wiring 4 is formed. The chips 11 are mutually connected electrically. Thus, a required electric circuit is constituted. Thereafter, a rear surface cover layer 6 is formed. Each LSI chip 11 is sealed, and the manufacturing is completed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路(以下、LSIと略称する)に
関し、特にシステムを構成する複数のLSIチップを一
括して実装するLSIに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit (hereinafter abbreviated as LSI), and particularly to an LSI in which a plurality of LSI chips constituting a system are collectively mounted.

〔従来の技術〕[Conventional technology]

従来、複数のLSIチップを用いて電子回路システムを
構成する場合には、各LSIチップを夫々個別のセラミ
ックケース等に搭載し、かつリード接続して個々のパッ
ケージを構成する。その上で、これらのLSIパッケー
ジを夫々同一のプリント基板上に実装し、かつこれらを
相互に電気接続して電子回路を構成する2段階構成とな
っていた。
Conventionally, when constructing an electronic circuit system using a plurality of LSI chips, each LSI chip is mounted in an individual ceramic case or the like and connected with leads to construct an individual package. Then, these LSI packages were mounted on the same printed circuit board, and they were electrically connected to each other to form an electronic circuit, resulting in a two-stage configuration.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の複゛数LSIチップを用いたLSIは、
第一の段階で個々のLSIチップをパッケージする必要
があり、この工程ではその組立てに於いてワイヤーボン
ディング等の機械的な精密工作を必要とし、かつウェハ
加工工程と全く異質の組立工程を必要とする。また、第
二の段階では形成された複数のLSIパッケージを夫々
プリント基板上へ実装する工程を必要とする。このため
、LSIの製造工程が複雑化し、かつ使用部材も多くな
る等の問題を有している。
The LSI using the conventional multiple LSI chips mentioned above is
In the first step, it is necessary to package individual LSI chips, and this process requires precision mechanical work such as wire bonding, and requires an assembly process that is completely different from the wafer processing process. do. Furthermore, the second step requires a step of mounting each of the formed LSI packages onto a printed circuit board. For this reason, there are problems such as the LSI manufacturing process becoming complicated and the number of parts used increasing.

本発明は製造工程の簡略化を図るとともに、使用部材を
も少なくできるLSIを提供することを目的としている
An object of the present invention is to provide an LSI that can simplify the manufacturing process and reduce the number of parts used.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のLSIは、複数の開孔部を有するセラミンク基
板と、このセラミック基板の各開孔部に固着された複数
のLSIチップと、前記セラミック基板の裏面に設けら
れて前記LSIチップの裏面に艙呈されたチップ内配線
に接続される裏面配線とで構成している。
The LSI of the present invention includes a ceramic substrate having a plurality of holes, a plurality of LSI chips fixed to each hole of the ceramic substrate, and a plurality of LSI chips provided on the back surface of the ceramic substrate and attached to the back surface of the LSI chips. It consists of backside wiring connected to exposed internal chip wiring.

〔作用〕[Effect]

上述した構成のLSIでは、セラミック基板にLSIチ
ップを搭載しかつその電気接続を行うことにより所要の
回路を構成することが可能となり、製造工程の簡略化、
使用部品の低減が可能となる。
In the LSI with the above-mentioned configuration, it is possible to configure the required circuit by mounting the LSI chip on a ceramic substrate and making electrical connections, which simplifies the manufacturing process.
It is possible to reduce the number of parts used.

・〔実施例〕 次に、本発明を図面を参照して説明する。·〔Example〕 Next, the present invention will be explained with reference to the drawings.

第1図は2つのLSIチップを実装して電子回路を構成
したLSIに本発明を適用した実施例を示しており、同
図(a)は平面図、同図(b)はそのAA線に沿う断面
図である。
Figure 1 shows an embodiment in which the present invention is applied to an LSI in which two LSI chips are mounted to form an electronic circuit. FIG.

このLSIは、1枚のセラミック基板1に複数個、ここ
では2個の方形の開孔部2を開設し、ここにLSIチッ
プ11を夫々固着している。このLSIチップ11はシ
リコン基板12の表面にトランジスタ等の素子回路13
と、これに接続されるアルミニウム配線14とが形成さ
れ、カバー膜15によって被覆されている。ここで、チ
ップ内配線としての前記アルミニウム配線14はシリコ
ン基板12に設けたV字溝16内面に沿って形成され、
そのv字溝16の底面からチップ裏面に露呈されている
In this LSI, a plurality of rectangular openings 2, in this case two square openings 2, are formed in one ceramic substrate 1, and LSI chips 11 are fixed therein. This LSI chip 11 has an element circuit 13 such as a transistor on the surface of a silicon substrate 12.
and aluminum wiring 14 connected thereto are formed and covered with a cover film 15. Here, the aluminum wiring 14 as the intra-chip wiring is formed along the inner surface of the V-shaped groove 16 provided in the silicon substrate 12,
The bottom surface of the V-shaped groove 16 is exposed to the back surface of the chip.

そして、前記セラミック基板1の裏面には裏面絶縁膜3
と裏面配線4が形成され、前記LSIチップ11のアル
ミニウム配線14の露呈部はこの裏面配線4によって接
続され、2個のLSIチップにより所要の電子回路を構
成している。
A back insulating film 3 is provided on the back surface of the ceramic substrate 1.
A backside wiring 4 is formed, and the exposed portion of the aluminum wiring 14 of the LSI chip 11 is connected by this backside wiring 4, and the two LSI chips constitute a required electronic circuit.

更に、これらのLSIチップ11はセラミック基板1の
表面及び裏面に設けた表面カバー層5と裏面カバー層6
によって一体的に封止されている。
Furthermore, these LSI chips 11 have a front cover layer 5 and a back cover layer 6 provided on the front and back sides of the ceramic substrate 1.
It is integrally sealed by.

第2図(a)〜第2図(C)は第1図のLSIの製造方
法を工程順に示す断面図である。
FIGS. 2(a) to 2(C) are cross-sectional views showing the method for manufacturing the LSI shown in FIG. 1 in order of steps.

先ず、第2図(a)のように、V字溝16にアルミニウ
ム配線14を形成しているLSIチップを、セラミック
基板1に開設した開孔部2内に仮付けする。このとき、
各LSIチップ11の裏面がセラミック基板1の裏面よ
りも突出されるようにすることが肝要である。
First, as shown in FIG. 2(a), an LSI chip having aluminum wiring 14 formed in a V-shaped groove 16 is temporarily attached in an opening 2 made in a ceramic substrate 1. At this time,
It is important that the back surface of each LSI chip 11 be made to protrude beyond the back surface of the ceramic substrate 1.

次に、第2図(b)のように、セラミック基板1の表面
にPSG、酸化膜、窒化膜、多結晶シリコン等を堆積し
、或いは樹脂を融着し、更にはこれらの組合せによって
表面カバー層5を形成し、前記LSIチップ11をセラ
ミック基板1に固着する。
Next, as shown in FIG. 2(b), PSG, oxide film, nitride film, polycrystalline silicon, etc. are deposited on the surface of the ceramic substrate 1, or resin is fused, and a surface cover is formed by a combination of these. A layer 5 is formed and the LSI chip 11 is fixed to the ceramic substrate 1.

次に、第2図(c)のように、LSIチップ11の裏面
を研磨、研削、エツチング等の手段によって削り取り、
LSIチップ11の裏面をセラミック基板1の裏面高さ
に一致させる。これにより、アルミニウム配線14はそ
の一部がV字溝16の底部から露呈される。
Next, as shown in FIG. 2(c), the back surface of the LSI chip 11 is removed by polishing, grinding, etching, etc.
The back surface of the LSI chip 11 is made to match the height of the back surface of the ceramic substrate 1. As a result, a portion of the aluminum wiring 14 is exposed from the bottom of the V-shaped groove 16.

しかる上で、第1図(b)c示したように、セラミック
基板1の裏面にPSG等を用いて裏面絶縁膜3を形成し
、前記アルミニウム配線14の露出された箇所を選択的
にエツチングして開孔する。
Then, as shown in FIG. 1(b)c, a back insulating film 3 is formed using PSG or the like on the back surface of the ceramic substrate 1, and the exposed portions of the aluminum wiring 14 are selectively etched. Drill the hole.

更に、アルミニウム、銅、タングステン等の金属のをバ
ッタ成膜し、かつこれをパターン形成することにより裏
面配線4を形成し、LSIチップ11を相互に電気接続
し、所要の電子回路を構成する。
Further, a metal such as aluminum, copper, tungsten, etc. is deposited in a batter and patterned to form the back wiring 4, and the LSI chips 11 are electrically connected to each other to form a required electronic circuit.

その後、セラミック基板1の裏面、に裏面カバー層6を
形成し、各LSIチップ11を封止して製造を完了する
Thereafter, a back cover layer 6 is formed on the back surface of the ceramic substrate 1, and each LSI chip 11 is sealed to complete manufacturing.

この構造によれば、LSIの製造に際しては、セラミッ
ク基板1に直接LSIチップ11を搭載し、かつこれら
に対する電気配線を施すだけで所要の電子回路を構成で
きるので、従来のようなパッケージ形成工程と実装工程
の2段階の工程を不要とし、製造の簡略化及び使用部品
の低減を達成できる。
According to this structure, when manufacturing an LSI, the required electronic circuit can be constructed by simply mounting the LSI chip 11 directly on the ceramic substrate 1 and providing electrical wiring thereto, so that it is possible to construct the required electronic circuit without using the conventional package forming process. This eliminates the need for a two-step mounting process, making it possible to simplify manufacturing and reduce the number of parts used.

なお、本実施例ではLSIチップ数を2つとして説明し
たが、セラミック基板の大きさや形状を変更することに
より、3つ以上のLSIチップの実装が可能となる。
Although this embodiment has been described with the number of LSI chips as two, it is possible to mount three or more LSI chips by changing the size and shape of the ceramic substrate.

また、その製造に際しては、セラミック基板上に予め銅
などの金属を用いた配線パターンを形成しておいてもよ
い。更に、LSIチップの裏面研削をウェハ製造時の最
終工程で行っておくことも可能である。
Further, in manufacturing the ceramic substrate, a wiring pattern using metal such as copper may be formed in advance on the ceramic substrate. Furthermore, it is also possible to grind the back surface of the LSI chip in the final step of manufacturing the wafer.

第3図は本発明の他の実施例の断面図であり、この図は
セラミック基板1にLSISIチツプAを搭載した製造
工程での断面図を示している。
FIG. 3 is a cross-sectional view of another embodiment of the present invention, and this figure shows a cross-sectional view in a manufacturing process in which an LSISI chip A is mounted on a ceramic substrate 1.

この実施例では、セラミック基板1に設ける開孔部2A
を基板の裏面側から開設した未貫通の凹部として形成し
、ここにLSISIチツプAの上面側を挿入して固着し
ている。この場合、LSIチップ11Aの表面カバー膜
15Aを多結晶シリコンで形成してお(ことにより、セ
ラミック基板1への固着に際して金シリコン共晶等を利
用でき、LSIチップの固着を容易に行うことが可能と
なる。
In this embodiment, the opening 2A provided in the ceramic substrate 1 is
is formed as a non-penetrating recess opened from the back side of the board, into which the top side of the LSISI chip A is inserted and fixed. In this case, the surface cover film 15A of the LSI chip 11A is formed of polycrystalline silicon (thereby, gold-silicon eutectic etc. can be used for fixing to the ceramic substrate 1, and the LSI chip can be easily fixed). It becomes possible.

また、各LSIチップIIAは多結晶シリコンを深溝構
造に形成して配線14Aを形成しているので、シリコン
基板12Aの裏面研削等が一層容易となる。この場合、
多結晶シリコンの配線14AはLSIチップの全面に配
置しているので、セラミック基板1の裏面における配線
の自由度を高めることもできる。
Moreover, since each LSI chip IIA has polycrystalline silicon formed in a deep groove structure to form the wiring 14A, it becomes easier to grind the back surface of the silicon substrate 12A. in this case,
Since the polycrystalline silicon wiring 14A is arranged over the entire surface of the LSI chip, the degree of freedom in wiring on the back surface of the ceramic substrate 1 can also be increased.

なお、この実施例においても、第2図の製造方法を用い
ることにより、略第1図に準する構造が構成できること
は言うまでもない。
It goes without saying that in this embodiment as well, by using the manufacturing method shown in FIG. 2, a structure substantially similar to that shown in FIG. 1 can be constructed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、セラミック基板の開孔部
にLSIチップを固着し、かつセラミック基板の裏面に
おいてLSIチップの裏面に露呈されたチップ内配線を
裏面配線に電気接続して回路を構成しているので、プリ
ント基板上にLSIパッケージを実装したシステムと全
(等価なLSIパッケージを極めて簡略な工程で製造可
能とする効果がある。
As explained above, the present invention configures a circuit by fixing an LSI chip in the opening of a ceramic substrate, and electrically connecting the internal wiring exposed on the back side of the LSI chip to the back side wiring on the back side of the ceramic substrate. This has the effect of making it possible to manufacture an LSI package equivalent to a system in which an LSI package is mounted on a printed circuit board in an extremely simple process.

また、LSIチップ内配内配置呈をLSIチップ裏面の
研削等によって行っており、その研削厚は任意性がある
ため、LSIチップ裏面とセラミック基板面の高さを一
致させること、及び裏面配線の形成を夫々容易で確実な
ものにでき、LSIの信頬性を高めることができる効果
がある。
In addition, the internal layout of the LSI chip is achieved by grinding the back surface of the LSI chip, and since the thickness of the grinding is arbitrary, it is important to match the heights of the back surface of the LSI chip and the surface of the ceramic substrate, and to remove the back surface wiring. This has the effect of making the formation easier and more reliable, and increasing the credibility of the LSI.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体集積回路の一実施例を示し、同
図(a)はその平面図、同図(b)はそのAA線に沿う
断面図、第2図(a)〜第2図(c)は製造方法を説明
するための断面図、第3図は本発明の他の実施例の製造
工程途中の断面図である。 ■・・・セラミック基板、2,2A・・・開孔部、3・
・・裏面絶縁膜、4・・・裏面配線、5・・・表面カバ
ー層、6・・・裏面カバー層、11・・・LSIチップ
、  12゜12A・・・シリコン基板、13・・・素
子回路、14・・・アルミニウム配線、14A・・・多
結晶シリコン配線、15.15A・・・カバー膜、16
・・・1字溝。
FIG. 1 shows an embodiment of the semiconductor integrated circuit of the present invention, FIG. 1(a) is a plan view thereof, FIG. FIG. 3(c) is a sectional view for explaining the manufacturing method, and FIG. 3 is a sectional view in the middle of the manufacturing process of another embodiment of the present invention. ■...Ceramic substrate, 2,2A...Opening part, 3.
... Back insulating film, 4... Back wiring, 5... Front cover layer, 6... Back cover layer, 11... LSI chip, 12゜12A... Silicon substrate, 13... Element Circuit, 14... Aluminum wiring, 14A... Polycrystalline silicon wiring, 15.15A... Cover film, 16
...1-character groove.

Claims (1)

【特許請求の範囲】[Claims] 1、複数の開孔部を有するセラミック基板と、このセラ
ミック基板の各開孔部に固着された複数の半導体集積回
路チップと、前記セラミック基板の裏面に設けられて前
記半導体集積回路チップの裏面に露呈されたチップ内配
線に接続される裏面配線とを備えることを特徴とする半
導体集積回路
1. A ceramic substrate having a plurality of openings, a plurality of semiconductor integrated circuit chips fixed to each opening of the ceramic substrate, and a ceramic substrate provided on the back surface of the ceramic substrate and attached to the back surface of the semiconductor integrated circuit chips. A semiconductor integrated circuit comprising: backside wiring connected to exposed internal chip wiring;
JP1473888A 1988-01-27 1988-01-27 Semiconductor integrated circuit Expired - Lifetime JPH0650760B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1473888A JPH0650760B2 (en) 1988-01-27 1988-01-27 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1473888A JPH0650760B2 (en) 1988-01-27 1988-01-27 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPH01191460A true JPH01191460A (en) 1989-08-01
JPH0650760B2 JPH0650760B2 (en) 1994-06-29

Family

ID=11869463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1473888A Expired - Lifetime JPH0650760B2 (en) 1988-01-27 1988-01-27 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH0650760B2 (en)

Also Published As

Publication number Publication date
JPH0650760B2 (en) 1994-06-29

Similar Documents

Publication Publication Date Title
KR100656218B1 (en) System on a package fabricated on a semiconductor or dielectric wafer
US6022758A (en) Process for manufacturing solder leads on a semiconductor device package
US5481133A (en) Three-dimensional multichip package
US5731222A (en) Externally connected thin electronic circuit having recessed bonding pads
US5606198A (en) Semiconductor chip with electrodes on side surface
JP3229206B2 (en) Endcap chip with conductive monolithic L-connection for multichip stacks and method of making same
US6818998B2 (en) Stacked chip package having upper chip provided with trenches and method of manufacturing the same
JP2889160B2 (en) Semiconductor chip and electronic module having integrated surface element interconnection and method of manufacturing the same
US5668409A (en) Integrated circuit with edge connections and method
JPH01166543A (en) Vlsi package
JPH10178124A (en) Chip size package manufactured on wafer level
JP2001044357A (en) Semiconductor device and manufacture thereof
JPH09232508A (en) Multichip package including pattern metal layer and insulating layer and using lead frame
JP2004071961A (en) Compound module and manufacturing method thereof
US10403510B2 (en) Method of fabricating a carrier-less silicon interposer using photo patterned polymer as substrate
JPH08306724A (en) Semiconductor device, manufacturing method and its mounting method
JP2001320015A (en) Semiconductor device and its manufacturing method
CN113097201B (en) Semiconductor packaging structure, method, device and electronic product
JP3394696B2 (en) Semiconductor device and manufacturing method thereof
JP4009380B2 (en) Manufacturing method of semiconductor chip
JPH01191460A (en) Semiconductor integrated circuit
JPH11354667A (en) Electronic part and its mounting method
JP3692353B2 (en) Assembling method of semiconductor device
JPH10209164A (en) Manufacture of semiconductor device
JP2002124597A (en) Method for producing component surrounded with plastic and component surrounded with plastic