JPH01185737A - Shift path circuit for ram - Google Patents

Abstract

PURPOSE:To perform a fast continuous operation on a RAM by performing the designation of an address after setting an initial address by a shift operation by incrementing data set at an address register automatically. CONSTITUTION:A shift lock counter circuit 103 is counted up at every output of one shift clock, and at a time when the number arrives equivalent to the number of bits of one word of the RAM20, a write pulse issuing circuit 105 issues a write pulse to the RAM20, and write data held at a write data register 16 is written on the designated address of the RAM20. Next, the address register 12 is set at an enable state by an address register enable circuit 102, and also, address data set already by an address increment circuit 104 is incremented, and the address data is held at the address register 12. In such a way, it is possible to write continuous data at high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an R computer system that writes data to or reads data from a RAM using a shift path during evaluation.
This invention relates to an AM shift path circuit.

[Conventional technology]

There are various computer systems that use shift paths, but among them, the following methods are commonly used to access R, A, and M. That is, when writing data to RAM, the RAM address and write data are set in advance by a shift pass,
After that, the shift mode is released, and then a system clock is issued to generate a write pulse to write data to the RAM.

Also, when reading data, the RAM address is set in advance using a shift pass, then the shift mode is canceled, the system clock is issued and the read data of the RAM is held, and then the shift mode is set again and the shift clock is issued. This method was used to read out the data.

[Problem to be solved by the invention]

In the above-mentioned conventional read/write method for R and AM using a shift path, an address must be set for each access, the shift mode must be turned on and off, and the system A clock must be issued. Therefore, writing continuous data,
There is a problem in that reading takes time, and in order to access one address, it is necessary to issue shift clocks for the number of bits equal to the total number of registers connected to the shift path.

The present invention was made in view of these circumstances, and
It is an object of the present invention to provide a shift path circuit for RAM that can read or write continuous data to or from RAM at high speed.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a computer system in which data is written to or read from RAM using a shift path during evaluation. A register, a write data register that holds data written to RAM, a read data register that holds data read from RAM, and a shift-out data switch that switches shift out to the write data register or read data register. The circuit controls the shift-out data switching circuit according to write or read instructions, and when writing, shifts and sets one word of write data to the write data register, and sends a write pulse to the RAM. After setting the write data to the specified address of RAM, the address set in the address register is incremented, and this series of operations is repeated for the required number of words, and when reading, the read data of the specified address of RAM is incremented. The present invention is characterized by comprising a control means for shifting out the read data after setting it in the read data register, incrementing the designated address, and repeating this series of operations for the required number of words.

According to the present invention, after setting the initial address when accessing the RAM, there is no need to specify the address each time an access is made, and it is only necessary to increment the address. Since it is not necessary to issue a clock, continuous data can be written to or read from the RAM at high speed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of a RAM shift path circuit according to the present invention. In the figure, the shift path circuit includes a control unit lO, an address register 12, an address increment circuit 14, and a write data register 16.
, a read data register 18 , and a shift-out data switching circuit 30 .

The control unit 10 enables a read/write setting circuit 100 in which read or write instructions are set by external input, an address input switching circuit 101 that selects an address to be set in the address register 12, and the address register 12. Address register enable circuit 102
, issues a shift clock and sets this shift clock to R.
A shift clock count circuit 103 counts the number of bits for one word of the RAM 20, a read data register enable circuit 104 enables data input to the read data register 18 when reading data from the RAM 20, and and a write pulse issuing circuit 105 that issues a write pulse to the RAM 20 when writing.

The address register 12 is a register that holds the address data of the address specified when accessing the RAM 20, and after the specified address is initialized in the address register 12, writing or reading of one word of data to the RAM 20 is completed. Each time the specified address is specified, the specified address is automatically incremented by the address increment circuit 14, thereby specifying the address.

The write data register 16 is a register in which write data inputted from the outside is shifted and set by a shift clock output from the shift clock count circuit 103, and holds the write data.

The read data register 18 is a register that holds data read from the RAM 20. The shift-out data switching circuit 30 selects the read data register 18 during reading.
This selector selects the shift-out data of the write data register 16 during writing.

In the above configuration, the control unit 10 determines whether the access to the RAM 20 is to read or write data.
The write setting circuit 100 makes a determination, and the shift-out data switching circuit 30 is controlled to switch based on the determination result.

Next, the address input switching circuit 101 switches the designation of the address to be accessed to the RAM 20 to the external input terminal, and the address register 12 is enabled by the address register enable circuit 102.

As a result, the address to be accessed from the outside to the RAM is initialized. Then, the input of the address register 12 is switched to the address increment circuit side by the address manual switching circuit 101.

When writing data to the RAM 20, the shift-out switching circuit 30 is switched to the write data register 16 side by the output signal of the read/write setting circuit 100, and
The shift clock count circuit 103 issues a shift clock and shifts and sets write data in the write data register 16. This shift clock count circuit 103 is 1
The write pulse issuing circuit 105 counts up each time it outputs a shift clock, and when the number becomes equal to the number of bits for one word of the RAM 20, the write pulse issuing circuit 105 issues a write pulse to the RAM 20, The write data held in the write data register 16 is written to the designated address of the RAM 20. Next, the address register 12 is enabled by the address register enable circuit 102, the address data already set is incremented by the address increment circuit 14, and the incremented address data is held by the address register 12. By repeating these series of operations for the required number of words, continuous data is sequentially written into the RAM 20.

Similarly, when reading data from the RAM 20, the shift-out data switching circuit 30 is switched to the read data register 18 side by the output signal of the read/write setting circuit 100, and the read data register enable circuit 104 switches the shift-out data switching circuit 30 to the read data register 18 side. is enabled, and data read from the RAM 20 is set in the read data register 18. Next, the shift clock count circuit 103 issues shift clocks by the number of bits corresponding to one word of the RAM 20, and shifts out the read data set in the read data register via the shift-out data switching circuit 30. After this, the address register 12 is set to the address register enable circuit 10.
2, the address increment circuit 14 increments the address data, and the incremented address data is held by the address register 12. By repeating these series of operations for the required number of words, RA
Continuous data in M20 is sequentially read out.

〔Effect of the invention〕

As explained above, in the present invention, when reading or writing data to RAM using a shift bus during evaluation, the address specification after setting the initial address automatically uses the data set in the address register. This is done by incrementing the data manually, and data is written or read by a shift operation.
It becomes possible to continuously write or read data to or from the RAM at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a RAM shift bus circuit according to the present invention. 410...control unit, 12...address register, 14...address increment circuit, 16...
...Write data register, 18...Read data register, 20...Shift-out data switching circuit.

Claims (1)

[Claims] In a computer system that writes data to or reads data from RAM using a shift path during evaluation, an address to be accessed in RAM is set, and an address register that holds this address data, and A write data register that holds write data, a read data register that holds data read from RAM, a shift-out data switching circuit that switches shift out to the write data register or read data register, and write or read data register. Controls the switching of the shift-out data switching circuit according to instructions, shifts and sets one word of write data to the write data register during writing, issues a write pulse to the RAM, and transfers the write data to the RAM. After setting the specified address in the RAM, the address set in the address register is incremented, and this series of operations is repeated for the required number of words. At the time of reading, after setting the read data of the specified address in the RAM in the read data register, A shift path circuit for a RAM, comprising a control means for shifting out the read data, then incrementing the specified address, and repeating a series of these operations for a required number of words.