JPH01185020A - Driver - Google Patents

Abstract

PURPOSE:To obtain a storing function and an output short circuit protecting function and to execute the high function of a driver by positively feeding back the output of a first field effect transistor to the input of a complementary second field effect transistor. CONSTITUTION:A drain which is the output of the first field effect transistor 101 is positively fed back from the gate through drain of a second field effect transistor 102 to the gate which is the input of the first field effect transistor 101. Namely, the driver has a bistable condition, a first stable condition is the condition in which both the first and second field effect transistors 101 and 102 are turned on, and a second stable condition is the condition in which the first and second field effect transistors 101 and 102 are turned off. Consequently, by using both stable conditions, the storing function is realized, drive date are written from the gate of the first field effect transistor 101, and an output short circuit is detected from the gate of the second field effect transistor 102. Thus, the simple driver to have the storing function and output short circuit protecting function can be obtained.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a drive device having a memory function.

[Summary of the invention]

The present invention provides a drive device including a first field effect transistor, a second field effect transistor complementary to the first field effect transistor, and a second field effect transistor complementary to the first field effect transistor.
The output of the first field effect transistor is configured to be positively fed back to the input of the second field effect transistor, so it has a memory function and an output short circuit protection function, and the drive device High functionality has been achieved [Problem to be solved by the invention] In a drive device having a plurality of outputs, a function of storing the state of each output is an essential function. Additionally, functions to monitor each output status and protect against output short circuits are also essential functions. However, a drive device having a plurality of outputs has a problem in that the configuration becomes complicated to realize these functions.

SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a drive device that achieves both the memory function and the output short-circuit protection function with a simple configuration.

[Means to solve the problem]

The driving device of the present invention includes a first field effect transistor, a first field effect transistor, and a first field effect transistor.
has a complementary second field effect transistor to the field effect transistor, and the drain which is the output of the first field effect transistor is connected to the first field effect transistor from the gate of the second field effect transistor via the drain. It is characterized by positive feedback to the gate, which is the input of the transistor.

[Effect]

According to the above configuration of the present invention, the drain which is the output of the first field effect transistor is positively fed back from the gate of the second field effect transistor to the gate which is the input of the first field effect transistor via the drain. Therefore, the drive device has a bistable state, and the first stable state is equal to the first and second stable state.
The partner of the field effect transistor is in the on state,
Since the second stable state is a state in which the first and second field effect transistors are off, both of these stable states are used to realize the memory function, and drive data is written to the gate of the first field effect transistor. Therefore, the output short circuit is detected from the gate of the second field effect transistor.

(Embodiment) Fig. 1 is a circuit diagram of a driving device in an embodiment of the present invention.A field effect transistor 101 is a first field effect transistor in the claims, and is an N-channel depression type field effect transistor. The transistor is a field effect transistor 102, which is a second field effect transistor in the claims, and is a P channel depletion type field effect transistor.Field effect transistor 1
01.102 are connected to respective gates of field effect transistors 102 and 1.01, and further connected to resistors 103 and 104. resistance 103
The other end is grounded together with the source of the field effect transistor. The other end of the resistor 104 is connected to the source 114 along with the source of the field effect transistor 102 . Load 113 is connected to power supply 114 and the drain of field effect transistor 101 . Switch 112 is connected between the gate of field effect transistor 101 and ground, and switch 111 is connected between the gate of field effect transistor 101 and 1! i
1114. The input terminal 105 is a drive bag,
[ is a data input/output terminal, and a power supply is connected between the ground terminal 1061 and the power supply terminal 107, and the output terminal 108 is connected to the load 113.

Next, the circuit operation of the driving device in the embodiment of the present invention shown in FIG. 1 will be explained. The load 113 can be driven as resistive, accommodative, or inductive in nature; however, in the case of an inductive load, a diode may be required to clamp the reverse induced voltage. The switches 111 and 112 are turned off in the initial state. When the switch 111 is turned on, the field effect transistor 101 is turned on, so that a voltage of approximately the same value as the power supply 114 is applied to the load 113, and in parallel with this, the field effect transistor 102 is also turned on. That is, switch 11
Since the field effect transistor 102 connected in parallel to 1 is turned on, even if the switch 111 is turned off, the state in which the voltage is applied to the load 113 is maintained. When the switch 112 is turned on from this state, the field effect transistor 101 is turned off, so the voltage applied to the load 113 becomes 0.
At the same time, the field effect transistor 102 is also turned off. The gate voltage of the field effect transistor 101 is
5, the switch 112
Even when the load 113 is turned off, the voltage applied to the load 113 is maintained at zero. These are explanations of the memory function of the drive device of the present invention.

Next, the output short circuit protection function will be explained. In the description of the memory function, a state in which a voltage is applied to the load 113 is referred to as an initial state. When the output terminal 108 is shorted to the ground terminal 106, the resistor 104 limits the current, so the output terminal 108
is protected. Further, if the output terminal 108 is short-circuited with the power supply terminal 107 and the output terminal 108 becomes lower than the threshold '1 of the field effect transistor 102, the field effect transistor 102 is turned off and no current flows through the resistor 103. Transistor 101 is turned off and output terminal 10B is protected.

FIG. 2 is a circuit diagram showing an embodiment of the driving device of the present invention configured with multiple outputs. It is composed of an analog multiplexer 201 and a drive circuit array 202. Analog multiplexer 201 has data input/output terminal 211
．． Address input terminal 215 (including a non-selected state).

) has a multiplex output terminal 212. The drive circuit array 202 includes a plurality of circuits shown in FIG. 1, and input terminals 213. In the embodiment of FIG. 2 having a plurality of output terminals 214, there are write mode, read mode,
It has three types of operation modes: standby mode.

In the standby mode, an address 1 indicating non-selection is input to the address input terminal 215. Data input/output terminal 211 and multiplex output terminal 212 are not connected at all, and the output state of drive circuit array 202 remains unchanged.

In the write mode, an arbitrary address is input to the address input terminal 215. Data input to the data input/output terminal 211 is output to an arbitrary multiplex output terminal 212 via the analog multiplexer 201 to change the output state of the drive circuit array 202. The number of multiplex output terminals 212 selected is arbitrary.

In the read mode, an arbitrary address is input to the address input terminal 215. An input terminal 215 is connected from the data input/output terminal 211 to an arbitrary multiplex output terminal 212 via the analog multiplexer 201.
The status of is output. When the drive circuit array 202 is in a holding state, the state of the output terminal 214 is displayed as an inverted logic on the input terminal 213, so by reading it, you can find out the held state and compare it with the written data. It is also possible to detect whether the output short-circuit protection function has been activated. Note that the number of multiplex output terminals 212 selected is one.

〔Effect of the invention〕

As described above, according to the present invention, complementary type first and second
memory function by connecting field effect transistors together in a positive feedback manner.

This has the effect of providing a simple drive device with an output short-circuit protection function.

The present invention is particularly effective as an output circuit of a monolithic integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the driving device of the present invention. FIG. 2 is a circuit diagram showing another embodiment of the driving device of the present invention. 101, 102... Field effect transistor 1, 3, 104... Resistor 105... Input terminal 106... Ground terminal 107... Power supply terminal 108...Output terminal 111.112...Switch 113...Load 114...Power supply 201
...Analog multiplexer 202
...Drive circuit array 211 ...
...Data input/output terminal 212 ...Multiplex output terminal 213 ...Input terminal 214 ...Output terminal 215 ...Address input terminal and above Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Mogami (1 other person) No.D1 Arm 1 Wing - Lambda Sword 1F Runcies Up
z z/+11*hW ) run; X jFigure 1Figure 2

Claims (1)

[Claims] The first field effect transistor has a second field effect transistor complementary to the first field effect transistor, and the output of the first field effect transistor is transmitted to the first field effect transistor through the second field effect transistor. A drive device characterized in that positive feedback is provided to the input of a field effect transistor.