JPH0118443B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an engine control method, and more specifically to an automobile engine control method using a microcomputer. Recently, comprehensive control of engines using microcomputers is being carried out for the purpose of improving engine control functions. In order to provide a highly accurate control function to an engine control system using a microcomputer, a large number of software interrupt processing programs, especially interval interrupt processing programs that are executed at regular intervals, are required. As a result, the time occupied by the central processing unit (hereinafter referred to as CPU) by the management program (OS) that manages various control programs (hereinafter referred to as tasks) started by interval interrupts increases. do. (Refer to Japanese Patent Application Laid-Open No. 146034/1983). An object of the present invention is to provide an engine control method that can shorten the management time required to manage the activation of tasks. A feature of the present invention is that the engine control system manages the startup cycle of a task group, sets a startup request flag when the startup cycle is reached, and uses this flag to execute the task of the startup cycle. This is done by setting the number of executions of the task with a shorter startup cycle.
This significantly reduces the time required for activation management for tasks with long activation cycles, increasing processing efficiency. Hereinafter, the present invention will be explained in detail based on embodiments shown in the drawings. FIG. 1 shows a control device for the entire engine system. In the figure, intake air passes through an air cleaner 2, a throttle chamber 4, an intake pipe 6, and is supplied to a cylinder 8. The gas burned in the cylinder 8 passes through the exhaust pipe 10 from the cylinder 8 and is discharged into the atmosphere. The throttle chamber 4 is provided with an injector 12 for injecting fuel, and the fuel injected from the injector 12 is atomized within the air passage of the throttle chamber 4 and mixed with intake air. A mixture is formed, and this mixture is supplied to the combustion chamber of the cylinder 8 through the intake pipe 6 when the intake valve 20 is opened. A throttle valve 14 is located near the outlet of the injector 12.
16 are provided. The throttle valve 14 is configured to be in mechanical communication with the accelerator pedal and is driven by the driver. On the other hand, the throttle valve 16 is arranged so as to be driven by the diaphragm 18, and is fully closed when the air flow rate is small.As the air flow rate increases, the negative pressure on the diaphragm 18 increases, so that the throttle valve 16 It begins to open and suppresses the increase in inhalation resistance. An air passage 22 is provided upstream of the throttle valves 14 and 16 of the throttle chamber 4.
2 is an electric heating element 2 that constitutes a thermal air flow meter.
4 is disposed, and an electric signal that changes depending on the air flow rate determined from the relationship between the air flow rate and the amount of heat transfer of the heating element is extracted. Since the heating element 24 is provided within the air passage 22, it is protected from high-temperature gas generated when the cylinder 8 backfires, and is also protected from being contaminated by dust in the intake air. The outlet of the air passage 22 is opened near the narrowest part of the bench lily, and the inlet thereof is opened on the upstream side of the bench lily. Fuel supplied to the injector 12 is supplied from a fuel tank 30 to a fuel pressure regulator 38 via a fuel pump 32, a fuel damper 34, and a filter 36. On the other hand, pressurized fuel is supplied from the fuel pressure regulator 38 to the injector 12 via a pipe 40.
From the fuel pressure regulator 38 to the fuel tank 3 so that the difference between the pressure in the intake pipe 6 where fuel is injected from the fuel tank 3 and the fuel pressure to the injector 12 is always constant.
Fuel is returned to zero via a return pipe 42. The air-fuel mixture taken in from the intake valve 20 is transferred to the piston 5.
0 and is combusted by a spark from the ignition plug 52, and this combustion is converted into kinetic energy. The cylinder 8 is cooled by cooling water 54, and the temperature of this cooling water is measured by a water temperature sensor 56, and this measured value is used as the engine temperature. A high voltage is supplied to the spark plug 52 from an ignition coil 58 in accordance with the ignition timing. Further, the crankshaft (not shown) is provided with a crank angle sensor that outputs a reference angle signal and a position signal at every reference crank angle and every fixed angle (for example, 0.5 degrees) according to the rotation of the engine. The output of this crank angle sensor, water temperature sensor 56
The output 56A and the electrical signal from the heating element 24 are input to a control circuit 64 consisting of a microcomputer, etc., and are processed by the control circuit 64, and the injector 12 and the ignition coil 58 are driven by the output of this control circuit 64. Ru. In the engine system controlled based on the above configuration, the throttle chamber 4 is provided with a bypass 26 that straddles the throttle valve 16 and communicates with the intake pipe 6, and this bypass 26 has a bypass valve that is controlled to open and close. 62 are provided. A control input from the control circuit 64 is supplied to the driving section of the bypass valve 62, so that opening and closing of the bypass valve 62 is controlled. This bypass valve 62 faces the bypass 26 provided bypassing the throttle valve 16, and is controlled to open and close by pulsed current. This bypass valve 62 changes the cross-sectional area of the bypass 26 by the amount of lift of the valve, and this amount of lift is controlled by driving a drive system by the output of a control circuit 64. That is, in the control circuit 64, an opening/closing cycle signal is generated to control the drive system, and the drive system uses this opening/closing cycle signal to send a control signal to the bypass valve 64 for adjusting the lift amount of the bypass valve 64.
This is applied to the second drive unit. FIG. 2 is an explanatory diagram of the ignition device of FIG. 1, in which a pulse current is supplied to a power transistor 72 via an amplifier 68, and the transistor 72 is turned on by this current. As a result, a primary coil current flows from the battery 66 to the ignition coil 68. The fall of this pulse current turns the transistor 74 into a cut-off state, and generates a high voltage in the secondary coil of the ignition coil 58. This high voltage is distributed via the power distributor 70 to each of the spark plugs 52 in each cylinder of the engine in synchronization with the engine rotation. FIG. 3 is for explaining an exhaust gas recirculation (hereinafter referred to as EGR) system, in which constant negative pressure from a negative pressure source 80 is applied to a control valve 86 via a pressure control valve 84. The pressure control valve 84 is applied to the transistor 90 and controls the ratio of the constant negative pressure of the negative pressure source being released to the atmosphere 88 according to the ON duty ratio of the repetitive pulse, and controls the state of application of negative pressure to the control valve 86. do. Therefore, the negative pressure applied to the control valve 86 is determined by the ON duty ratio of the transistor 90. The controlled negative pressure of the constant pressure valve 84 controls the amount of EGR flowing from the exhaust pipe 10 to the intake pipe 6. FIG. 4 is an overall configuration diagram of the control system.
CPU 102 and read-only memory 104
(hereinafter referred to as ROM), random access memory 106 (hereinafter referred to as RAM), and input/output circuit 1
It consists of 08. The above CPU 102 is
Using various programs stored in the ROM 104, input data from the input/output circuit 108 is operated, and the operation results are returned to the input/output circuit 108 again. The intermediate storage required for these operations is RAM.
106 is used. CPU102, ROM104,
Various types of data are exchanged between the RAM 106 and the input/output circuit 108 via a bus line 110 consisting of a data bus, a control bus, and an address bus. The input/output circuit 108 includes a first analog-to-digital converter (hereinafter referred to as ADC1) and a second analog-to-digital converter (hereinafter referred to as ADC1).
analog to digital converter (hereinafter referred to as
ADC2) and angle signal processing circuits 126 and 1
It has an input means with a discrete input/output circuit (hereinafter referred to as DIO) for inputting and outputting bit information. ADC1 has a battery voltage detection sensor 132
(hereinafter referred to as VBS) and cooling water temperature sensor 56 (hereinafter referred to as VBS)
(hereinafter referred to as TWS) and atmospheric temperature sensor 112 (hereinafter referred to as TAS)
), the adjustment voltage generator 114 (hereinafter referred to as VRS), and the throttle angle sensor 116 (hereinafter referred to as θTHS)
The outputs of the λ sensor 118 (hereinafter referred to as λS) are applied to a multiplexer 120 (hereinafter referred to as MPX), and the MPX 120 selects one of them and converts it into an analog-to-digital conversion circuit 122 (hereinafter referred to as λS). (hereinafter referred to as ADC). ADC1
The digital value that is the output of 22 is stored in register 124.
(hereinafter referred to as REG). In addition, the flow rate sensor 24 (hereinafter referred to as AFS)
The signal is input to the ADC 2, converted into a digital signal via an analog-to-digital conversion circuit 128 (hereinafter referred to as ADC), and set in a register 130 (hereinafter referred to as REG). The angle center sensor 146 (hereinafter referred to as ANGS) outputs a signal indicating a reference crank angle, for example, 180 degrees crank angle (hereinafter referred to as REF), and a signal indicating a minute angle, for example, 1 degree crank angle (hereinafter referred to as POS). , added to the angle signal processing circuit 126,
The waveform is shaped here. DIO has an idle switch 148 (hereinafter
IDLE-SW), top gear switch 150 (hereinafter referred to as TOP-SW), and starter switch 152 (hereinafter referred to as START-SW) are input. Next, the pulse output circuit and control target based on the calculation results of the CPU will be explained. The injector control circuit (denoted as INJC) is a circuit that converts the digital value of the calculation result into a pulse output. Therefore, a pulse with a pulse width corresponding to the fuel injection amount is
It is generated by INJC 134 and applied to injector 12 via AND gate 136. The ignition pulse generation circuit 138 (hereinafter referred to as IGNC) has a register (hereinafter referred to as ADV) for setting the ignition timing and a register (hereinafter referred to as DWL) for setting the primary current energization start time of the ignition coil.
These data are set by the CPU. A pulse is generated based on the set data and is applied via AND gate 140 to amplifier 68, detailed in FIG. The opening rate of the bypass valve 62 is determined by the control circuit (hereinafter referred to as
ISCC) 142 via an AND gate 144.
ISCC142 is a register that sets the pulse width.
Register to set ISCD and repeat pulse period
Has ISCP. The EGR amount control pulse generation circuit 180 (hereinafter referred to as EGRC) that controls the transistor 90 that controls the EGR control valve 86 shown in FIG. 3 has a register that sets a value representing the duty of the pulse.
It has EGRD and a register EGRP for setting a value representing the pulse repetition period. This EGRC
The output pulse of is applied to transistor 90 via AND gate 156. Further, the 1-bit input/output signal is controlled by the circuit DIO. The input signal is IDLE-SW signal,
There is a TOP-SW signal and a START-SW signal. Further, the output signal includes a pulse output signal for driving the fuel pump. This DIO is provided with a register DDR for determining whether a terminal is used as an input terminal or an output terminal, and a register DOUT for latching output data. The register 160 is a register (hereinafter referred to as a register) that holds instructions for commanding various states inside the input/output circuit 108.
For example, by setting an instruction in this register, the AND gate 136,
140, 144, and 156 are all turned on or turned off. MOD like this
By setting the instruction in register 160,
You can control the stop and start of INJC, IGNC, and ISCC output. FIG. 5 is a diagram showing the basic configuration of a program system for the control circuit shown in FIG. 4. In the figure, an initial processing program 202,
The interrupt processing program 206, macro processing program 228, and task dispatcher 208 are management programs for managing task groups.
The initial processing program 202 is a program for performing preprocessing for operating the microcomputer, such as clearing the memory contents of the RAM 106, setting initial values of registers of the input/output interface circuit 108, and further processing. performs processing to take in input information such as cooling water temperature Tw, battery voltage, etc. for preprocessing necessary for engine control. In addition, the interrupt processing program 206 accepts various interrupts, analyzes the cause of the interrupt, sets a startup request for starting a necessary task among the task groups 210 to 226 in the task control table, and Submit to dispatcher 208. Interrupt factors include an AD conversion interrupt (ADC) that occurs after AD conversion of input information such as power supply voltage and cooling water temperature, an initial interrupt (INTL) that occurs in synchronization with engine rotation, and a set constant There are interval interrupts (INTV) that occur every 10 ms, for example, and engine stall interrupts (ENST) that occur when the engine is stopped. Each task in the task groups 210 to 226 is assigned a task number representing a priority order, and each task belongs to one of task levels 0 to 2. That is, tasks 0 to 2 belong to task level 0, tasks 3 to 5 belong to task level 1, and tasks 6 to 8 belong to task level 2. The task dispatcher 208 receives startup requests based on the various interrupts and performs processing based on priorities assigned to various tasks corresponding to these startup requests.
Allocate CPU occupancy time. Here, task priority control by the task dispatcher 208 is based on the following method. (1) A task with a lower priority is suspended and the execution right is transferred to a task with a higher priority only between task levels. It is assumed here that level 0 has the highest priority.
(2) If there is a task currently being executed or suspended within the same task level, this task has the highest priority and other tasks cannot operate until this task is completed. (3) If there are activation requests for multiple tasks within the same task level, the smaller the task number, the higher the priority. The processing content of the task dispatcher 208 will be described later, but in one embodiment of the present invention, processing is performed on a task-by-task basis in order to perform the above-mentioned priority control.
The configuration is such that a task control table is provided in RAM. Each time the execution of each task is completed, a report of the completion of the task is sent to the macro processing program 228 and recorded in the task control table. Next, the processing contents of the task dispatcher 208 will be explained based on FIGS. 6 to 9. 6th
The figure is managed by the task dispatcher 208.
Shows the task control table provided in RAM.
This task control table is provided with blocks corresponding to task levels, and in this embodiment there are three sets of task levels 0 to 2. Eight bits are assigned to each block, of which the 0th to 2nd bits (Q ₀ to Q ₂ ) are activation bits that display the activation request task, and the 7th bit (R) is the activation bit that displays the activation request task. Represents an execution bit indicating which task is currently suspended (including execution). And the activation bit Q ₀ to
Q ₂ are arranged in descending order of execution priority within each task level. For example, in Figure 5, the activation bit corresponding to task 4 is the activation bit of task level 1.
Q is ₀ . When a request to start a task is received, a flag is set in the start bit corresponding to the task by the interrupt processing program, and the task dispatcher 208 sends the issued start request to the start bit corresponding to the higher level task in order. It searches, resets the flag corresponding to the issued activation request, sets flag 1 in the execution bit, and performs processing to activate the corresponding task. FIG. 7 shows a start address table provided in RAM 106 managed by task dispatcher 208. Start addresses SA0 to SA8 indicate the start addresses corresponding to each task 0 to 8 of the task groups 210 to 226 shown in FIG. 16 bits are allocated to each start address information, and these start address information are used by the task dispatcher 208 to start the corresponding task for which a start request has been made, as will be described later. Next, the processing flow of the task dispatcher will be explained with reference to FIGS. 8 and 9. In FIG. 8, when task dispatcher processing is started in step 300, it is determined in step 302 whether or not execution of a task belonging to task level 1 is being suspended. At the start, l=0, and the search starts from level zero. If the execution bit (R0 bit in FIG. 6) is set to 1, the macro processing program 228 still sends a task completion report to the task dispatcher 20.
This means that the program that has not been issued at level 8 is in a level zero task, and the execution of this task has been suspended. In other words, this indicates a state in which the currently executing task has been interrupted due to the occurrence of an interrupt with a higher priority level. Therefore, if flag 1 is set in the execution bit (R0), the process jumps from step 302 to 314 and restarts the suspended task. On the other hand, if flag 1 is not set in the execution bit (R0), that is, if the execution display flag has been reset, the process moves to step 304, and level l=
It is determined whether or not there is a task waiting to be started among the tasks numbered zero. That is, the activation bits at level l=0 are sorted in order of the execution priority of the corresponding tasks, that is, Q ₀ ,
Search in the order of Q ₁ and Q ₂ . If flag 1 is not set in the activation bit belonging to task level 1, the process moves to step 306, and the task level is updated from a high level to a low level. That is, task level l=0 is incremented by +1 and l+1→
Let it be l. When the task level is updated in step 306, the process moves to step 308, where it is determined whether all task levels have been checked. All levels are not checked,
That is, if l=3 is not the case, the process returns to step 302 and the process is performed in the same manner as described above. Step 3
If all task levels have been checked in step 08, the process moves to step 310, where the interrupt is canceled. That is, since interrupts are prohibited during the processing period from step 302 to step 308, the interrupt is canceled at this step. Then, in the next step 312, the next interrupt is waited for. A background task may be performed in step 312. Next, in step 304, if there is a task waiting to be activated at task level l, that is, if the flag 1 is set in the activation bit belonging to task level l, the process moves to step 400 in FIG. In a loop of steps 400 and 402, a search is made to find out which activation bit of task level l is flagged as 1. First, the relative task number m is set to zero so that the search is performed in the order of the corresponding priority execution levels, that is, in the order of Q ₀ , Q ₁ , and Q ₂ . At step 401
Determine whether Qm=1. Also, in step 402, m is incremented to move to the next task number. After determining the relevant boot bit, proceed to step 4.
In step 404, the start bit with the flag set is reset, and a flag 1 is set in the execution bit (hereinafter referred to as the R bit) of the corresponding task level. Furthermore, in step 406, the activation task number is determined from the level l and the relative task number m using the formula n=l×3+m, and step 408
Specify the absolute address of the ROM from this task number n (this address will be the storage address of the start address table).
The start address information of the corresponding startup task is extracted from the start address table provided in the start address table. Next, in step 410, a determination is made as to whether or not to execute the corresponding startup task. Here, if the extracted start address information is a specific value, for example 0, it is determined that the corresponding task does not need to be executed. This determination step is necessary to selectively provide the function of only a specific task for each vehicle type among the task group for controlling the engine. If it is determined in step 410 that the execution of the corresponding task is stopped, the process moves to step 414, and the R bit of the corresponding task level 1 is reset. Then, the process returns to step 302 and it is determined whether or not there is a task in task level l that has issued a start request. Since there may be cases in which a plurality of activation bits are flagged during the same task level, the R bit is reset in step 414 and then the process proceeds to step 302. On the other hand, if execution of the relevant task is not stopped in step 410, that is, if it is to be executed, the process moves to step 412, jumps to the relevant task, and executes the task. Next, FIG. 10 is a diagram showing the processing flow of the macro processing program 228. This program uses steps 562 and 56 to find the termination mask.
Consists of 4. In steps 562 and 564, the task level is first searched from 0 to find the completed task level. As a result, the process advances to step 568, where the execution (RUN) flag in the 7th bit of the task control block of the completed task is reset. This means that the task has completed execution. And again Task Day Patschiya 2
Returning to step 08, the next task to be executed is determined. Next, FIG. 11 shows a specific embodiment of the program system shown in FIG. Management program in diagram
The OS includes an initial processing program 202, an interrupt processing program 206, and a task dispatcher 2.
08 and a mask processing program 228. The interrupt processing program 206 includes various interrupt processing programs, and the initial interrupt processing (hereinafter referred to as INTL interrupt processing) 602 uses an initial interrupt signal that is generated in synchronization with engine rotation to interrupt half of the number of engine cylinders per engine rotation. That is, if it is a 4-cylinder engine, the initial interrupt will occur twice. By this initial interrupt, the fuel injection time calculated by the FGI task 612 is set in the INJD register of the input/output interface circuit 108. There are two types of AD conversion interrupt processing 604, one is AD converter 1 interrupt (hereinafter abbreviated as ADC1).
and AD converter 2 interrupt (hereinafter abbreviated as ADC2). The AD converter 1 has 8-bit accuracy and is used for inputting power supply voltage, cooling water temperature, intake air temperature, usage adjustment, etc., and starts conversion at the same time as specifying the input point to the multiplexer 120. Generates ADC1 interrupt after completion.
Note that this interrupt is used only before cranking.
Further, the AD converter 128 is used to input the air flow rate and generates an ADC2 interrupt after the conversion is completed. In addition,
This interrupt is also used only before cranking. Next, the interval interrupt processing program (below
It is referred to as INTV interrupt processing program. ) 606, the INTV interrupt signal is generated every 10 ms, for example, according to the time set in the INTV register, and is used as a basic signal for time monitoring of tasks to be started at regular intervals. This interrupt signal updates the soft timer and activates the task that has reached the specified period.
In addition, the engine stall interrupt processing program (hereinafter referred to as ENST)
This is called an interrupt processing program. ) 608 detects the stop state of the engine. When an INTL interrupt signal is detected, counting is started, and when the next INTL interrupt signal cannot be detected within a predetermined period of time, for example, 1 second, an ENST interrupt is generated. For example 1
If the INTL interrupt signal is not detected even after seconds have passed, it is determined that an engine stall has occurred, and the ignition coil is energized and the fuel pump is stopped. After these processes, the process waits until the starter switch 152 is turned on. Table 1 shows an overview of the processing for the above interrupt factors.

[Table] The initial processing program 202 and macro processing program 228 perform the processing as described. The task groups activated by the various interrupts mentioned above are as follows. Tasks belonging to task level 0 include an AD2 input task (hereinafter referred to as ADIN2 task), a fuel injection control task (hereinafter referred to as EGI task), and a start monitor task (hereinafter referred to as MONIT task). Also, tasks that belong to task level 1 are AD1 input task (hereinafter referred to as ADIN1 task) and time coefficient processing task (hereinafter referred to as AFSI task).
There is. Furthermore, tasks belonging to task level 2 include an idle rotation control task (hereinafter referred to as ISC task), a correction calculation task (hereinafter referred to as HOSEI task), and a start preprocessing task (hereinafter referred to as ISTRT task). Table 2 shows the assignment of each task level and the function of the task.

【table】

[Table] As is clear from Table 2, the activation cycle of each task activated by various interrupts is determined in advance, and this information is stored in the ROM 104. Next, based on FIGS. 12 and 13, a case will be described in which an INTV interrupt is activated without using the soft timer table shown in FIG. 11. FIG. 12 shows a soft timer flag provided in the RAM 106. Each of the soft timer flags is set to manage a group of tasks so that they are activated at approximately constant intervals. In some cases, the number of bits may be equal to the number of different activation cycles among the activation cycles. Bits (hereinafter referred to as flag bits), for example F1~
Assume that it is composed of 8 bits of F8. Each flag bit is, for example, 10 m sec for flag bit F1, 20 m sec for F2, and 40 m sec for F3.
sec, ..., F8 is associated with 1280 m sec and the activation cycle of the multiple series. These activation cycles can be arbitrarily changed as long as they are numerical values in multiple series. Now, Tables 3 and 4 show examples of the relationship between task groups that are activated at regular intervals and their activation cycles.

【table】

[Table] When the relationship between activated tasks and activation cycles is shown in Table 1, flag bits F1 to F6 of the soft timer flag correspond to tasks 1 to 6. In addition, in the case of Table 2, the flag bits F1, F2
correspond to tasks 1 and 2, respectively, flag bit F3 to tasks 3, 4, and 5, flag bit F4 to tasks 6 and 7, and flag bits F5 and F6 to tasks 8 and 9, respectively. In this embodiment, a task corresponding to the minimum startup cycle (hereinafter referred to as the minimum startup cycle) among the different startup cycles, that is, task 0, which is started every 10 m sec in this embodiment, is started by an interval interrupt, Upon activation of the task, other tasks are activated in sequence at a multiple series activation cycle based on the determination result of the soft timer flag. The contents of the above processing will be explained based on the processing flow shown in FIG. The processing flow in the figure shows an example where task 2 is started by starting task 1, but the same applies to other cases, such as when task 2 starts task 3 (however, in the case of Table 1 (The case in Table 2 will be described later.) In the figure, when task 1 is activated by an interval interrupt in step 700, it is determined in the next step 702 whether flag bit F1 of the soft timer flag STF is 1 or not. Here, in the soft timer flag SFT, the flag bit corresponding to the activation cycle of the task to be activated is set to "1", and the flag bit corresponding to the activation cycle of the task that is not activated is in the state of "0". shall be. Now, in step 702, set the soft timer flag.
If it is determined that the flag bit F1 of the SFT is "1", the process moves to step 704, sets the flag bit F1 to "0", and checks again in the next step 708 whether or not the flag bit F1 is "1". A determination is made. Flag bit F1 has already been set to “0” in step 704.
Therefore, in step 708, it is determined that flag bit F1 is not "1", and the process moves to the next step 712, where the original processing of task 1 is performed, and in step 714, task 1 ends. On the other hand, when task 1 is started at step 700 in the next cycle, the soft timer flag has already been set.
As mentioned above, the flag bit F1 of the SFT is set to "0" in step 704, so it is not set in step 702.
Then flag bit F1 is determined to be “0”,
The process moves to step 706. In step 706, flag bit F1 is set to “1”.
and moves to step 708. Step 70
In step 8, it is determined again whether flag bit F1 is "1", and since flag bit F1 has already been set to "1" in step 706, step 71 is executed.
Transition to 0. Step 710 starts task 2 (sets the Q flag corresponding to task 2 in FIG. 6 to 1),
The process moves to step 712 to perform the original processing of task 1, and then ends task 1 in step 714. As described above, steps 704 and 706 complete one cycle (in this case, 20 m sec, which is the startup cycle of task 1).
The flag bit F1 alternately repeats the state of “1” and “0” for each task, and when task 1 starts, the flag bit F1
When F1 is "0", that is, task 2 is activated at twice the activation period of task 1. Therefore, when starting tasks 1 to 6 in sequence as shown in Table 1 above, steps 702 to 702 are placed at the beginning or end of tasks 1 to 5.
This becomes possible by inserting a program consisting of 12 bits (provided that the flag bits to be determined by the soft timer flag are replaced with F2 to F5, respectively). Next, in the case of Table 2, tasks 1, 2, 3, 6,
For steps 8 and 9, follow steps 702 to 71 described above.
By inserting a program consisting of 2 into each task, tasks 4 and 5 are started sequentially at a multiple series start cycle, but tasks 4 and 5 have the same start cycle as task 3.
As for task 7, which has the same startup cycle as task 6, the task dispatcher 208
Tasks 4, 5, and 7 are activated by setting flags 1 in activation bits corresponding to tasks 4, 5, and 7 in the task control block provided in the RAM 106 managed by the task controller. According to this embodiment, as many soft timer blocks with different activation cycles as shown in FIG. 11 are used.
Since it is no longer necessary to provide it in RAM, it becomes possible to allocate that amount to other controls. FIG. 14 is an additional flowchart of the interrupt processing program 206 and task dispatcher of FIG. 5 or FIG. 11. In step 89, the interrupt processing program 206 determines that it is INTVIRQ.
If it is determined to be 0, the process advances to step 892 and the Q0 bit of level ₀ is set to 1. This will cause task 0
This means that the startup request for ADIN2 in Table 2 has been registered. Next, proceed to 208 of Task Day Spa. Step 894 represents steps up to step 410 of FIGS. 8 and 9, and the operation is as described above. If YES is determined in step 410 of FIG. 9, the process advances to step 896. This step 8
96 to 910 are software for updating the soft timer counter shown in FIG. Step 8
At step 96, it is determined whether the task serves as a clock for updating the soft timer. In the case of Table 3, tasks 0~
4 becomes YES in step 896. On the other hand, in the case of Table 4, tasks 0, 1, 2, 5, and 7 are YES, and the others are NO. At step 896, F1
~Determine n of Fn of F8. In Table 3, when task 0, n=1, and an update judgment is made for F1.
In step 902, as shown in 702 in FIG.
Determine whether or not is 1. If YES, F1, which is Fn, is set to zero in step 904; on the other hand, if NO, F1, which is Fn, is set to 1 in step 906. When F1, which is Fn, becomes 1, step 910
Then, the Q of the corresponding task is set to 1, and a start request is registered. In this example, it is Q that corresponds to task 1 in Table 3. In this way, a startup request is issued, and execution proceeds to step 411 in FIG. Next, the IRQ generation circuit is shown in FIG. A register 735, a counter 736, a comparator 737, and a flip-flop 738 are an INTVIRQ generation circuit, and the INTVIRQ generation period is set in the register 735, for example, 10 [ms] in this embodiment. In response, a clock pulse is set to counter 736, and when the count value matches register 735, flip-flop 738 is set.
In this set state, the counter 736 is cleared and counting is restarted. Therefore, for a certain period of time (10m
INTVIRQ occurs every sec). Register 741, counter 742, and comparator 74
3. A flip-flop 744 is an ENSTIRQ generation circuit that detects engine stoppage. Register 741, counter 742, and comparator 743 are similar to those described above, and when the count value reaches the value of register 741, ENSTIRQ is generated. However, while the engine is rotating, the REF pulse generated by the crank angle sensor at a certain crank angle causes the counter 7 to
42 is cleared, so the count value of counter 742 does not reach the value of register 741.
ENSTIRQ does not occur. INTVIRQ occurred on flip-flop 738
ENSTIRQ occurred on flip-flop 744.
Furthermore, the IRQs generated by ADC1 and ADC2 are flip-flops 740, 746, 764, and 76, respectively.
It is set to 8. Also, flip-flop 73
7, 745, 762, and 766 are set with signals indicating whether to generate or inhibit IRQ. If flip-flops 737, 745, 762, and 766 are set to "H", AND gate 748,
750, 770, and 772 become active, and when an IRQ is generated, an IRQ is generated immediately from the OR gate. Therefore, flip-flops 737, 745, 76
Depending on whether "H" or "L" is input to each of 2,766, generation of IRQ can be inhibited or inhibited. Furthermore, when an IRQ occurs, the cause of the IRQ can be determined by loading the contents of flip-flops 740, 746, 764, and 768 into the CPU. When the CPU starts executing a program according to the IRQ, the IRQ signal needs to be cleared, so the flip-flop 7 related to the IRQ that started execution
Clear one of 40,746,764,768. Although the above-described embodiments of the present invention have been explained with respect to engine control of an automobile, the present invention is not limited to this and is of course applicable to other types of computer control. As described above, since the present invention is configured so that the interval interrupt processing to be performed by the management program is divided among tasks, the time required for the interrupt processing handled by the management program is reduced, and the interrupt processing performance is improved. Controllability can be improved. FIG. 16 shows another embodiment of the present invention, in which a determination is made in step 890 as to whether it is INTVIRQ.
This step is similar to step 890 in FIG. In step 920, n of Fn is set to 1.
In other words, it is decided to set Fn to F1 and to perform processing on F1. In step 922, the contents of FIG. 13 are checked for F1. If the previous state is F1=1, step 926 sets F1=0, and if F1=0, step 924 sets F1=1. At step 928, it is determined whether n=8. In other words, it is determined whether the processing for all the bits of the soft timer counter shown in FIG. 12 has been completed. In this case, since n=1, the answer is NO, and in step 930 it is determined that n=2. In other words, the next bit of F2 will be processed.
Similarly, when n=8, it means that all bits have been processed, and the updating of the soft timer counter in FIG. 12 is completed. Next, in steps 934 to 942, a start request for each task is registered based on the soft timer counter. First, in step 932, INTVIRQ
occurs every 10m sec, so the startup cycle is 10m
Set the Q of all tasks in sec to 1. Step 93
By setting n=1 in step 4, the processing of F1 is started. It is determined in step 936 whether the F1 bit in FIG. 12 is 1. If F1=1, the process advances to step 938. In this step, the activation request flag Q for all tasks corresponding to the F1 bit of the soft timer counter is set to 1. The process then proceeds to step 940. On the other hand, if NO in step 936, the process directly advances to step 940. At step 940
Determine whether n=8 of Fn. In this case n
= 1, so the judgment is NO. Step 942
Then, n=1 is updated to n=2. This results in F2 processing. Similarly, if you proceed to the process of F8, the judgment in step 940 will be YES and the 16th step will be YES.
The flow in the figure ends. This flow is interrupt processing 2
This is INTVIRQ processing of 06. Processing proceeds from step 940 to the task dispatcher. In the process of FIG. 16, steps 410 and 41 of FIG.
1 is not necessary, and in step 410
If YES, the process immediately proceeds to step 411.

[Brief explanation of drawings]

Figure 1 is a configuration diagram showing the control device for the entire engine system, Figure 2 is an explanatory diagram of the ignition system in Figure 1, and Figure 3 is an explanatory diagram of the ignition system in Figure 1.
FIG. 4 is a block diagram for explaining the exhaust gas recirculation system, FIG. 4 is an overall block diagram of the engine control system, FIG. 5 is a diagram showing the basic structure of the program system for the engine control method according to the present invention, and FIG.
The figure shows the table of task control blocks provided in the RAM managed by the task dispatcher, Figure 7 shows the start address table of task groups activated by various interrupts, and Figures 8 and 9 show the table of task control blocks provided in the RAM managed by the task dispatcher. Figure 10 shows the processing flow of the task dispatcher, Figure 10 shows the processing flow of the macro processing program, Figure 11 shows the software system diagram, Figure 12 shows the software timer counter, and Figure 13 shows the processing flow of INTVIRQ. , FIG. 14 is a process flow diagram for updating the soft timer counter and registering a start request, FIG. 15 is a diagram of an interrupt generation circuit, and FIG. 16 is a flow diagram showing another embodiment of the present invention. 102...CPU, 104...ROM, 106...
...RAM, 108...Input/output circuit.

Claims (1)

[Claims] 1 Various sensors that detect the operating state of the engine, an arithmetic circuit that digitally processes output signals from the sensor, storage means that stores a program for operating the arithmetic circuit, and engine control based on the arithmetic results of the arithmetic circuit. It consists of a control mechanism that performs
The program is classified based on its control function, a startup cycle is set for each classified task group according to its influence on the engine, and a startup request is issued to each task based on the set cycle. , the activation period is 2 n of the minimum activation period.
Set so that the relationship is multiplied by (n = 0, 1, 2...), measure the minimum activation period among the activation periods using an interval interrupt, and perform tasks according to this minimum activation period. A method for controlling an engine, characterized in that a longer startup cycle is measured based on the number of executions of , and an even longer startup cycle is measured based on the number of times a task is executed according to the measured startup cycle. .