JPH01183853A - Thin-film filed-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a short-circuit between a metallic layer, and n<+>a-Si by anodizing the exposed section of a metal after patterning. CONSTITUTION:An amorphous silicon thin-film 11 is formed onto an insulating substrate 1, and a gate insulating film 12, a metallic layer capable of being anodized as a gate electrode 13 and a protective insulating film 14 are laminated and formed in succession. Laminated layers are removed through etching while being left only in a gate formation predetermined region, and the side face of the gate-electrode metallic layer exposed through etching is anodized. Accordingly, since an oxide film 23 is shaped onto the surface, the anodizing film 23 can block a short circuit even when a metal and n<+>a-Si are brought into contact, thus preventing the short circuit between the metal and n<+>a-Si.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a thin film field effect transistor and a method for manufacturing the same.

(Prior Art) Active matrix liquid crystal display devices are seen as a promising means of realizing large-area, 9-item, high-definition, high-quality, and inexpensive panel displays, but their switching elements are made of amorphous (α silicon) A-5i) A thin film transistor (TPT) using a film is used.

FIG. 4 shows the specific structure of a conventional TPT. A wiring pattern 2 serving as an address line and a gate is formed on a glass substrate 1, and a gate insulating film 3. a-3i layer 4, n”a
-5i layer 5 is deposited to form islands of a-si WJ. Next, after forming the pixel electrode, the source/drain electrode 6S,
Wiring to become 6D and data lines is formed.

As this type of display becomes larger and has higher definition,
The number of transistors increases significantly, making it difficult to manufacture them without defects. In addition, the SF fineness of the display has improved,
When the required precision of mask alignment increases, the fourth
This cannot be done with the reverse staggered type shown in the figure. On the other hand, by using a coplanar type as shown in FIG. 3 and creating a self-line structure, almost perfect alignment accuracy can be achieved. However, when using a coplanar thin film transistor, the gate metal +P23 and the n+a-3i layer 25s
.

A defect in which the 25D is shorted on the side surface of the gate insulating film 22 may occur. Therefore, it has been extremely difficult to form all transistors without defects.

In FIG. 3, 21 is an a-5i layer, 22 is a gate insulating IL, 23 is a gate metal, 25S is a source n''a-3i layer 5, and 250 is a drain n+a-SiM layer.
, 26 is an S-preserving insulating film, 27G is a gate electrode, 27S is a source electrode, and 27D is a drain electrode. In addition, in FIG. 4, 2 is the wiring pattern of the gate electrode, 3 is the gate insulating film, 4 is the a-3i layer, 5 is the n0a-3i layer,
6S indicates a source electrode, and 6D indicates a drain electrode.

(Problems to be Solved by the Invention) As described above, in a coplanar TPT, a metal layer and an
It was difficult to eliminate the seams between a and 3i.

The present invention provides a metal layer and n”a in coplanar TPT.
The purpose is to eliminate short circuit between -5i.

[Structure of the invention]

(Means for Solving the Problems) A first aspect of the present invention is that a thin film field effect transistor includes an amorphous silicon thin film formed on an insulating substrate and having n0 layers, and a part of this amorphous silicon thin film. A gate insulating film formed as a VL layer in sequence on the upper surface of the gate electrode formation area adjacent to the n+ layer, a gate electrode whose side surfaces are anodized, and a gate wiring layer, and on the n+ layer. The gate electrode metal layer is formed of Ta and T.
It is characterized by being an alloy containing a. Next, the manufacturing method includes a step of forming an amorphous silicon thin film on an insulating substrate, a gate insulating film, and a metal layer that can be anodized to become a gate electrode on the amorphous silicon thin film.

and a step of sequentially laminating and forming a protective insulating film, a step of removing the laminated layer by etching using the same etching mask leaving only the area where the gate is to be formed, and anodic oxidation on the side surfaces of the gate electrode metal layer exposed by the etching. The method includes a step of applying impurity doping to the exposed portion of the amorphous silicon thin film to form source and drain electrodes.
It is characterized by being formed by VD or sputtering.

(Function) After patterning, an oxide film is formed on the surface by anodic oxidation of the exposed parts of the metal.
Even if the a-5i contacts, the anodic oxide film can block the short-circuit, so that the short-circuit between the metal and the n''a-3i can be eliminated.

(Example) An example of the present invention will be described below with reference to FIG. 1 and FIG. 2.

The structure of the example thin film field effect transistor shown in FIG.
g layer 12. Goo 1 to Ta layer 13 of the electrode. S of protective insulating film
It has an iO layer 14, and the side surface of the Ta layer 13 is a tag 23 formed by anodizing. and,
This Ta layer 13 is provided with a gate electrode wiring layer 17G. Further, the n"a-5i layer 1 of each source and drain region is formed on a part of the 5inX layer 12.
55. Source electrode 17S and drain electrode 170 at 15D
are formed respectively. j7, the entire surface except for the above-mentioned electrodes and the electrode wiring layer is covered with a protective insulating film 16.

Next, the thin film field effect transistor according to the present invention!
An example of the XI manufacturing method will be described with reference to No. 2134.

A-3i layer 30 is formed on the glass substrate 1 by plasma CVD.
00 people 11.5 iOxff 2000 people 12 is deposited, and a Ta layer is deposited by sputtering to 800 people 13.

2000 SiOx insulating films are deposited by plasma CVD (FIG. 1a).

Next, etching with diluted IIF (BHF) on the 5 inch) 4 layer 14 with the same pattern, TaW1
Chemical dry etching (CDE) for 13, S
The i0g layer 12 is sequentially etched with N114F (FIG. 1b). Next, anodization was performed in a 0.1% citric acid aqueous solution at 0.5 A/af to 120 V, and the Si
The side surface of the Ta layer 13 exposed from the Ox insulating film is
oy layer 23 (FIG. 1C). Next, the surface of the a-Si layer 11 is plasma-doped in PI (3 plasma) to form n-middle regions 15S and 150 of the source and drain regions, and then an SiO2 insulating film 16 is deposited by plasma CVD. , Drill a contact hole (Fig. 1d).

Next, a gate electrode wiring layer 17G and a gate electrode interconnection layer 17G are deposited by sputtering to a thickness of 1-1.

Form source and drain electrodes 175 and 170 (first
By means of figure e) the formation of a thin film field effect transistor is achieved.

In addition to the above embodiments, a Si/SiOx
If the TPT has the same structure of /TaO2/gates,
Similar effects can be obtained regardless of the structure of the source and drain. The anodic oxide film is not limited to Ta0y, but also AQ.
O□Tie is fine.

When Tie was not present, there was about 30% transistor error, but 2000 Ta layers were added, and after etching each layer of the insulating film - Ta - insulating film in the same pattern, anodization was performed to form the TaoX part. As a result, the number of defects was reduced to 0-1%, and a great effect was obtained.

〔Effect of the invention〕

As described above, according to the present invention, the number of short circuits that cause transistor failure can be reduced to almost zero, and the image quality of a display can be greatly improved, and the yield of products can be greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an embodiment according to the present invention, and FIG.
e is a cross-sectional view showing the manufacturing method of the present invention in order of steps;
FIG. 3 is a sectional view of a conventional coplanar TPT, and FIG. 4 is a sectional view of a conventional inverted staggered TPT. 1...Glass substrate 11...a-5i layer 12...5iflx layer (gate insulating film) 13.
...Ta layer (gate electrode) 23 ...Ta
Ox layer 14... Si00 layer (insulating tibia membrane) Agent Patent attorney Inoue - Rikitsutsu 1 Figure 2 (Shiba's ln Figure 2 (vsu 2) Figure 3 Figure 4

Claims (2)

[Claims] (1) An amorphous silicon thin film formed on an insulating substrate and having an n^+ layer, and a part of this amorphous silicon thin film on the upper surface of an area where a gate electrode is to be formed adjacent to the n^+ layer. A gate insulating film, a gate electrode and a gate wiring layer whose side surfaces are anodized, and the n^
+ A thin film field effect transistor comprising a source electrode and a drain electrode formed on an amorphous silicon layer. (2) Forming an amorphous silicon thin film on an insulating substrate, and sequentially laminating a gate insulating film, a metal layer that can be anodized to become a gate electrode, and a protective insulating film on the amorphous silicon thin film. a step of etching away the laminated layer using the same etching mask leaving only the region where the gate is to be formed; a step of anodizing the side surface of the gate electrode exposed by the etching; A method for manufacturing a thin film field effect transistor, comprising a step of doping an exposed portion of the transistor with an impurity to form source and drain electrodes.