JPH01181137A - Storage unit - Google Patents

Abstract

PURPOSE:To realize the high performance and the small capacity of a storage unit by adding a block reading/writing function and an interleaving function to the storage unit. CONSTITUTION:The read data 521 corresponding to the stored data 501.0 and 501.1 and the read data 522 corresponding to the stored data 502.0 and 502.1 are read out to a read data line 55 through a selection circuit 54 with the use of an interface clock 57 and a request command address signal 58. These read-out data is used as the read data 60. In this case, a high-speed access cycle 63 means the action modes including so-called nibble, page and static column modes, etc. In such a way, both a block transfer function and an interleaving function are secured by setting a data access unit opposite to a storage unit (bank).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to reading and writing to a storage device.

[Conventional technology]

Conventionally, reading and writing to this type of storage device was possible only by block transfer or only by interleaf? It was limited. In other words, it is limited to those that can write or read multiple data with one command and address specification, or those that have 11 banks that can be read and written independently and can interleaf these. Ta.

FIG. 3 is a block diagram showing such a conventional storage device capable of block transfer, and FIG. 4 is an operation timing diagram thereof.

In FIG. 3, the row direction corresponds to a data access unit 11, and n memory elements 16. ,,~162. . , 16□, 1~16°+h% 163+ 1~16321.16,,,~1
649 is provided. Each storage element e.g. 16
．． ,, are O to m storage units 16 in the column direction (word direction) 12. ,,. ~16. ．． ．． ”.

Memory element 16. ,,． 1629. ．． 163. , ． 1
6. , , storage unit 16, , ' , 162. ,
. , 163. , . , 16. ,, '2 is data 2
01. . , 20°. , 203. . , 20, , (bo, b l+ b 2, b 3 in the figure, respectively) are stored. The last storage unit 162 of the storage element in the column direction
19,! 6. , 7.163, 9.16. , from A: Corresponding to each, read data 2 in data access unit
31.232.233.234 are read from the read data line 26 through the selection circuit 25.

FIG. 4 (This is a timing diagram of the read operation of the above-mentioned conventional example.

An interface clock 29 (a in the figure), one request command, and an address signal 31 (b in the figure) are applied as shown. As a result, the successive data (c-f in FIG. 4) of the data (in FIG. 3) is selected by the selection circuit 25 (FIG. 3), and the successive data 35 (FIG. 3) is sent to the successive data line 26 (FIG. 3). It is output as g) in the figure.

[Problem to be solved by the invention]

However, such conventional storage devices have the following drawbacks. That is, in the case of a storage device capable of only block transfer, there is no performance problem in reading, but when writing, if the addresses are not consecutive, it must be executed one by one. In such a case,
The next write cycle can only be started once the previous write cycle has finished. However, such an operation has drawbacks such as a significant drop in execution efficiency and performance.

On the other hand, in a storage device capable of only interleafing, there is no drop in write performance for discontinuous addresses as described above. However, conversely, even when writing and reading consecutive addresses, each address must be generated one by one, which has the disadvantage of lowering execution efficiency.

This is especially noticeable in the case of a bus system. Furthermore, due to their nature, interleave-only storage devices typically have at least four banks (so-called 4-way interleaf) to increase performance. However, this method has the disadvantage that the basic storage capacity and the additional storage capacity become large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a storage device that has both block successive functions, a write function, and an interleaf function, and is capable of compensating for the drawbacks when each function is operated independently.

[Means to solve the problem]

The storage device of the present invention has a plurality of independent banks, each with addresses consecutive in the row direction, each consecutive with the address of the last one in each row, and each bank with one address in each row. Banks are arranged to correspond to one data access unit, and for these banks, by simply specifying the address of one bank, it is possible to support multiple data access units to multiple consecutive banks in the row direction by block transfer. The timing control unit provides a control signal by one command so as to enable writing or reading of data to be written or read, and also to enable sequential writing or reading of data in the banks in the column direction by interleaving.

Therefore, the storage device of the present invention has both a block succession function, a write function, and an increment function, and these functions complement each other except for the drawbacks when they function independently, so that it has high performance and Storage capacity can be reduced.

〔Example〕

The present invention will be described in detail below with reference to Examples.

FIG. 1 is a block diagram showing an embodiment of a storage device according to the present invention, and FIG. 2 is an example of its operation timing.

In FIG. 1, memory element: column direction (word direction) 1
2, n pieces are arranged in two columns in the row direction, and these are respectively written as
41. ,,~411. . , 41□, 1 to 41□9. Furthermore, each memory element is arranged in the column direction 12 from 0 to m.
storage units (banks) 41, . 0-41. ,,'″
, 41□+1° to 41□, 1''. Storage unit (bank) 4 of storage elements 410, 3.412.l
1. ,,. ,41□,11;41+,+'',4
12+1 ”+1 data access unit 4 in the row direction
6, and data 501.6 respectively. . , 50°. ;
5L, +, 50□, 1 (bo, b, ;l in the figure) 2
, b3) are stored. Read data 52+, 52□ of the data access unit 46 corresponding to each storage unit (bank) is read from the read data line 55 through the selection circuit 54. In addition, since the interleaf has two memory units (banks), it can be stored in a well-known manner.
Way interleaf is possible.

Next, the operation will be explained based on FIG.

An ink face clock 57 (a in the figure), a request command, and an address signal 58 (b in the figure) are applied as shown. As a result, the stored data 50. of FIG. ,, ,50
．． , , (bo, bz in the figure) successive data 52. (C in the figure) and similarly stored data 502.
. , 50□, + (Fig.

The successive data 52□ (d in the figure) corresponding to bs) is read out and becomes the successive data 60 (e in the figure).

Here, the high-speed access cycle (The in the figure) 53 is an operation mode such as a so-called nibble mode, page mode, or static column mode.

As described above, one data access unit is defined as a storage unit (
By making it compatible with banks), it is possible to have both block transfer function and interleaf function.

〔Effect of the invention〕

As described above, the storage device of the present invention has both block successive, write function, and interleaf function.
It can compensate for the shortcomings of both functions, and has high performance.
This has the effect of reducing the basic storage capacity and additional storage capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the storage device according to the present invention, FIG. 2 is a diagram showing the operation timing of the embodiment of FIG. 1, FIG. 3 is a block diagram showing a conventional example, and FIG. It is an operation timing diagram. 41,,, ', 41. ,, ' , 41□＋
l' + 412113... Memory unit (bank). Figure 2 Figure 4

Claims (1)

[Claims] A plurality of independent data access units arranged such that each address is consecutive in the row direction, the column direction is consecutive to the address of the last one in each row direction, and each row direction corresponds to one data access unit. Write data corresponding to multiple data access units to multiple consecutive row-direction banks for a certain column address of the bank by block transfer by simply specifying the address of one bank for these banks. or enable reading,
In addition, a timing control unit is provided which controls by giving a control signal based on one command so as to enable writing or reading to a certain address in the row direction to banks in the column direction sequentially by interleaving. Characteristic storage device.