JPH01165278A - Clock generating circuit for image memory - Google Patents

Abstract

PURPOSE:To make the circuit configuration of the title circuit simpler and, at the same time, to miniaturize the circuit by alternately supplying pixel clocks to a quartered memory depending upon the difference between the horizontal and vertical synchronizing signals and odd and even fields. CONSTITUTION:By controlling gates 10a-10d by means of the count results of counters 5 and 6 which are respectively reset by vertical and horizontal synchronizing signals and the 1/2 of the dot number in the horizontal direction and 1/4 of the dot number in the vertical direction, supply of pixel clocks to four video RAMs 11a-11d is switched. Therefore, the pixel clocks can be supplied to a total of four memories which are constituted in a quartered state depending upon the difference between the horizontal and vertical synchronizing signals and odd and even fields.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image memory clock generator for generating a serial clock, a so-called pixel clock, when storing a video signal in an image memory and reading it from the image memory. Regarding circuits.

[Conventional technology]

When dot data obtained by digitizing a video signal, that is, a television image signal, is stored in a memory and read out, it is necessary to use clocks corresponding to horizontal and vertical scanning lines.

For example, if one frame is composed of 512 dots x 512 dots, and each dot is 8-bit data, 512 dots of data are read from and written to the memory during the period of one horizontal scanning line. It is necessary to perform this for a total of 512 horizontal scanning lines, 256 horizontal scanning lines for each of the even and odd fields that make up one frame.

[Problem that the invention seeks to solve]

By the way, in the case of a color image, each dot of data has 1
The most common case is to use bytes, that is, 8 bits, but in this case, 512x 512x 8 pintos, that is, 2
,097,152 bits of memory are required. Therefore, in reality, 64kX4 focus memories are combined into two control groups to
Four sets of bit memories are prepared, and each of the four sets stores 256 x 256 dots in the first half and second half of one horizontal scanning line, and the upper half and lower half of the vertical scanning line, that is, the A of the screen.
A configuration in which the uke has a zuzu is considered.

However, when adopting such a configuration, the pixel clock for reading and writing each dot of data to the memory must be made to correspond to the horizontal scanning line and vertical scanning line, respectively, and also correspond to both odd and even fields. Let me do it 411
It becomes necessary to selectively supply the memory of 1i1,
Such a circuit has not yet been proposed.

The present invention was made in view of these circumstances, and
A horizontal synchronization signal is sent to a total of four memories in a four-part configuration.
It is an object of the present invention to provide a novel circuit for supplying a pixel clock according to a vertical synchronization signal and another of odd and even fields.

[Means for solving problems]

In the image memory clock generation circuit of the present invention, the counting results of the counters are reset by the vertical synchronization signal and the horizontal synchronization signal, respectively, and are reset by the number of dots in the horizontal direction of 2 and the number of dots in the vertical direction, A. By controlling the gate at 4 video l? The pixel clock supply to AM is switched.

[Effect]

In the image memory clock generation circuit of the present invention, a horizontal synchronization signal, a horizontal synchronization signal, and a pixel clock are alternately supplied to the four-divided memory in correspondence with odd and even fields.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to the drawings showing embodiments thereof.

FIG. 1 is a block diagram showing the configuration of a Ronque source circuit for image memory according to the present invention.

In FIG. 1, reference numeral 1 is a synchronous counter that inputs a basic clock BCLK from an input terminal T, divides the frequency by eight, and outputs the divided signal from an output terminal OC. The output from the output terminal QC of the synchronous counter 1 is given to the clock terminal CLCK of the CRT controller 2.

The CRT controller 2 is a general-purpose CRT controller that is widely used, and has clock terminals C1,
It operates according to the clock given to CK and generates a video signal period signal DISPTMG indicating a period for actual video display within the period of horizontal synchronization signal H1 for double-sided display, vertical synchronization signal V, and horizontal synchronization signal T ( Output.

3b is an impark for inverting the vertical synchronizing signal V, and the vertical synchronizing signal V inverted by this inverter 3b
For example, two counters 5 forming the first synchronous counter 5
a, 5b, and each reset terminal R of the first D-flip-flop 7 as the first gate switching means.

3a is an inverter for inverting the horizontal synchronizing signal H, and the inverted horizontal synchronizing signal ■
are three counters 6 constituting the second synchronous counter 6
a, 6b, 6c, and each reset terminal R of a second D-flip-flop 8 serving as a second gate switching means.

4 is the video signal period signal DISPTMG and the basic counter B
This is a two-man powered AND gate to which CLK is given as an input. Therefore, this AND gate 4 outputs the basic clock BCLK only during the valid period of the video signal period signal DISPTMG, and this clock output becomes the pixel clock. Note that the pixel clock that is the output of this AND gate 4 is passed through delay circuits 9a and 9b to ND gates 10a, 10b, 10c, and 10, which will be described later.
d has one input each, but both delay circuits 9a,
9b is provided to adjust the timing of the pixel clock.

As mentioned above, the first synchronous counter 5 is composed of two counters 5a and 5b, each with a reset terminal R.
An inverted signal V of the vertical synchronizing signal ■ is applied to the vertical synchronizing signal ■. Then, the counter 5a is reset by the inverted signal ■ of the vertical synchronizing signal V, and counts the video signal period signal DrSPTMG given to its input terminal T by 128 (
512 of 174) When counted, counter 5 is sent from terminal CO.
A signal is sent to the terminal EP of the D flip-flop 7 to operate the counter 5b, and a high level signal is output from the output terminal OA to the trigger terminal T of the first D-flip-flop 7.

On the other hand, the counter 5b, like the counter 5a, is reset by the inverted signal ■ of the vertical synchronization signal V, and when a signal is input from the counter 5a to the terminal HD, the video signal period signal DISPTMG given to the input terminal T is counted. This is 128 (FM counting, from the output terminal OD to the first D
- Output a high level signal to the data terminal D of the flip-flop 7.

As described above, the second synchronous counter 6 is composed of the three counters 6a, 6b, and 6c, each of which has its reset terminal R supplied with an inverted signal (2) of the horizontal synchronizing signal I. Then, the counter 6a is reset by the inverted signal (2) of the horizontal synchronizing signal H, and when the video signal period signal DTSPTMG given to its input terminal T is counted, 128 of these signals are counted.
Send a signal to terminal EP of 6c to both counters 6b and 6c.
At the same time, a high level signal is output from the output terminal QA to the trigger terminal T of the second D-flip-flop 8.

On the other hand, the counter 6b, like the counter 6a, is reset by the inverted signal (2) of the horizontal synchronizing signal II, and when a signal is input to the terminal ED, the video signal period signal DTSPTMG given to the input terminal T is counted and is counted by 128. After counting, a signal is sent from the terminal CO to the terminal EP of the counter 6c to operate the counter 6c.

The counter 6c is reset by the inverted signal (2) of the vertical synchronization signal (2), and when a signal is input to the terminal ET, the QAII output is changed to a high level and outputted to the data terminal of the first D-flip-flop 7.

The first D-flip-prop 7 is connected to one terminal T of the QA ratio output trigger of the counter 5a, and to the OD of the counter 5b.
The specific output data terminal is given to each terminal, and the Q output is given to the third
．． The output is also connected to the input of the fourth AND gate IOc, 10d. These are applied to the inputs of second AND gates 10a and 10b, respectively. Note that the reset terminal R of the first D-flip-flop 7 is supplied with the inverted signal V of the vertical synchronizing signal V, as described above.

The second D-flip-flop 8 is connected to one terminal T of the OA small output trigger of the counter 6a, and also to the QA terminal T of the counter 6c.
The Q output is given to the specific output data terminals respectively, and the Q output is given to the second
．． The input of the fourth AND game Oc, IOd, and the output of the first. These signals are applied to the inputs of the third ANII games HOa and 10b, respectively. The reset terminal R of the second D-flip-flop 8 is supplied with the inverted signal (2) of the horizontal synchronizing signal (3) as described above.

Note that these first D-flip-flop 7 and second D-flip-flop 8 are used as control means for each ANI) gate 10a, 10b, 10c, and 10d, which will be described later.

4 three-person AND gates 10a, 10b, 10c
, 10d is the respective output SCI, SC2, SC3,
SC4 is 4 each (circular video RAM 11a, Il
b, llc, lld, and the first AN
The three-man power of D game NOa is the first D-flip-flop 7
The output of the second D-flip-flop 8 and the output of the AND gate 4 serve as a pixel clock.

The three outputs of the second AND gate Ob are the output of the first D-flip-flop 7, the Q output of the second D-flip-flop 8, and the output of the AND gate 4, which are the pixel clocks.

The three outputs of the third AND gate Oc are the Q output of the first D-flip-flop 7, the vine output of the second D-flip-flop 8, and the pixel clock which is the output of the AND gate 4.

The third output of the fourth AND gate 10d is the Q output of the first D-flip-flop 7, and the Q output of the second D-flip-flop 8.
The Q output of the Q output and the output of the AND gate 4 serve as a pixel clock.

4 video RAM1], a, Ilb, llc,
Each lld is a 24k x 4 bit video I? It has an 8-bit configuration with two AM control groups, and as mentioned above, the first AND gate 10 is connected to the first video RAM 11a.
The output SCI of a is stored in the second video RAM 11b.
The output SC2 of the NO gate 10b is the third video R.
AM11c has the output SC3 of the third AND gate IOc.
However, the fourth AND game 1 is stored in the fourth video RAM 11c.
-10c output SC4 is given respectively.

Note that these video RAMs 11a, llb, Ilc
, each lid is equipped with a serial boat (not shown), and each of the above-mentioned AND games Oa, 10b,
Video signals are input and output from the respective serial ports according to the pixel clocks given from 10c and 10d.

Next, the operation of the image memory clock generation circuit of the present invention configured as described above will be explained.

Note that FIG. 2 is a timing chart for explaining the operation.

The basic clock BCLK is divided by 8 by the synchronous counter 1 and input to the CRT controller 2.
The controller 2 executes a preprogrammed control procedure according to the input clock.

Hitting, Figure 2 (a), (b), (c), (
As shown in d), a vertical synchronizing signal (2), a horizontal synchronizing signal (I), and a video signal period signal (DISPT) are generated and output.

Note that in this embodiment, one period of the vertical synchronization signal V is 16.6
6m5. The period of the vertical synchronizing signal V is 190.08 μs, one period of the horizontal synchronizing signal H is 63.36 μs, and the period of the horizontal synchronizing signal H is 9.6 μs.

CI? Horizontal synchronization signal H output from T controller 2
is inverted at impark 3a, and reset terminal R of second synchronous counter 6 and second D-flip-flop 8
is input. On the other hand, the vertical synchronizing signal (2) output from the CRT controller 2 is inverted by the inverter 3b and input to the reset terminal R of the first synchronous counter 5 and the first D-flip-flop 7.

During this time, the AND gate 4 connects the basic clock BCLK and CI
? An AND signal with the video signal period signal DISPTMG as shown in FIG. 2 te+ output from the T controller 2,
Specifically, during the valid period of the video signal period signal DISPTMG, the basic clock BCLX is changed as shown in FIG.
Bixel clock, i.e. video RAM 11a, Il
It converts and outputs the data of one pixel for each of b, llc, and lid into black and 7 corresponding to reading and writing.

In this embodiment, the valid period of the video signal period signal DTSPTMG starts 16 μs after the rise of the horizontal synchronizing signal H, and its length is 40.96 μs.

Then, the vertical synchronizing signal ■ and the horizontal synchronizing signal T (as shown in FIG. - The page output of flip-flop 7.8 is at high level.

Therefore, since the two inputs other than the pixel clock input of the first ANI) game HOa are at high level,
The pixel clock output from the ANI) gate 4 is applied to the first video!lAM 11a as the output SCI of the first AND gate Oa in FIG. 2 (as shown in hl).

Eventually, the second synchronous counter 6 counts 256 pixel clocks, that is, the number corresponding to the first half of the 512 dots required for one horizontal scanning line, and the OA output of the counter 6c changes to high level. At this time, the OA output of the counter 6a has already turned to high level. As a result, the Q output of the second D-flip-flop 8 changes to high level, and the output of the same page changes to low level. Therefore, since the input from the Q output of the second D-flip-flop 8 of the first AND gate 10a turns to low level, the first
The pixel clock is no longer output from the AND gate 10a. However, since the two inputs of the second AND gate 10b other than the pixel clock input both turn to high level, this second AND gate 10b changes to high level as shown in FIG.
The second video RAM 1 serves as the output SC2 of the gate 10a.
A 1b heavy cell clock is supplied.

In this way, when 256 heavy cell clocks are supplied to the second video RAM 11b, the old output of the counter 6c changes to low level, and the Q of the second D-flip-flop 8
The output changes to low level, the page output changes to high level, and the horizontal synchronizing signal () is output from the CRT controller 2, thereby causing the second synchronous counter 6 and the
D-flip-flop 8 is reset.

Therefore, during the period of one horizontal opening signal, the first video RAMI
256 in each of la and second video RAM 11b.
pixel clocks are provided.

By the way, both counters 5a of the first synchronous counter 5,
5b and the first D-flip-flop 7 are both reset by the vertical synchronizing signal V at the start of one frame as described above, but when the video signal period signal DISPTMG output from the CIIT controller 2 is counted 128 times, the counter The QD output of 5b changes to high level. At this time, both the QA outputs of the counter 5a have already turned to high level. As a result, the Q output of the first D-flip-flop 7 changes to high level and the same Q output changes to low level, and the first and second ANfl gates 10a, 10b
, that is, the inputs to which the outputs of the first D-flip-flop 7 are given are low level, and the inputs of the third and fourth D-flip-flops
AND gate 10c.

10d each, i.e. the first D-flip-flop 7
The pixel clock is connected to these third and fourth A as the inputs to which the Q outputs of
ND gates t-10c, 10d to 2561 [1st position are alternately supplied to the third and fourth video RAMs 11c, Ild.

This operation continues until the video signal period signal DISPTMG is counted by the first synchronous counter 5 by 128111!1, and then the first synchronous counter 5 and the first D-flip-flop are 7 is reset. In this way, during one vertical interval signal V, the first . Second
For the video RAMs 11a and llb and the third and fourth video RAMs 11c and lid, odd (or even) field data is sequentially output and written at intervals of one horizontal scanning line, and the next vertical interval signal is Even (or odd) field data is read and written during the V period.

Therefore, during two periods of the vertical synchronization signal V, each video RAM
256 pixel clocks are supplied to each of 11a, llb, llc, and lid, and image data of a frame including both odd and even fields is read and written.

〔Effect of the invention〕

As described above, the image memory clock generation circuit of the present invention converts the basic clock into a pixel clock using the vertical synchronization signal, horizontal synchronization signal, and video signal period signal that can be generated by a general CRT controller. Since it is possible to supply a serial clock compatible with 2:1 interlaced video signals, it is possible to simplify and downsize the circuit configuration, and it is also possible to synchronize with externally synchronized television cameras, etc. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the bottom of a clock generation circuit for an image memory according to the present invention, and FIG. 2 is a timing chart for explaining its operation. 2... CRT controller 4... AND gate 5... First synchronous counter 6... Second synchronous counter 7... First D-flip-flop 8
...Second D-flip-flop 10a,,]
Ob, lOc. 10d-AND gate Ila, 1], b, Ilc, 1l
d-=video RAM Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] Pixel data of the first half of each horizontal scanning line of an even field and an odd field of a 1, 2:1 interlaced video signal are stored in the first and third image memories, and pixel data of the latter half is stored in the second image memory. and a clock generation circuit for an image memory that generates a pixel clock for storing pixel clocks in a fourth image memory at an interval of one horizontal scanning line according to the basic clock, the period of a vertical synchronization signal, a horizontal synchronization signal, and one horizontal synchronization signal. a control circuit that generates a video signal period signal indicating the output period of the video signal; and a clock output means that outputs the basic clock as a pixel clock during the output period of the video signal period signal; A first counter that is reset when a signal period signal equivalent to 1/4 of the number of vertical scanning lines is counted, and a first and second gate control signal are alternately output each time the first counter is reset. a second counter that is reset by a horizontal synchronization signal or when the pixel clock counts the number of pixels equivalent to 1/2 of one horizontal scanning line; and resetting the second counter. a first gate control means that alternately outputs a third and fourth gate control signal each time the pixel clock is outputted in accordance with the first and second gate control signals; or the first (or third) and second (or fourth) memories during the same vertical synchronization signal period according to the third and fourth gate control signals. ) A clock generation circuit for an image memory, characterized in that it is provided with a gate for switching so as to alternately transfer data to the memory.