JPH01163864A - Scsi host adapter - Google Patents

Abstract

PURPOSE:To improve performance efficiently by inputting the disconnecting signal of a microprocessor and a flag from a FIFO storing the data of a constant quantity to an SCSI host adapter, and deciding the execution or interruption of a DMA action. CONSTITUTION:In an SCSI (Small Computer System Interface) host adapter 2 having a First In First Out (FIFO) memory 21 used as a data buffer at the time of a direct memory access (DMA), a DMA action is controlled by a data quantity in the FIFO 21. That is, the SCSI host adapter 2 inputs a disconnecting signal DISCON 'H' of a microprocessor 23 and a flag FLAG from the FIFO 21 storing the data of the constant quantity, and decides the execution or the interruption of the DMA action. Thus, the data to be discarded at the time of disconnection is made smaller, and a performance down at the time of the disconnection can be suppressed to a minimum.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to communication operations between a total of X hosts and multiple devices such as disk devices and tape devices, and uses direct memory access (hereinafter referred to as DMA). First-in, first-out memory (Fi
rst In FirstOUT memory; hereafter FIF
SC8I (Small Com
This invention relates to improvements to host adapters (Puter System Interface).

<Prior Art> FIG. 2 shows an example in which the above-mentioned 5C3I host adapter is used in a computer system.

The system in this figure consists of a processor μpH and a memory RAM
The host compute 1ilcPUI with 12 and the system
5C with FIFO21 connected via bus SB
3I host adapter 2 and 5cst input/output bus
A plurality of devices connected to bus B, that is, disk devices 3
1. It is composed of a tape device 32.

The 5C3I host adapter 2 controls DMA transfer between the RAM 12 in the CPUI and the disk device 31 or tape device 32 using the internal FIF 021 as a data buffer.

<Problems to be Solved by the Invention> Here, it is assumed that the 5C3I host adapter 2 uses the PIF021 to transfer data between the RAM 12 and the tape device 32.

At this time, assume that for some reason a request is generated to interrupt data transfer with the tape device t32 and transfer data to the disk device 31 first.

Note that the function of interrupting data transfer with a device (in this example, the tape device 32 or disk device 31) is called a disconnect function.

In this case, assuming that a large amount of data to be transferred to the tape device 32 is already stored inside the FIFO 21,
In order to newly import data to be transferred to the disk device 31, the 5C3I host adapter 2 uses the F I FO21
There was a problem in that all the data inside had to be discarded, which led to a drop in performance.

That is, if the data in the FIFO is discarded at the time of disconnection, the system bus occupation time required to fetch this data from the CPU side is completely wasted.

The present invention has been made to solve the above problems, and aims to improve the efficiency of system performance.

Means for Solving Problems> The present invention controls a DMA operation based on the amount of data in a FIFO, and its configuration is as follows.

That is, the present invention provides a 5C3I host adapter that is involved in communication operations between a host computer and a plurality of devices and that has a first-in, first-out memory that is used as a data buffer during direct memory access. The 5C3I host computer is characterized in that a flag is output when the data is stored, and a control section is provided for controlling the direct memory access operation based on this flag, a disconnect signal given from a microprocessor, and a disconnect signal given from a microprocessor. It's an adapter.

The 5C3I host adapter of the present invention inputs a microprocessor disconnect signal and a flag from a FIFO containing a certain amount of data to determine whether to perform or suspend a DMA operation.

<Embodiment> FIG. 1 shows an example of a 5C3I host adapter in which the present invention is implemented.

In this figure, 21 is a FIFO, and a flag FLAG becomes "H" when the amount of internal data reaches a certain amount.
For example, if the total capacity of FIFO 21 is set to 32 bytes, and the data amount is 2 bytes, FLAG "H" is sent.
shall be sent.

22 is a direct memory access controller D
It is a MAC and controls data transfer performed via FIFO21. The signal REQ is a request signal for the DMA C22, and when RE = “L”, the DMA
C22 performs data transfer.

23 is a microprocessor MPU, which receives various parameters associated with data transfer from the CPU 1 and sends them to the DMAC.
In addition, when a device that supports the disconnect function is connected to this 5C3I host adapter 2, the MPU 23 always sends the disk connect signal DI when transferring data to that device.
Sends 5CON “H”.

24 is a control section, which is composed of a first gate circuit g1 and a second gate circuit g2. The first gate circuit g1 is M
Manually input signal DI 5CON from PU23 and F
Input the flag FLAG from IFO21. Second
The gate circuit g2 connects the output of the first gate circuit g1 to the DMA generated on the device side or host computer side, etc.
A request signal REQ is input, and its output is used as an activation signal for the DMAC 22.

The 5C6I host adapter 2 of the present invention configured as described above operates as follows.

Currently, the MPU 23 always sends the signal D I when a device involved in data transfer disconnects.
5CON ``H'' is being sent.

Now, assume that a data transfer destination device with a possibility of disconnection has been determined, and the DMAC 22 controls the FIFO 21 to start data transfer.

Then, when the disconnect signal is not given from the device side and the capacity of FI FO21 reaches 2 bytes,
FLAG becomes 'H'.

As a result, the first gate circuit Ngl becomes DISCON″H
", FLAG"H", the output becomes "L".Furthermore, this output "L" is given to the second gate circuit g2, and the second gate circuit g2 receives the DMA request signal REQ generated by either one. is blocked, and a DMA prohibition signal (
“H”) is given, and DMA is interrupted.

In other words, FIFO21 originally has a capacity of 32 bytes, but during DMA with a device that may be disconnected, it is apparently always used as a FIFO with a capacity of 2 bytes. . As a result, in the conventional method, up to 32 bytes of data were discarded at the time of disconnection, causing system waste.
According to the present invention, the data to be discarded at the time of disconnection can be reduced to a maximum of 2 bytes, and the performance drop at the time of disconnection can be kept to a minimum.

<Effects of the Invention> The 5C3I host adapter of the present invention inputs the disconnect signal of the microprocessor and the flag from the FIFO that stores a certain amount of data, and determines whether to execute or interrupt the DMA operation, so it is easy to use in the system. It is possible to reduce waste and improve performance efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of a 5C3I host adapter embodying the present invention, and FIG. 2 is a system diagram when a conventional SCSI host adapter is used. 1...Host calculation 1ficPU, 11...Processor μP, 12...Memory RAM, 2...5C3I host adapter, 21...FIF
O122...Direct memory access controller DMAC1 23...Microprocessor MPU, 24...Control unit, gl...First gate circuit, g2...Second gate circuit, 31...・Disk device, 32...Tape device, SB
...System bus, B...5C3I bus. Figure 1 Figure Z

Claims (1)

[Claims] Involved in communication operations between the host computer and multiple devices,
SCSI with first-in, first-out memory used as a data buffer during direct memory access
In the host adapter, a control unit outputs a flag when a certain amount of data is stored in the first-in, first-out memory, and controls direct memory access operation based on the flag and a disconnect signal given from the microprocessor. An SC characterized by providing
SI host adapter.