JPH01156858A - Computer system - Google Patents

Abstract

PURPOSE:To avoid the omission of DMA data during its transfer by deciding based on the semaphore contained in an operation system whether or not another program routine worked first by each program routine which performs the transfer of the DMA data of low-speed input/output space access. CONSTITUTION:The program routines 41-4m and 51-5n register their under- execution states on a semaphore 6 set in an operation system before each program routine starts its prescribed working. In case another program routine registers earlier its under-execution state under such conditions, the execution of the relevant program routine is held until the earlier registration of the program routine is canceled. While the exclusive action of each program routine is surely carried out since the registration is canceled on the semaphore 6 after execution of each program routine. Thus it is possible to avoid such a case where a CPU is held by the low-speed input/output space access routines 41-4m during the transfer of DMA data. Then the omission of the DMA data can be avoided during its transfer.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention comprises a slow input/output space access task and a DMA access task, which are operated in parallel by a multitasking operating system. related to computer systems.

(Prior Art) In recent years, computer systems have been widely used for monitoring and controlling industrial plants. Such computer systems constantly monitor the status of each device that makes up the plant or state variables such as temperature, pressure, and flow rate within the system, and control the plant based on the monitoring results. It also performs self-diagnosis and failure detection of each hardware component that makes up the plant, and outputs warnings and the like as necessary.

Next, a description will be given of the hardware configuration within one unit case of a computer system that performs such monitoring and control.

A plurality of hardware modules are arranged within one unit case via a bus for transmitting data and addresses.

Hardware modules include a basic central module for monitoring the entire bus, a main CPU module, a memory module, and unique monitoring and control modules that differ for each system.

There are input/output modules, etc.

In addition to hardware elements that perform the respective module functions, each of these hardware modules has hardware elements allocated in the low-speed input/output space for the purpose of monitoring the status of each module and of the module itself, and setting the operating mode. A group of registers are arranged.

By accessing this register group, e.g.

(1) Module ID number (2) Bus operation abnormality and its causes (3) Memory parity check abnormality (4) Temperature monitoring (5) Software runaway check (6) Reset type (7) Memory address space The readout status, status settings, etc. of information related to settings, etc. are performed.

In computer systems for monitoring and controlling industrial plants, the contents of the registers in the above-mentioned low-speed input/output space are constantly checked to monitor abnormal conditions, and in the event of an abnormality, processing such as outputting an alarm, resetting, and restarting is performed. It is necessary to do it.

On the other hand, application software often requires data transfer to disk devices and data communication with other computer systems for plant monitoring and control.

In order to efficiently transfer data between a disk device and a memory, data is generally transferred using DMA.

Also, to speed up processing in data communication with other computer systems.

This may be performed by DMA transfer.

Next, a DMA data transfer operation in the disk device will be explained.

FIG. 3 shows an example of a CPU module in a computer system, and this CPU module 1 is
It is connected to other modules via a system bus 2.

The CPU 1a manages the entire computer system, and uses MPC (Message Passin).
g Co-Processor) lb performs data transfer with other modules via the system bus 2. In this MPctb, registers for the low-speed input/output space are arranged.

The disk controller 1c controls the disk device 3. The DMA controller 1d.

This causes the disk controller 1c to execute data transfer between the memory 1e and the disk device 3 by DMA.

With this configuration, in the application program,
When an input/output request is made to the disk device 3, the operating system transfers control to a disk driver routine.

The disk driver routine issues a command to the disk controller 1c in accordance with the above input/output request. As a result, the DMA request code R1 is output from the disk controller lc to the DMA controller ld. When the DMA controller 1d inputs this, the DMA controller 1d
A hold signal is output to U1a to request the right to use bus If. In response, the CPU Ia returns the hold acceptance signal AI to the DMA controller 1d, releases the bus 1f, and enters the hold state.

As a result, the DMA controller ld acquires the right to use the bus 1f and returns a DMA request acceptance signal A2 to the disk controller 1c. In this way, the disk controller 1c
confirms the establishment of the DMA transfer path, and executes a predetermined DMA transfer between the disk device 3 and the memory 1e.

The operation from when the disk controller 1c outputs the DMA request signal R1 until it receives the DMA request acceptance signal A2 is repeatedly executed for each transfer of 1 byte.

Generally, data input/output is performed in a disk device in units of one sector, so for example, one sector is 512
If the amount of data is in bytes, such an operation will be repeated 512 times for one input/output request in a program. C
Intermittently during this operation, PU1a outputs the DMA request signal R1.
In response to this, bus 1f is released.

However, the CPU 1a executes various processes during the idle time between the end of data transfer of one byte and the time when the transfer of the next one byte is instructed. Note that this DMA data transfer is performed in synchronization with the rotation cycle of the disk, so this idle time occurs at a constant cycle.

By the way, access to the above-mentioned low-speed input/output space is performed by MP
This is done by the operation of Clb. When MPClb executes this access operation, it outputs a hold signal H2 to the CPU 1a. Therefore, the CPU 1a is temporarily held in the same way as above.

The CPU hold time at this time is usually several hundred microseconds, and this time corresponds to the time to transfer DMA data of several bytes to several tens of bytes to the disk device 3.

By the way, in this basic software and application software, input/output tasks are provided to transfer data using DMA for disk access, communication, etc., while low-speed input/output space is used for setting and monitoring hardware modules. There are tasks to access. The above two types of tasks apparently operate in parallel under the control of the multi-task operation system.

(Problem to be Solved by the Invention) As described above, in an environment where a DMA access task and a low-speed input/output access task operate in parallel as a multitask, suppose that the former task is executed and the D
Assume that the latter task is executed and the low-speed input/output space is accessed during a period when MA data transfer is being performed intermittently.

Then, since the CPU 1a is held by MPClb during the access period, it is unable to respond to the hold request from the DMA controller 1d, and DMA data transfer is interrupted during that period.

DMA data transfer must be performed at a predetermined timing synchronized with the rotation of the disk, so if the transfer process is not performed at the desired timing, data for that period will be lost.

Conventionally, as a countermeasure to this problem, when creating application programs, consideration was given to ensuring that tasks that access the disk and tasks that access low-speed input/output space operate exclusively and are not executed at the same time. .

However, there are cases where an operating system that cannot be managed by an application program accesses the disk or low-speed input/output space, making it impossible to ensure exclusive operation as described above.

For this reason, in such a conventional computer system, there has been a problem in that data is lost during DMA data transfer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a computer system that solves the above problems and eliminates data loss during DMA data transfer.

[Structure of the Invention] (Means for Solving the Problems) For this purpose, the present invention provides for each program routine that performs DMA data transfer or low-speed input/output space access to In addition to registering the execution of the program routine in the semaphore provided in the real-time multitasking operation system, if at the time of registration, the execution is registered earlier by each of the other program routines, that The present invention is characterized in that the program routine waits without being executed until the registration is canceled, and the registration in the semaphore is canceled after the program routine is executed.

(Function) Each program routine that performs DMA data transfer or low-speed input/output space access determines whether another program routine is being executed first based on the semaphore provided in the operating system. Program routines can be reliably operated in an exclusive manner. Therefore, this makes it possible to eliminate loss of transfer data during DMA data transfer.

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a conceptual diagram of a main program routine in a computer system according to an embodiment of the present invention. The hardware of the computer system of this embodiment is the third
The configuration is the same as shown in the figure, and the software is real-time
Various application programs are now executed using a multitasking operating system as a basic system.

In FIG. 1, the low-speed input/output space access routine 41
4111 accesses the low-speed input/output space in the application software and basic system.

DMA access routines 51 to 50 perform DMA data transfer to a disk device or a communication channel in a disk driver or communication channel driver.

Further, the semaphore 6 is intended for real-time multitasking operation systems, and is a shared variable that can be accessed from any of the low-speed input/output space access routines 41-4m and the DMA access routines 51-50. In this embodiment, the flag is used as a flag for managing the execution of each of the above access routines.

First, the operation when any one low-speed input/output space access routine 41 and any one DMA access routine 5j are executed in the above configuration will be described.

In the semaphore 6, while any of the access routines mentioned above is being executed, it is registered that the access routine is being executed. When the low-speed input/output space access routine 41 is activated, it checks the contents of the semaphore 6, as shown in FIG. 2(a). When no other access routine is indicated as being executed, the low-speed input/output space access routine 41
The execution of the access routine is registered in the semaphore 6 to obtain access rights (process 71).

After this, process 72 to access the predetermined low-speed input/output space.
), after execution, cancels the registration to the semaphore 6 and relinquishes the access right (processing 73).

On the other hand, when semaphore 6 indicates that another access routine is being executed, low-speed input/output space access routine 4
1 waits until the execution of its other access routines is finished.

Furthermore, when the DMA access routine 5j is also activated, it checks the contents of the semaphore 6 as shown in FIG. Low speed input/output space access routine 41
registers execution of the access routine in the semaphore 6 and acquires access rights (process 74). Thereafter, process 75) allows access to the disk device and communication channel through predetermined DMA data transfer, and after that, cancels the above registration to semaphore 6 and relinquishes the access right (process 76).
).

Further, when it is indicated that another access routine is being executed, the DMA access routine 5j waits until the execution of that access routine is completed.

In this way, the low-speed input/output space access routines 41 to 41
Any one of the access routines 11 and DMA access routines 51 to 5n can acquire access rights from the semaphore 6 and execute it, and during its execution,
Other access routines will not be able to gain access rights and will be guaranteed to be excluded.

This prevents the low-speed input/output space access routines 41-4m from being activated and holding the CPU during DMA data transfer by the DMA access routines 51-50. There will be no missing parts.

[Effects of the Invention] As described above, according to the present invention, each program routine that performs DMA data transfer or low-speed input/output space access uses a semaphore provided in the operation system before starting a predetermined operation. The execution of the program routine in question is registered, and if, at the time of registration, the execution is registered earlier by another program routine.

The program routine waits without being executed until the registration is cancelled, and the registration to the semaphore is canceled after the program routine is executed.
Since the exclusive operation of each program routine can be performed reliably, the CPU is prevented from being held by the low-speed input/output space access routine during DMA data transfer, thereby eliminating loss of transfer data during DMA data transfer.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram of main program routines in a computer system according to an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of each program routine, and FIG.
The figure is a hardware configuration diagram showing an example of a CPU module. 1 ・CPU module, la -CPU, Ib-
MPCllc...Disk controller 1~roller, ld...
・DMA controller, le... memory, If...
・Bus, 2... System bus, 3... Disk device, 4j... Low speed input/output space access routine, 5j.
...DMA access routine, 6...semaphore. (7317) Agent: Patent Attorney Noriyuki Chika (
8869) Ken Daishimaru Figure 1 (a) (b) Figure 2

Claims (1)

[Claims] A real-time multitasking operation system is the basic system, and after the central processing unit that executes the application program and the central processing unit are put on hold, the disk device or communication channel is
DMA data transfer means for executing data transfer by MA; low-speed input/output space access means for accessing low-speed input/output space after holding the central processing unit;
In a computer system comprising each program routine for activating the DMA data transfer means and the low-speed input/output space access means, each of the program routines includes a program routine before activating the DMA data transfer means or the low-speed input/output space access means. In addition, the real-time
Execution registration means for registering that the program routine is currently being executed in a semaphore provided in the multitasking operation system; 1. A computer system comprising: execution standby means for not executing the program routine until the program routine is canceled; and registration canceling means for canceling registration in the semaphore after the program routine is executed.