JPH01155459A - Processor and parallel computer - Google Patents

Abstract

PURPOSE:To lower a power cost by reducing power consumption and to miniaturize a computer by simplifying a cooling unit for heat generation by providing a means to detect the execution of a program and a power source current control means at an arithmetic processor. CONSTITUTION:The arithmetic processor 1 is constituted of independent blocks such as a program memory 2, an instruction decoding part 3 which decodes instructions read out sequentially from the memory 2, a data memory 4 operated according to sequence judged by the decoding part 3, an ALU5, and a multiplier 6, etc. Also, the decoding part 3 supplies the operating sequence of respective block, and also, supplies a power down control signal to perform the limitation of a power source current to power down circuits 9-1-9-4 attached on the block not being operated. And the circuits 9-1-9-4 limit the supply of the power source current to the block to which they belong, respectively. In such a way, it is possible to lower the power cost by reducing the power consumption, and to miniaturize the computer by simplifying the cooling unit for the heat generation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an arithmetic processor and a parallel computer using a plurality of arithmetic processors, and particularly to reducing power consumption of the device,
This provides a power supply means for a processor that is suitable for space saving and cost reduction.

(Prior Art) In the development of supercomputers to achieve processing speeds exceeding T (Tera) FLOPS, research has been conducted on methods for increasing the speed by operating multiple processors in parallel. The number of arithmetic processors used can range from several thousand to even hundreds.

ICs that power down for the purpose of reducing power consumption are individually used in memory, microcontrollers, and the like.

The method used in actual memory is to use a signal from an external chip select terminal to power down the internal memory. The microcomputer has a dedicated instruction to enter a power-down mode, and enters a power-down state by executing this instruction.

As an actual circuit system, a method is generally used to reduce power consumption by stopping the supplied clock.

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, when the number of arithmetic processors reaches several thousand or more, the power consumption becomes enormous.

For this reason, each heat generated is large, and therefore the cooling device equipment becomes large-scale, resulting in problems such as an increase in installation space, an increase in electric power, and an increase in cost.

An object of the present invention is to more effectively limit power consumption to the necessary minimum.

[Means for solving problems]

The above object is achieved by determining the program instructions to be executed by the processor and limiting the current supply to circuit blocks that are not used during instruction execution.

Furthermore, in a parallel computer realized by operating a plurality of processors in parallel, when a program is transferred to a processor to be executed, this is achieved by limiting the current supply to the processors to which the program is not transferred.

[Effect]

Generally, a processor reads a program from memory and decodes instructions to perform processing.

Normally, the circuits required for processing by an instruction are fixed, and it is easy to detect circuits that are unnecessary for execution.A circuit is provided to limit the current supply to the 0 circuit, and this circuit is controlled by the output signal of the above detection result. By doing.

Unnecessary power consumption can be reduced.

Furthermore, in a parallel computer, it is possible to detect which processor is used when compiling a source program for calculation processing. Therefore, in this case as well.

Current supply to processors that are not operating can be limited.

With the above, unnecessary power consumption can be reduced.

〔Example〕

Hereinafter, the present invention will be explained in detail using examples.

FIG. 1 shows a first embodiment of the invention. The arithmetic processor 1 has a program memory 2. 3. an instruction decoding unit that decodes instructions sequentially read from the program memory; A data memory 4 that operates according to the sequence determined by the instruction decoder 3. It is composed of independent blocks including an ALU 5, a multiplier 6, and an I10 section 7, and the blocks are connected by a data bus 8 for data transfer.

The instruction decoding section 3 provides the operation sequence of the blocks, and at the same time, the power down circuits 9-1. A power-down control signal for limiting the power supply current is applied to 9-4. The power down circuit 9 receives the power down control signal.
-1 to 9-4 limit the power supply current supply of the respective associated blocks.

In this embodiment, the command to power down is generated by the instruction decoding section 3, but as another method, it is also possible to make the power down decision for each processing block individually.

FIG. 2 shows a second embodiment of the invention. An interface circuit 12 that performs input/output between the arithmetic processor 1 and data memory 11 in FIG. 1 and the outside, and the arithmetic processor 1
．． Data memory 11. A communication network 15 that uses n processor elements 10 each configured of a data bus 14 that transfers data between the interface circuits 12 and connects the interface circuits 12 of the processor elements 10-1 to 10-n, and the processor The arithmetic processor 1, which is a parallel computer configured with a control circuit 16 that transfers programs to elements 10-1 to 10-n or performs state control, controls external circuits that are accessed when accessing external circuits during execution of arithmetic operations. A power down control signal is supplied to the power down circuit 14 in response to the power down control signal.

The power-down circuit receives the power-down control signal from the memory 11. of the associated external circuit. It is determined whether any or all of the interface circuits 12 should be powered down, and the power supply current is limited for circuits that are not accessed.

Further, the control circuit 16 applies a signal to the power down circuit 13 attached to the processor 1 among the processor elements 10 that do not execute a program, and limits the power supply current to the processor 1 and peripheral circuits.

The configurations of the processor and parallel computer in the embodiments described above are examples, and do not limit the configuration to be implemented.
Furthermore, in the embodiment, the power supply current supplied to each circuit is limited for the entire block.

It is also possible to limit the power supply current supply by further subdividing the block.

As means for powering down, there are a method of stopping the clock input to the circuit block, a method of limiting the current supplied to each transistor, and a method of cutting off the power supply.

FIG. 3 shows an instruction decoder 3 in the first embodiment of the present invention.
This is an example. The instruction output from the program memory 21 pointed to by the program address counter 20 is stored in the prefetch register 22 for prefetching, and the instruction previously stored in the prefetch register 22 is stored in the next instruction register 25. sent to. The output of the instruction register 24 becomes the address of the microcode ROM 26, and the output of the microcode ROM becomes the address of the microcode ROM 26.

Control the operation of the processor. The outputs of the brief fetch register 22 and the instruction register 24 are input as addresses of the power down control code ROM 25, and the output of the power down control code ROM 25 controls the power down of each functional block.

The selector 23 is a changeover switch for inputting the jump destination instruction to the instruction register 24 without going through the briefetch register when executing a 1-branch instruction.

Here, by powering down the instruction in anticipation of the future state, the startup operation from the power down mode can be sped up.

〔Effect of the invention〕

As described in detail below, according to the present invention, it is possible to significantly reduce the power consumption of a processor or a parallel computer consisting of a large number of processors, and it is effective in reducing power costs. Furthermore, since the cooling device for heat generation is simplified, it is effective in reducing the size and cost of the computer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment in which the invention is applied to an arithmetic processor, FIG. 2 is a block diagram of an embodiment in which the invention is applied to a parallel computer, and FIG. 3 is a block diagram of an embodiment in which the invention is applied to a parallel computer. It is a block diagram showing an example. 1... Arithmetic processor, 3... Instruction decoder, 9-1
゜9-2.9-3.9-4...Power down circuit, 1
0-1, 10-2, -10-n-processor element, 13.14-1.14-2...power down circuit, 16...control circuit, 22...brifetch register, 24...・Instruction register, 25...power/l pull ηrii: J path

Claims (1)

[Scope of Claims] 1. A programmable arithmetic processor, characterized in that it is provided with means for detecting a program execution state and means for controlling a power supply current flowing from a power supply input terminal by the detection means. processor. 2. The processor according to claim 1, further comprising means for independently controlling power supply current for each individual block within the processor. 3. In a parallel computer that has a plurality of independently operating processor groups and a control unit that writes programs to each processor and controls the operating state, a program can be executed internally in some or all of the processor groups. A parallel computer characterized by using a processor comprising means for detecting a state and means for controlling a power supply current flowing from a power supply input terminal using the detection means. 4. For multiple peripheral circuits attached to the processor,
Claim 3, characterized in that each circuit is provided with means for detecting the operating state according to the command and means for controlling the power supply current of each circuit according to the detection result during execution of the command. Parallel computer described. 5. The processor according to claim 2, further comprising means for reading an instruction in advance and means for controlling a power supply current based on the currently executing instruction and the previously read instruction. 6. The processor according to claim 2, wherein the means for controlling the power supply includes means for restricting the current supply and canceling the restriction during execution of an instruction.