JPH01149299A - Non-volatile semiconductor storage - Google Patents

Abstract

PURPOSE:To suppress energy consumption by detecting the size of the output voltage of a high pressure generating means and changing a voltage rising rate according to the size. CONSTITUTION:When a control signal CNT1 is outputted to instruct a writing from a CPU4 and a high voltage VPP for writing does not achieve a prescribed value for a control signal CNT4 of a comparator 14, a control signal CNT2 is outputted and an oscillating means 1 starts oscillation. A booster means 6 receives the output of the oscillating means 1 and boosts an external power source voltage VCC and the boosted voltage VPP is detected by a voltage detecting means 12 in a constant voltage means 10. When a reference voltage VR1 to be outputted from the voltage detecting means 12 goes to be larger than a reference voltage VR2, the output of the CNT2 is prohibited by an output CNT4 of the comparator 14 and the oscillation of the oscillating means 1 is stopped. Then, the maximum value of the voltage VPP is limited and a constant voltage is obtained. Thus, the energy consumption can be suppressed.

Description

[Detailed Description of the Invention] [Summary] Regarding a nonvolatile semiconductor memory device having a write circuit that boosts an externally supplied power supply voltage to generate a write voltage for an EEFROM cell or the like, the output write voltage is The purpose is to control power consumption by varying the capacity of the booster circuit according to its size, and to achieve this with fewer circuit elements. step-up means for boosting a power supply voltage to output a data write voltage; A voltage detecting means receives voltages at a plurality of output terminals of the voltage detecting means, and as a write voltage outputted from the boosting means increases, an oscillation frequency of the oscillation means and a voltage increase rate of the boosting means are reduced. and a constant voltage means that compares the voltage of one of the output terminals of the voltage detection means with a reference voltage and stops boosting when the write voltage reaches a predetermined value. The write circuit includes a write circuit having the following configuration.

[Industrial application field]

The present invention relates to a non-volatile semiconductor memory device, more specifically, to an EEF system in which an externally supplied power supply voltage is boosted within a chip.
The present invention relates to a nonvolatile semiconductor memory device equipped with a write circuit that generates a voltage necessary for writing into a ROM cell or the like.

[Conventional technology]

When writing data to a floating gate type EEFROM cell, a rectangular pulse having a relatively high voltage amplitude of, for example, about 20V and a pulse width of 2 to 3+ws is applied, but when the externally supplied power supply voltage is 5V. In a nonvolatile semiconductor memory device that uses a voltage power supply of about 100 MHz, or a microprocessor incorporating the same, when writing data, it is necessary to boost the power supply voltage within the chip to generate a write voltage. For this reason, a write circuit 30 such as that shown in FIG. 5, for example, is commonly used.

The write circuit 30 is provided with a booster 32 (charge pump) that increases the voltage by inputting a pulse wave from the oscillator 21, and the DC voltage boosted by the booster 32 is transferred to the CPU 33. control so that it becomes a predetermined writing pulse,
Furthermore, the write pulse obtained by this is applied to the constant voltage means 3.
4, and waveform shaping means 35 for eliminating pulse overshoot.
The signal is output to the EEPROM cell array 36 via the EEPROM cell array 36.

In addition, Fig. 5 shows how the EEFROM is connected to the Myracro processor 37.
An example is shown below.

[Problem that the invention seeks to solve]

However, if the boosting means 32 is configured with a circuit such as a Kotscroft-Walton circuit, the current supply capacity of the boosting means 32 increases in proportion to the output frequency of the oscillation means 31, so the frequency is low and the load is low. If it is heavy,
There is an inconvenience that the current is insufficient and the device does not operate properly.

For this reason, the number of oscillation cycles of the oscillation means 31 is set high in advance, and if the voltage is increased too much, the voltage that has been increased too much is limited by the constant voltage means 34. When an EEPROM is used, a problem arises in that the power consumption in the oscillation means 21 increases further as the frequency increases.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to suppress power consumption by changing the boosting capability according to the size of the load or the value of the output voltage, and to achieve this with fewer circuit elements.

[Means for solving problems]

In the principle diagram shown in FIG. 1, the above problem is solved by the oscillation means 1 and the boosting means 6 which receives the output of the oscillation means 1, boosts the power supply voltage supplied from the outside, and outputs the data writing voltage. , a voltage detecting means 12 connected to the output terminal of the boosting means 6 and dividing the write voltage outputted by the boosting means 6 and outputting the divided voltage to a plurality of output terminals; and a plurality of outputs of the voltage detecting means 12. a delay means 17 for controlling the oscillation frequency of the oscillation means 1 and the voltage increase rate of the boosting means 6 to decrease as the write voltage output from the boosting means 6 increases; A write circuit includes a constant voltage means 11 that compares the voltage of one of the output terminals of the voltage detection means 12 with a reference voltage and stops boosting when the write voltage reaches a predetermined value. This is achieved by a nonvolatile semiconductor memory device characterized by the following.

[For production]

A control signal CNT + instructing writing from the CPU 4 is output, and a control signal CNT of the comparator 14.

When indicates that the write high voltage v1 has not reached a predetermined value, the control signal CNTt is output and the oscillation means 1 starts oscillating.

Boosting means 6 receives the output of oscillation means 1 and boosts external power supply voltage VCC. The boosted voltage V□ is detected by the voltage detection means 12 in the constant voltage means IO. This voltage detecting means 12 detects the voltage VPP output from the boosting means 6.
As V increases, the oscillation frequency of the oscillation means 1 is lowered by the control signal CNTs, thereby reducing the boosting ability of the boosting means 6 and making the rise of the voltage V□ gradual.

Furthermore, the reference voltage v1 output from the voltage detection means 12
is the reference voltage v, I! If it is larger, comparator 14
output commercial? , inhibits the output of CNTz and stops the oscillation of the oscillation means l. This limits the maximum value of the voltage V□ to achieve constant voltage.

〔Example〕

(a) Description of an Embodiment FIG. 2 shows an embodiment of the present invention, in which the reference numeral 1 indicates an odd number of inverters 2 connected in series via an MO3 resistor 3. 2 is a loop oscillation means that feeds back the output of the final stage to the first stage inverter 2 via an AND gate G.
The switch 5 (which is turned ON and OFF by the output signal CNT2 of the anime game)
MOS) transistor) is installed, switch 5
When G is turned on, one input of AND gate G is set to a high level (H level), thereby forming a feedback loop and starting oscillation.

Reference numeral 6 denotes a boosting means for boosting the power supply voltage Vcc by receiving the pulse wave of the oscillation means 1 via a MOS transistor (MOS) that is turned on and off by the control signal CNT3 of the CPU 4. A plurality of diodes 8a... are installed with their anodes connected to the power supply voltage VCC, and these diodes 8a...
Each connection point has a charge pump in which a capacitor 8b for inputting a pulse wave from the oscillation means 1 and a capacitor 8c for inputting this pulse wave via an inverter 9 are connected alternately to every other capacitor. , when a pulse wave is input from the oscillation means 1, the voltage of the pulse wave is pumped up and converted into a DC voltage, and the EEF is used as the write voltage.
output to the ROM cell array 10 and select a predetermined word line in the EEPROM cell array 10 according to a command signal from the CPU 4;
The bit line is configured to apply a voltage to the bit line.

Reference numeral 11 denotes a constant voltage means for detecting the magnitude of the voltage output from the boosting means 6 to the EEPROM cell array IO and limiting an excessive output voltage of the boosting means 6, which is composed of a voltage detecting means 12 and a resistive voltage divider circuit. The reference voltage generation means 13 and a comparator 14 are provided.

The voltage detection means 12 described above is an N-channel enhancement offset gate transistor (high voltage transistor) Q, ~Q11 whose gate and drain are commonly connected.
++ connected in series, one end on the drain side of this voltage detecting means 16 receives the output voltage VPP of the boosting means 6, and the other end on the source side receives the output voltage VPP of the boosting means 6. Enhancement transistor 1. is grounded via an N-channel depletion transistor t2 whose source and base are short-circuited, and an N-channel enhancement transistor t is connected to the CPU 4.
H level signal CNT output from to AND gate G.
It is configured to turn on and off in response to +. This voltage detection means 12 is a kind of voltage dividing circuit, and such a voltage division is necessary for the reference voltage (2) of the comparator 14. This is because Vcc is created based on the external power supply voltage Vcc.

Further, the above-mentioned comparator 14 is connected to the voltage detection means 12.
N-channel dayvision transistor connected to t
2 and the output voltage v, l! of the reference voltage generating means 13. The voltage V+t1 is the reference voltage ■. When the rise is higher than , the low level (
The switch 5 is configured to turn off the switch 5 by outputting an inverted signal CNT to (L level). Note that the voltage V output from the reference voltage generating means 13. is the boosting means 6
It is set so that the output CNTa of the comparator 14 is inverted when the output voltage V□ of the comparator 14 is increased to a predetermined value.

17 is a delay means connected in parallel between the first stage and the second stage of the inverter 2 in the oscillation circuit I,
This delay means 17 is an MO3 field effect transistor (F
ET) A plurality of CR circuits 20.ET) in which capacitors (MOS capacitors) 191 to 1911 are connected in series to each of 18+ to 18, respectively. 207 are further connected in parallel, and each CR circuit 20. Each FET I L ~1B in ~207 is turned on when the control signal CNT of the control terminal T+~Tt connected between each high voltage transistor Q and ~Qa++ of the voltage detection means 16 exceeds a threshold value. is configured to do so.

Note that symbols t2 and t4 indicate N-channel enhancement.
A CPU controlling an N-channel enhancement transistor t2, which is a transistor and is connected to the voltage detection means 12.
4, which turns on and off the comparator 14 and the reference voltage generating means 13. In addition, T-4 and LS are P-channel enhancement transistors, L6 to t are N-channel enhancement transistors, and each comparator 1
4.

Further, Lq and tlo are N-channel enhancement transistors forming a voltage dividing circuit of the reference voltage generating means 13.

Next, the operation of the above embodiment will be explained.

In the embodiment described above, the EEFROM cell array 10
When writing data D to , the CPU 4 sets the control signal CNT, which instructs writing, to H level.

As a result, the transistor t+ in the voltage stabilizing means 11
, t, s, and Lm are turned on, and the voltage detection means 12, the comparator 14, and the reference voltage generation means 13 become operable.

In this state, the output voltage Vllll+ of the boosting means 6 is still a low voltage, and the voltage V□
is smaller than the reference voltage vo input to the comparator 14, so the output control signal CNT of the comparator 14 is H
become the level.

Therefore, the control signal C of the CPU 4 and the comparator 14
The output of the AND gate Gt inputting NT I and CNT becomes H level, and the transistor 5 receiving this turns on.

As a result, one input of the AND gate G becomes H, and an (i-return loop is formed in the oscillation circuit 1 to start oscillation. However, since the output voltage V□ of the boosting means 6 is still at a low level, The control voltages at the terminals T, -T7 of the voltage detection means 12 do not turn on any of the transistors 18.about.181.

In this state, the oscillation frequency of the oscillation means 1 reaches its maximum value.

When the control signal CNT+ of the CPU 4 becomes H level and the transistor 7 is turned on, the booster 6 uses a charge pump action to gradually boost the external power supply voltage Vcc to the voltage V□.
Output.

Therefore, the voltage VPP is applied to the voltage detection means 12, a current flows, and the control signal CNT is outputted from the terminals T, .about.T11, and the detected voltage Vl11 is outputted from the source side of the transistor t1.

By the way, since the output frequency of the oscillation means 1 is high at the start of oscillation, the voltage V of the boosting means 6 rises rapidly. When the voltage V□ starts to rise, first, when the voltage at the terminal T of the voltage detection means 12 reaches the dark value voltage of the transistor 1B+, the transistor 18 is turned on and the MOS capacitor 1 is turned on.
9. is connected to the oscillation means 1, and the oscillation frequency is lowered.

As a result, the boosting ability of the booster circuit 6 decreases, and the rate of increase in the output voltage V□ decreases.

When the output voltage VPP of the booster circuit 6 further increases and the voltage applied to the terminal T2 of the voltage detection circuit 12 reaches the dark value voltage of the transistor 183, the MOS capacitor 19. is connected to the oscillation circuit 1. As a result, the oscillation frequency is further reduced and the rate of increase in V□ is also further reduced.

As the output voltage V□ of the booster circuit 6 increases, transistors 1Bt to 18. , are turned on one after another to gradually lower the oscillation frequency (rate of increase in voltage V□), thereby obtaining a rising waveform of Vpp as shown in FIG.

Voltage v9 of booster circuit 6. When t! further increases and reaches a predetermined value, the transistor t! connected to the voltage detection means 12! Since the bitter voltage ■□ becomes larger than the reference voltage V@t and becomes VR,>VR, the control signal CN↑4 from the comparator 14 becomes L level and the AND gate Gt
The output CN↑ of is set to L level.

Therefore, the transistor 5 is turned off and the oscillation of the oscillation circuit 1 is stopped. Therefore, the output voltage v1 of the booster circuit 6 does not become higher than necessary (it is kept at a constant voltage).

Note that the above embodiment can be formed integrally with the EEFROM chip, or can be formed as a separate member.

(b) Other Embodiments In the above-mentioned embodiments, the oscillation means 1 was constructed by a loop circuit, but in a microcomputer etc. equipped with a variable frequency oscillator (VFO) 21, as shown in FIG.
It is also possible to use the FO 21 as an oscillator and to adjust the oscillation frequency by connecting the output of the voltage detection means 12 to its control terminal.

〔Effect of the invention〕

As described above, the present invention detects the magnitude of the output voltage of the high voltage generating means and changes the voltage increase rate depending on the magnitude, so that not only no extra power is consumed in the oscillator, but also the EEFROM It is possible to eliminate the overshoot of the write voltage that destroys the circuit, and it is possible to omit the waveform shaping circuit.

In addition, since the voltage detection means is also used to output both the control signal and the voltage detection force, the circuit can be made into a cylinder.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing the principle of the present invention.
FIG. 4 is a block diagram showing another embodiment of the present invention, and FIG. 5 is a block diagram showing an example of a conventional device. (Explanation of symbols) l...Oscillation means, ~4...CPU. 6... Boosting means, 10... EEP/ROM cell array, 11... Constant voltage means, 12... Voltage detection means, 13... Reference voltage generation means, 14... Comparator, 17. ...delay means, 20...CR circuit, 21...variable frequency oscillator.杢′Loquat Silk Ichishinsa 匑匈j1 teyo, 1 ear → name) Calendar evil pulse 3rd figure chestnut 4 figure

Claims (1)

[Claims] Oscillating means (1); Boosting means (6) receiving the output of the oscillating means (1) and boosting an externally supplied power supply voltage to output a data writing voltage; connected to the output end of the boosting means (6);
) voltage detecting means (12) that divides the write voltage outputted by the voltage detecting means (12) and outputs the divided voltage to a plurality of output terminals; delay means (17) for controlling the oscillation frequency of the oscillation means (1) and the voltage increase rate of the boosting means (6) to decrease as the write voltage output from the voltage detection means increases; (12) Compares the voltage of one of the output terminals with a reference voltage, and includes a constant voltage means (11) that stops boosting when the write voltage reaches a predetermined value. A nonvolatile semiconductor memory device characterized by: